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+/** SerDes.c
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+ Provides SoC specific SerDes interface
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+
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+ Copyright 2017-2020 NXP
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+
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+ SPDX-License-Identifier: BSD-2-Clause-Patent
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+**/
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+
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+#include <Library/ChassisLib.h>
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+#include <Library/DebugLib.h>
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+#include <Library/SerDesHelperLib.h>
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+#include <SocSerDes.h>
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+#include <Soc.h>
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+#include <Uefi.h>
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+
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+// SerDes1 Protocol Mask in Reset Configuration Word (RCW) Status Register
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+#define SERDES1_PROTOCOL_MASK 0xffff0000
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+
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+// SerDes1 Protocol Shift in Reset Configuration Word (RCW) Status Register
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+#define SERDES1_PROTOCOL_SHIFT 16
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+
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+STATIC SERDES_CONFIG mSerDes1ConfigTable[] = {
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+ {0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3 } },
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+ {0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } },
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+ {0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3 } },
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+ {0x4558, {QSGMII_FM1_A, PCIE1, PCIE2, SATA } },
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+ {0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } },
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+ {0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } },
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+ {0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, PCIE3 } },
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+ {0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } },
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+ {0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA } },
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+ {0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } },
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+ {0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA } },
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+ {0x7000, {PCIE1, PCIE1, PCIE1, PCIE1 } },
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+ {0x9998, {PCIE1, PCIE2, PCIE3, SATA } },
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+ {0x6058, {PCIE1, PCIE1, PCIE2, SATA } },
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+ {0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3 } },
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+ {0x2455, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } },
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+ {0x2255, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC2, PCIE2, PCIE3 } },
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+ {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
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+ {0x1460, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE3, PCIE3 } },
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+ {0x2460, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } },
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+ {0x3460, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } },
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+ {0x3455, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } },
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+ {0x9960, {PCIE1, PCIE2, PCIE3, PCIE3 } },
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+ {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
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+ {0x2533, {SGMII_2500_FM1_DTSEC9, PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
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+ {}
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+};
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+
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+SERDES_CONFIG *gSerDesConfig[] = {
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+ mSerDes1ConfigTable
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+};
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+
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+/**
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+ Probe all SerDes for lane protocol and execute provided callback function.
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+
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+ @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol
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+ @param Arg Pointer to Arguments to be passed to callback function.
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+
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+**/
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+VOID
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+SerDesProbeLanes (
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+ IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
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+ IN VOID *Arg
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+ )
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+{
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+ UINT32 SerDesProtocol;
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+ LS1046A_DEVICE_CONFIG *DeviceConfig;
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+
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+ DeviceConfig = (LS1046A_DEVICE_CONFIG *)LS1046A_DCFG_ADDRESS;
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+ SerDesProtocol = DcfgRead32 ((UINTN)&DeviceConfig->RcwSr[4]) & SERDES1_PROTOCOL_MASK;
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+ SerDesProtocol >>= SERDES1_PROTOCOL_SHIFT;
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+
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+ SerDesInstanceProbeLanes (
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+ SERDES_1,
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+ SerDesProtocol,
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+ FixedPcdGet8 (PcdSerDesLanes),
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+ SERDES_PROTOCOL_COUNT,
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+ gSerDesConfig[SERDES_1],
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+ SerDesLaneProbeCallback,
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+ Arg
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+ );
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+}
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+
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+/**
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+ Function to return SerDes protocol map for all SerDes available on board.
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+
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+ @param SerDesProtocolMap Pointer to SerDes protocl map.
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+
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+**/
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+VOID
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+GetSerDesProtocolMap (
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+ OUT UINT64 *SerDesProtocolMap
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+ )
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+{
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+ UINT32 SerDesProtocol;
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+ LS1046A_DEVICE_CONFIG *DeviceConfig;
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+ EFI_STATUS Status;
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+
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+ *SerDesProtocolMap = 0;
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+ DeviceConfig = (LS1046A_DEVICE_CONFIG *)LS1046A_DCFG_ADDRESS;
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+ SerDesProtocol = DcfgRead32 ((UINTN)&DeviceConfig->RcwSr[4]) & SERDES1_PROTOCOL_MASK;
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+ SerDesProtocol >>= SERDES1_PROTOCOL_SHIFT;
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+
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+ Status = GetSerDesMap (
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+ SERDES_1,
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+ SerDesProtocol,
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+ FixedPcdGet8 (PcdSerDesLanes),
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+ SERDES_PROTOCOL_COUNT,
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+ gSerDesConfig[SERDES_1],
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+ SerDesProtocolMap
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+ );
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+
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+ if (Status != EFI_SUCCESS) {
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+ DEBUG ((DEBUG_ERROR, "%a: failed for SerDes1 \n",__FUNCTION__));
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+ *SerDesProtocolMap = 0;
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+ }
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+}
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