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@@ -1,1589 +0,0 @@
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-/** @file
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- Functions in this library instance make use of MMIO functions in IoLib to
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- access memory mapped PCI configuration space.
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-
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- All assertions for I/O operations are handled in MMIO functions in the IoLib
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- Library.
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-
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- Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
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-
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- On the NeoverseN1Soc, a slave error is generated when host accesses the
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- configuration space of non-available device or unimplemented function on a
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- given bus. So this library introduces a workaround using IsBdfValid(),
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- to return 0xFFFFFFFF for all such access.
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-
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- In addition to this, the hardware has two other limitations which affect
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- access to the PCIe root port:
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- 1. ECAM space is not contiguous, root port ECAM (BDF = 0:0:0) is isolated
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- from rest of the downstream hierarchy ECAM space.
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- 2. Root port ECAM space is not capable of 8bit/16bit writes.
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- The description of the workarounds included for these limitations can
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- be found in the comments below.
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-
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- Copyright (c) 2020, ARM Limited. All rights reserved.
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-
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- SPDX-License-Identifier: BSD-2-Clause-Patent
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-
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-**/
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-
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-
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-#include <Base.h>
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-
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-#include <Library/BaseLib.h>
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-#include <Library/PciExpressLib.h>
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-#include <Library/IoLib.h>
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-#include <Library/DebugLib.h>
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-#include <Library/PcdLib.h>
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-#include <NeoverseN1Soc.h>
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-
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-/**
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- Assert the validity of a PCI address. A valid PCI address should contain 1's
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- only in the low 28 bits.
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-
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- @param A The address to validate.
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-
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-**/
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-#define ASSERT_INVALID_PCI_ADDRESS(A) \
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- ASSERT (((A) & ~0xfffffff) == 0)
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-
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-/* Root port Entry, BDF Entries Count */
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-#define BDF_TABLE_ENTRY_SIZE 4
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-#define BDF_TABLE_HEADER_COUNT 2
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-#define BDF_TABLE_HEADER_SIZE 8
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-
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-/* BDF table offsets for PCIe */
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-#define PCIE_BDF_TABLE_OFFSET 0
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-
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-#define GET_BUS_NUM(Address) (((Address) >> 20) & 0x7F)
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-#define GET_DEV_NUM(Address) (((Address) >> 15) & 0x1F)
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-#define GET_FUNC_NUM(Address) (((Address) >> 12) & 0x07)
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-#define GET_REG_NUM(Address) ((Address) & 0xFFF)
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-
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-/**
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- BDF Table structure : (Header + BDF Entries)
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- --------------------------------------------
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- [Offset 0x00] ROOT PORT ADDRESS
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- [Offset 0x04] BDF ENTRIES COUNT
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- [Offset 0x08] BDF ENTRY 0
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- [Offset 0x0C] BDF ENTRY 1
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- [Offset 0x10] BDF ENTRY 2
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- [Offset 0x14] BDF ENTRY 3
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- [Offset 0x18] BDF ENTRY 4
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- ...
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- [Offset 0x--] BDF ENTRY N
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- --------------------------------------------
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-**/
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-
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-/**
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- Value returned for reads on configuration space of unimplemented
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- device functions.
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-**/
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-STATIC UINTN mDummyConfigData = 0xFFFFFFFF;
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-
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-/**
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- Registers a PCI device so PCI configuration registers may be accessed after
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- SetVirtualAddressMap().
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-
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- Registers the PCI device specified by Address so all the PCI configuration
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- registers associated with that PCI device may be accessed after SetVirtualAddressMap()
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- is called.
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-
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- If Address > 0x0FFFFFFF, then ASSERT().
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-
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- @param Address The address that encodes the PCI Bus, Device, Function and
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- Register.
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-
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- @retval RETURN_SUCCESS The PCI device was registered for runtime access.
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- @retval RETURN_UNSUPPORTED An attempt was made to call this function
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- after ExitBootServices().
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- @retval RETURN_UNSUPPORTED The resources required to access the PCI device
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- at runtime could not be mapped.
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- @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
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- complete the registration.
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-
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-**/
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-RETURN_STATUS
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-EFIAPI
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-PciExpressRegisterForRuntimeAccess (
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- IN UINTN Address
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- )
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-{
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- ASSERT_INVALID_PCI_ADDRESS (Address);
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- return RETURN_UNSUPPORTED;
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-}
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-
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-/**
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- Check if the requested PCI address can be safely accessed.
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-
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- SCP performs the initial bus scan, prepares a table of valid BDF addresses
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- and shares them through non-trusted SRAM. This function validates if the
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- requested PCI address belongs to a valid BDF by checking the table of valid
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- entries. If not, this function will return false. This is a workaround to
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- avoid bus fault that occurs when accessing unavailable PCI device due to
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- hardware bug.
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-
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- @param Address The address that encodes the PCI Bus, Device, Function and
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- Register.
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-
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- @return TRUE BDF can be accessed, valid.
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- @return FALSE BDF should not be accessed, invalid.
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-
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-**/
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-STATIC
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-BOOLEAN
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-IsBdfValid (
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- IN UINTN Address
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- )
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-{
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- UINTN BdfCount;
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- UINTN BdfValue;
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- UINTN BdfEntry;
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- UINTN Count;
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- UINTN TableBase;
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- UINTN ConfigBase;
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-
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- ConfigBase = Address & ~0xFFF;
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- TableBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + PCIE_BDF_TABLE_OFFSET;
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- BdfCount = MmioRead32 (TableBase + BDF_TABLE_ENTRY_SIZE);
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- BdfEntry = TableBase + BDF_TABLE_HEADER_SIZE;
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-
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- /* Skip the header & check remaining entry */
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- for (Count = 0; Count < BdfCount; Count++, BdfEntry += BDF_TABLE_ENTRY_SIZE) {
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- BdfValue = MmioRead32 (BdfEntry);
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- if (BdfValue == ConfigBase) {
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- return TRUE;
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- }
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- }
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-
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- return FALSE;
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-}
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-
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-/**
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- Get the physical address of a configuration space register.
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-
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- Implement a workaround to avoid generation of slave errors from the bus. That
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- is, retrieve the PCI Express Base Address via a PCD entry, add the incomming
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- address with that base address and check whether this converted address
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- points to a accessible BDF. If it is not accessible, return the address
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- of a dummy location so that a read from it does not cause a slave error.
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-
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- In addition to this, implement a workaround for accessing the root port's
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- configuration space. The root port configuration space is not contiguous
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- with the rest of the downstream hierarchy configuration space. So determine
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- whether the specified address is for the root port and use a different base
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- address for it.
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-
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- @param Address The address that encodes the PCI Bus, Device, Function and
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- Register.
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-
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- @return Physical address of the configuration register that corresponds to the
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- PCI configuration register specified by input parameter 'Address'.
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-
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-**/
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-STATIC
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-VOID*
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-GetPciExpressAddress (
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- IN UINTN Address
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- )
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-{
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- UINT8 Bus, Device, Function;
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- UINTN ConfigAddress;
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-
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- Bus = GET_BUS_NUM (Address);
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- Device = GET_DEV_NUM (Address);
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- Function = GET_FUNC_NUM (Address);
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-
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- if ((Bus == 0) && (Device == 0) && (Function == 0)) {
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- ConfigAddress = PcdGet32 (PcdPcieRootPortConfigBaseAddress) + Address;
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- } else {
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- ConfigAddress = PcdGet64 (PcdPciExpressBaseAddress) + Address;
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- if (!IsBdfValid(Address)) {
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- ConfigAddress = (UINTN)&mDummyConfigData;
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- }
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- }
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-
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- return (VOID *)ConfigAddress;
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-}
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-
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-/**
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- Reads an 8-bit PCI configuration register.
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-
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- Reads and returns the 8-bit PCI configuration register specified by Address.
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- This function must guarantee that all PCI read and write operations are
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- serialized.
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-
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- If Address > 0x0FFFFFFF, then ASSERT().
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-
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- @param Address The address that encodes the PCI Bus, Device, Function and
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- Register.
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-
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- @return The read value from the PCI configuration register.
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-
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-**/
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-UINT8
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-EFIAPI
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-PciExpressRead8 (
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- IN UINTN Address
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- )
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-{
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- ASSERT_INVALID_PCI_ADDRESS (Address);
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- return MmioRead8 ((UINTN)GetPciExpressAddress (Address));
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-}
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-
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-/**
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- Writes an 8-bit PCI configuration register.
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-
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- Writes the 8-bit PCI configuration register specified by Address with the
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- value specified by Value. Value is returned. This function must guarantee
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- that all PCI read and write operations are serialized.
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-
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- If Address > 0x0FFFFFFF, then ASSERT().
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-
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- @param Address The address that encodes the PCI Bus, Device, Function and
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- Register.
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- @param Value The value to write.
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-
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- @return The value written to the PCI configuration register.
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-
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-**/
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-UINT8
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-EFIAPI
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-PciExpressWrite8 (
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- IN UINTN Address,
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- IN UINT8 Value
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- )
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-{
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- UINT8 Bus, Device, Function;
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- UINT8 Offset;
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- UINT32 Data;
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-
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- ASSERT_INVALID_PCI_ADDRESS (Address);
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-
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- Bus = GET_BUS_NUM (Address);
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- Device = GET_DEV_NUM (Address);
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- Function = GET_FUNC_NUM (Address);
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-
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- //
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- // 8-bit and 16-bit writes to root port config space is not supported due to
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- // a hardware limitation. As a workaround, perform a read-update-write
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- // sequence on the whole 32-bit word of the root port config register such
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- // that only the specified 8-bits of that word are updated.
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- //
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- if ((Bus == 0) && (Device == 0) && (Function == 0)) {
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- Offset = Address & 0x3;
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- Address &= 0xFFFFFFFC;
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- Data = MmioRead32 ((UINTN)GetPciExpressAddress (Address));
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- Data &= ~(0xFF << (8 * Offset));
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- Data |= (Value << (8 * Offset));
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- MmioWrite32 ((UINTN)GetPciExpressAddress (Address), Data);
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- return Value;
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- }
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-
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- return MmioWrite8 ((UINTN)GetPciExpressAddress (Address), Value);
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-}
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-
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-/**
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- Performs a bitwise OR of an 8-bit PCI configuration register with
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- an 8-bit value.
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-
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- Reads the 8-bit PCI configuration register specified by Address, performs a
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- bitwise OR between the read result and the value specified by
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- OrData, and writes the result to the 8-bit PCI configuration register
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- specified by Address. The value written to the PCI configuration register is
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- returned. This function must guarantee that all PCI read and write operations
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- are serialized.
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-
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- If Address > 0x0FFFFFFF, then ASSERT().
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-
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- @param Address The address that encodes the PCI Bus, Device, Function and
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- Register.
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- @param OrData The value to OR with the PCI configuration register.
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-
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- @return The value written back to the PCI configuration register.
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-
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-**/
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-UINT8
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-EFIAPI
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-PciExpressOr8 (
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- IN UINTN Address,
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- IN UINT8 OrData
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- )
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-{
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- ASSERT_INVALID_PCI_ADDRESS (Address);
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- return MmioOr8 ((UINTN)GetPciExpressAddress (Address), OrData);
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-}
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-
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-/**
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- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
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- value.
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-
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- Reads the 8-bit PCI configuration register specified by Address, performs a
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- bitwise AND between the read result and the value specified by AndData, and
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- writes the result to the 8-bit PCI configuration register specified by
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- Address. The value written to the PCI configuration register is returned.
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- This function must guarantee that all PCI read and write operations are
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- serialized.
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-
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- If Address > 0x0FFFFFFF, then ASSERT().
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-
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- @param Address The address that encodes the PCI Bus, Device, Function and
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- Register.
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- @param AndData The value to AND with the PCI configuration register.
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-
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- @return The value written back to the PCI configuration register.
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-
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-**/
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-UINT8
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-EFIAPI
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-PciExpressAnd8 (
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- IN UINTN Address,
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- IN UINT8 AndData
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- )
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-{
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- ASSERT_INVALID_PCI_ADDRESS (Address);
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- return MmioAnd8 ((UINTN)GetPciExpressAddress (Address), AndData);
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-}
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-
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-/**
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- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
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- value, followed a bitwise OR with another 8-bit value.
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-
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- Reads the 8-bit PCI configuration register specified by Address, performs a
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- bitwise AND between the read result and the value specified by AndData,
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- performs a bitwise OR between the result of the AND operation and
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- the value specified by OrData, and writes the result to the 8-bit PCI
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- configuration register specified by Address. The value written to the PCI
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- configuration register is returned. This function must guarantee that all PCI
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- read and write operations are serialized.
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-
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- If Address > 0x0FFFFFFF, then ASSERT().
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-
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- @param Address The address that encodes the PCI Bus, Device, Function and
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- Register.
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- @param AndData The value to AND with the PCI configuration register.
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- @param OrData The value to OR with the result of the AND operation.
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-
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- @return The value written back to the PCI configuration register.
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-
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-**/
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-UINT8
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-EFIAPI
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-PciExpressAndThenOr8 (
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- IN UINTN Address,
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- IN UINT8 AndData,
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- IN UINT8 OrData
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- )
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-{
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- ASSERT_INVALID_PCI_ADDRESS (Address);
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- return MmioAndThenOr8 (
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- (UINTN)GetPciExpressAddress (Address),
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- AndData,
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- OrData
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- );
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-}
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-
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-/**
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- Reads a bit field of a PCI configuration register.
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-
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- Reads the bit field in an 8-bit PCI configuration register. The bit field is
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- specified by the StartBit and the EndBit. The value of the bit field is
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- returned.
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-
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- If Address > 0x0FFFFFFF, then ASSERT().
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- If StartBit is greater than 7, then ASSERT().
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- If EndBit is greater than 7, then ASSERT().
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- If EndBit is less than StartBit, then ASSERT().
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-
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- @param Address The PCI configuration register to read.
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- @param StartBit The ordinal of the least significant bit in the bit field.
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- Range 0..7.
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- @param EndBit The ordinal of the most significant bit in the bit field.
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- Range 0..7.
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-
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- @return The value of the bit field read from the PCI configuration register.
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-
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-**/
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-UINT8
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-EFIAPI
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-PciExpressBitFieldRead8 (
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- IN UINTN Address,
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- IN UINTN StartBit,
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- IN UINTN EndBit
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- )
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-{
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- ASSERT_INVALID_PCI_ADDRESS (Address);
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- return MmioBitFieldRead8 (
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- (UINTN)GetPciExpressAddress (Address),
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- StartBit,
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- EndBit
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- );
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-}
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-
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-/**
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- Writes a bit field to a PCI configuration register.
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-
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- Writes Value to the bit field of the PCI configuration register. The bit
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- field is specified by the StartBit and the EndBit. All other bits in the
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- destination PCI configuration register are preserved. The new value of the
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- 8-bit register is returned.
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-
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- If Address > 0x0FFFFFFF, then ASSERT().
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|
|
- If StartBit is greater than 7, then ASSERT().
|
|
|
- If EndBit is greater than 7, then ASSERT().
|
|
|
- If EndBit is less than StartBit, then ASSERT().
|
|
|
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
-
|
|
|
- @param Address The PCI configuration register to write.
|
|
|
- @param StartBit The ordinal of the least significant bit in the bit field.
|
|
|
- Range 0..7.
|
|
|
- @param EndBit The ordinal of the most significant bit in the bit field.
|
|
|
- Range 0..7.
|
|
|
- @param Value The new value of the bit field.
|
|
|
-
|
|
|
- @return The value written back to the PCI configuration register.
|
|
|
-
|
|
|
-**/
|
|
|
-UINT8
|
|
|
-EFIAPI
|
|
|
-PciExpressBitFieldWrite8 (
|
|
|
- IN UINTN Address,
|
|
|
- IN UINTN StartBit,
|
|
|
- IN UINTN EndBit,
|
|
|
- IN UINT8 Value
|
|
|
- )
|
|
|
-{
|
|
|
- ASSERT_INVALID_PCI_ADDRESS (Address);
|
|
|
- return MmioBitFieldWrite8 (
|
|
|
- (UINTN)GetPciExpressAddress (Address),
|
|
|
- StartBit,
|
|
|
- EndBit,
|
|
|
- Value
|
|
|
- );
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
|
|
|
- writes the result back to the bit field in the 8-bit port.
|
|
|
-
|
|
|
- Reads the 8-bit PCI configuration register specified by Address, performs a
|
|
|
- bitwise OR between the read result and the value specified by
|
|
|
- OrData, and writes the result to the 8-bit PCI configuration register
|
|
|
- specified by Address. The value written to the PCI configuration register is
|
|
|
- returned. This function must guarantee that all PCI read and write operations
|
|
|
- are serialized. Extra left bits in OrData are stripped.
|
|
|
-
|
|
|
- If Address > 0x0FFFFFFF, then ASSERT().
|
|
|
- If StartBit is greater than 7, then ASSERT().
|
|
|
- If EndBit is greater than 7, then ASSERT().
|
|
|
- If EndBit is less than StartBit, then ASSERT().
|
|
|
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
-
|
|
|
- @param Address The PCI configuration register to write.
|
|
|
- @param StartBit The ordinal of the least significant bit in the bit field.
|
|
|
- Range 0..7.
|
|
|
- @param EndBit The ordinal of the most significant bit in the bit field.
|
|
|
- Range 0..7.
|
|
|
- @param OrData The value to OR with the PCI configuration register.
|
|
|
-
|
|
|
- @return The value written back to the PCI configuration register.
|
|
|
-
|
|
|
-**/
|
|
|
-UINT8
|
|
|
-EFIAPI
|
|
|
-PciExpressBitFieldOr8 (
|
|
|
- IN UINTN Address,
|
|
|
- IN UINTN StartBit,
|
|
|
- IN UINTN EndBit,
|
|
|
- IN UINT8 OrData
|
|
|
- )
|
|
|
-{
|
|
|
- ASSERT_INVALID_PCI_ADDRESS (Address);
|
|
|
- return MmioBitFieldOr8 (
|
|
|
- (UINTN)GetPciExpressAddress (Address),
|
|
|
- StartBit,
|
|
|
- EndBit,
|
|
|
- OrData
|
|
|
- );
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
|
|
|
- AND, and writes the result back to the bit field in the 8-bit register.
|
|
|
-
|
|
|
- Reads the 8-bit PCI configuration register specified by Address, performs a
|
|
|
- bitwise AND between the read result and the value specified by AndData, and
|
|
|
- writes the result to the 8-bit PCI configuration register specified by
|
|
|
- Address. The value written to the PCI configuration register is returned.
|
|
|
- This function must guarantee that all PCI read and write operations are
|
|
|
- serialized. Extra left bits in AndData are stripped.
|
|
|
-
|
|
|
- If Address > 0x0FFFFFFF, then ASSERT().
|
|
|
- If StartBit is greater than 7, then ASSERT().
|
|
|
- If EndBit is greater than 7, then ASSERT().
|
|
|
- If EndBit is less than StartBit, then ASSERT().
|
|
|
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
-
|
|
|
- @param Address The PCI configuration register to write.
|
|
|
- @param StartBit The ordinal of the least significant bit in the bit field.
|
|
|
- Range 0..7.
|
|
|
- @param EndBit The ordinal of the most significant bit in the bit field.
|
|
|
- Range 0..7.
|
|
|
- @param AndData The value to AND with the PCI configuration register.
|
|
|
-
|
|
|
- @return The value written back to the PCI configuration register.
|
|
|
-
|
|
|
-**/
|
|
|
-UINT8
|
|
|
-EFIAPI
|
|
|
-PciExpressBitFieldAnd8 (
|
|
|
- IN UINTN Address,
|
|
|
- IN UINTN StartBit,
|
|
|
- IN UINTN EndBit,
|
|
|
- IN UINT8 AndData
|
|
|
- )
|
|
|
-{
|
|
|
- ASSERT_INVALID_PCI_ADDRESS (Address);
|
|
|
- return MmioBitFieldAnd8 (
|
|
|
- (UINTN)GetPciExpressAddress (Address),
|
|
|
- StartBit,
|
|
|
- EndBit,
|
|
|
- AndData
|
|
|
- );
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
|
|
|
- bitwise OR, and writes the result back to the bit field in the
|
|
|
- 8-bit port.
|
|
|
-
|
|
|
- Reads the 8-bit PCI configuration register specified by Address, performs a
|
|
|
- bitwise AND followed by a bitwise OR between the read result and
|
|
|
- the value specified by AndData, and writes the result to the 8-bit PCI
|
|
|
- configuration register specified by Address. The value written to the PCI
|
|
|
- configuration register is returned. This function must guarantee that all PCI
|
|
|
- read and write operations are serialized. Extra left bits in both AndData and
|
|
|
- OrData are stripped.
|
|
|
-
|
|
|
- If Address > 0x0FFFFFFF, then ASSERT().
|
|
|
- If StartBit is greater than 7, then ASSERT().
|
|
|
- If EndBit is greater than 7, then ASSERT().
|
|
|
- If EndBit is less than StartBit, then ASSERT().
|
|
|
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
-
|
|
|
- @param Address The PCI configuration register to write.
|
|
|
- @param StartBit The ordinal of the least significant bit in the bit field.
|
|
|
- Range 0..7.
|
|
|
- @param EndBit The ordinal of the most significant bit in the bit field.
|
|
|
- Range 0..7.
|
|
|
- @param AndData The value to AND with the PCI configuration register.
|
|
|
- @param OrData The value to OR with the result of the AND operation.
|
|
|
-
|
|
|
- @return The value written back to the PCI configuration register.
|
|
|
-
|
|
|
-**/
|
|
|
-UINT8
|
|
|
-EFIAPI
|
|
|
-PciExpressBitFieldAndThenOr8 (
|
|
|
- IN UINTN Address,
|
|
|
- IN UINTN StartBit,
|
|
|
- IN UINTN EndBit,
|
|
|
- IN UINT8 AndData,
|
|
|
- IN UINT8 OrData
|
|
|
- )
|
|
|
-{
|
|
|
- ASSERT_INVALID_PCI_ADDRESS (Address);
|
|
|
- return MmioBitFieldAndThenOr8 (
|
|
|
- (UINTN)GetPciExpressAddress (Address),
|
|
|
- StartBit,
|
|
|
- EndBit,
|
|
|
- AndData,
|
|
|
- OrData
|
|
|
- );
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- Reads a 16-bit PCI configuration register.
|
|
|
-
|
|
|
- Reads and returns the 16-bit PCI configuration register specified by Address.
|
|
|
- This function must guarantee that all PCI read and write operations are
|
|
|
- serialized.
|
|
|
-
|
|
|
- If Address > 0x0FFFFFFF, then ASSERT().
|
|
|
- If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
|
-
|
|
|
- @param Address The address that encodes the PCI Bus, Device, Function and
|
|
|
- Register.
|
|
|
-
|
|
|
- @return The read value from the PCI configuration register.
|
|
|
-
|
|
|
-**/
|
|
|
-UINT16
|
|
|
-EFIAPI
|
|
|
-PciExpressRead16 (
|
|
|
- IN UINTN Address
|
|
|
- )
|
|
|
-{
|
|
|
- ASSERT_INVALID_PCI_ADDRESS (Address);
|
|
|
- return MmioRead16 ((UINTN)GetPciExpressAddress (Address));
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- Writes a 16-bit PCI configuration register.
|
|
|
-
|
|
|
- Writes the 16-bit PCI configuration register specified by Address with the
|
|
|
- value specified by Value. Value is returned. This function must guarantee
|
|
|
- that all PCI read and write operations are serialized.
|
|
|
-
|
|
|
- If Address > 0x0FFFFFFF, then ASSERT().
|
|
|
- If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
|
-
|
|
|
- @param Address The address that encodes the PCI Bus, Device, Function and
|
|
|
- Register.
|
|
|
- @param Value The value to write.
|
|
|
-
|
|
|
- @return The value written to the PCI configuration register.
|
|
|
-
|
|
|
-**/
|
|
|
-UINT16
|
|
|
-EFIAPI
|
|
|
-PciExpressWrite16 (
|
|
|
- IN UINTN Address,
|
|
|
- IN UINT16 Value
|
|
|
- )
|
|
|
-{
|
|
|
- UINT8 Bus, Device, Function;
|
|
|
- UINT8 Offset;
|
|
|
- UINT32 Data;
|
|
|
-
|
|
|
- ASSERT_INVALID_PCI_ADDRESS (Address);
|
|
|
-
|
|
|
- Bus = GET_BUS_NUM (Address);
|
|
|
- Device = GET_DEV_NUM (Address);
|
|
|
- Function = GET_FUNC_NUM (Address);
|
|
|
-
|
|
|
- //
|
|
|
- // 8-bit and 16-bit writes to root port config space is not supported due to
|
|
|
- // a hardware limitation. As a workaround, perform a read-update-write
|
|
|
- // sequence on the whole 32-bit word of the root port config register such
|
|
|
- // that only the specified 16-bits of that word are updated.
|
|
|
- //
|
|
|
- if ((Bus == 0) && (Device == 0) && (Function == 0)) {
|
|
|
- Offset = Address & 0x3;
|
|
|
- Address &= 0xFFFFFFFC;
|
|
|
- Data = MmioRead32 ((UINTN)GetPciExpressAddress (Address));
|
|
|
- Data &= ~(0xFFFF << (8 * Offset));
|
|
|
- Data |= (Value << (8 * Offset));
|
|
|
- MmioWrite32 ((UINTN)GetPciExpressAddress (Address), Data);
|
|
|
- return Value;
|
|
|
- }
|
|
|
-
|
|
|
- return MmioWrite16 ((UINTN)GetPciExpressAddress (Address), Value);
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- Performs a bitwise OR of a 16-bit PCI configuration register with
|
|
|
- a 16-bit value.
|
|
|
-
|
|
|
- Reads the 16-bit PCI configuration register specified by Address, performs a
|
|
|
- bitwise OR between the read result and the value specified by
|
|
|
- OrData, and writes the result to the 16-bit PCI configuration register
|
|
|
- specified by Address. The value written to the PCI configuration register is
|
|
|
- returned. This function must guarantee that all PCI read and write operations
|
|
|
- are serialized.
|
|
|
-
|
|
|
- If Address > 0x0FFFFFFF, then ASSERT().
|
|
|
- If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
|
-
|
|
|
- @param Address The address that encodes the PCI Bus, Device, Function and
|
|
|
- Register.
|
|
|
- @param OrData The value to OR with the PCI configuration register.
|
|
|
-
|
|
|
- @return The value written back to the PCI configuration register.
|
|
|
-
|
|
|
-**/
|
|
|
-UINT16
|
|
|
-EFIAPI
|
|
|
-PciExpressOr16 (
|
|
|
- IN UINTN Address,
|
|
|
- IN UINT16 OrData
|
|
|
- )
|
|
|
-{
|
|
|
- ASSERT_INVALID_PCI_ADDRESS (Address);
|
|
|
- return MmioOr16 ((UINTN)GetPciExpressAddress (Address), OrData);
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
|
|
|
- value.
|
|
|
-
|
|
|
- Reads the 16-bit PCI configuration register specified by Address, performs a
|
|
|
- bitwise AND between the read result and the value specified by AndData, and
|
|
|
- writes the result to the 16-bit PCI configuration register specified by
|
|
|
- Address. The value written to the PCI configuration register is returned.
|
|
|
- This function must guarantee that all PCI read and write operations are
|
|
|
- serialized.
|
|
|
-
|
|
|
- If Address > 0x0FFFFFFF, then ASSERT().
|
|
|
- If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
|
-
|
|
|
- @param Address The address that encodes the PCI Bus, Device, Function and
|
|
|
- Register.
|
|
|
- @param AndData The value to AND with the PCI configuration register.
|
|
|
-
|
|
|
- @return The value written back to the PCI configuration register.
|
|
|
-
|
|
|
-**/
|
|
|
-UINT16
|
|
|
-EFIAPI
|
|
|
-PciExpressAnd16 (
|
|
|
- IN UINTN Address,
|
|
|
- IN UINT16 AndData
|
|
|
- )
|
|
|
-{
|
|
|
- ASSERT_INVALID_PCI_ADDRESS (Address);
|
|
|
- return MmioAnd16 ((UINTN)GetPciExpressAddress (Address), AndData);
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
|
|
|
- value, followed a bitwise OR with another 16-bit value.
|
|
|
-
|
|
|
- Reads the 16-bit PCI configuration register specified by Address, performs a
|
|
|
- bitwise AND between the read result and the value specified by AndData,
|
|
|
- performs a bitwise OR between the result of the AND operation and
|
|
|
- the value specified by OrData, and writes the result to the 16-bit PCI
|
|
|
- configuration register specified by Address. The value written to the PCI
|
|
|
- configuration register is returned. This function must guarantee that all PCI
|
|
|
- read and write operations are serialized.
|
|
|
-
|
|
|
- If Address > 0x0FFFFFFF, then ASSERT().
|
|
|
- If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
|
-
|
|
|
- @param Address The address that encodes the PCI Bus, Device, Function and
|
|
|
- Register.
|
|
|
- @param AndData The value to AND with the PCI configuration register.
|
|
|
- @param OrData The value to OR with the result of the AND operation.
|
|
|
-
|
|
|
- @return The value written back to the PCI configuration register.
|
|
|
-
|
|
|
-**/
|
|
|
-UINT16
|
|
|
-EFIAPI
|
|
|
-PciExpressAndThenOr16 (
|
|
|
- IN UINTN Address,
|
|
|
- IN UINT16 AndData,
|
|
|
- IN UINT16 OrData
|
|
|
- )
|
|
|
-{
|
|
|
- ASSERT_INVALID_PCI_ADDRESS (Address);
|
|
|
- return MmioAndThenOr16 (
|
|
|
- (UINTN)GetPciExpressAddress (Address),
|
|
|
- AndData,
|
|
|
- OrData
|
|
|
- );
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- Reads a bit field of a PCI configuration register.
|
|
|
-
|
|
|
- Reads the bit field in a 16-bit PCI configuration register. The bit field is
|
|
|
- specified by the StartBit and the EndBit. The value of the bit field is
|
|
|
- returned.
|
|
|
-
|
|
|
- If Address > 0x0FFFFFFF, then ASSERT().
|
|
|
- If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
|
- If StartBit is greater than 15, then ASSERT().
|
|
|
- If EndBit is greater than 15, then ASSERT().
|
|
|
- If EndBit is less than StartBit, then ASSERT().
|
|
|
-
|
|
|
- @param Address The PCI configuration register to read.
|
|
|
- @param StartBit The ordinal of the least significant bit in the bit field.
|
|
|
- Range 0..15.
|
|
|
- @param EndBit The ordinal of the most significant bit in the bit field.
|
|
|
- Range 0..15.
|
|
|
-
|
|
|
- @return The value of the bit field read from the PCI configuration register.
|
|
|
-
|
|
|
-**/
|
|
|
-UINT16
|
|
|
-EFIAPI
|
|
|
-PciExpressBitFieldRead16 (
|
|
|
- IN UINTN Address,
|
|
|
- IN UINTN StartBit,
|
|
|
- IN UINTN EndBit
|
|
|
- )
|
|
|
-{
|
|
|
- ASSERT_INVALID_PCI_ADDRESS (Address);
|
|
|
- return MmioBitFieldRead16 (
|
|
|
- (UINTN)GetPciExpressAddress (Address),
|
|
|
- StartBit,
|
|
|
- EndBit
|
|
|
- );
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- Writes a bit field to a PCI configuration register.
|
|
|
-
|
|
|
- Writes Value to the bit field of the PCI configuration register. The bit
|
|
|
- field is specified by the StartBit and the EndBit. All other bits in the
|
|
|
- destination PCI configuration register are preserved. The new value of the
|
|
|
- 16-bit register is returned.
|
|
|
-
|
|
|
- If Address > 0x0FFFFFFF, then ASSERT().
|
|
|
- If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
|
- If StartBit is greater than 15, then ASSERT().
|
|
|
- If EndBit is greater than 15, then ASSERT().
|
|
|
- If EndBit is less than StartBit, then ASSERT().
|
|
|
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
-
|
|
|
- @param Address The PCI configuration register to write.
|
|
|
- @param StartBit The ordinal of the least significant bit in the bit field.
|
|
|
- Range 0..15.
|
|
|
- @param EndBit The ordinal of the most significant bit in the bit field.
|
|
|
- Range 0..15.
|
|
|
- @param Value The new value of the bit field.
|
|
|
-
|
|
|
- @return The value written back to the PCI configuration register.
|
|
|
-
|
|
|
-**/
|
|
|
-UINT16
|
|
|
-EFIAPI
|
|
|
-PciExpressBitFieldWrite16 (
|
|
|
- IN UINTN Address,
|
|
|
- IN UINTN StartBit,
|
|
|
- IN UINTN EndBit,
|
|
|
- IN UINT16 Value
|
|
|
- )
|
|
|
-{
|
|
|
- ASSERT_INVALID_PCI_ADDRESS (Address);
|
|
|
- return MmioBitFieldWrite16 (
|
|
|
- (UINTN)GetPciExpressAddress (Address),
|
|
|
- StartBit,
|
|
|
- EndBit,
|
|
|
- Value
|
|
|
- );
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
|
|
|
- writes the result back to the bit field in the 16-bit port.
|
|
|
-
|
|
|
- Reads the 16-bit PCI configuration register specified by Address, performs a
|
|
|
- bitwise OR between the read result and the value specified by
|
|
|
- OrData, and writes the result to the 16-bit PCI configuration register
|
|
|
- specified by Address. The value written to the PCI configuration register is
|
|
|
- returned. This function must guarantee that all PCI read and write operations
|
|
|
- are serialized. Extra left bits in OrData are stripped.
|
|
|
-
|
|
|
- If Address > 0x0FFFFFFF, then ASSERT().
|
|
|
- If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
|
- If StartBit is greater than 15, then ASSERT().
|
|
|
- If EndBit is greater than 15, then ASSERT().
|
|
|
- If EndBit is less than StartBit, then ASSERT().
|
|
|
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
-
|
|
|
- @param Address The PCI configuration register to write.
|
|
|
- @param StartBit The ordinal of the least significant bit in the bit field.
|
|
|
- Range 0..15.
|
|
|
- @param EndBit The ordinal of the most significant bit in the bit field.
|
|
|
- Range 0..15.
|
|
|
- @param OrData The value to OR with the PCI configuration register.
|
|
|
-
|
|
|
- @return The value written back to the PCI configuration register.
|
|
|
-
|
|
|
-**/
|
|
|
-UINT16
|
|
|
-EFIAPI
|
|
|
-PciExpressBitFieldOr16 (
|
|
|
- IN UINTN Address,
|
|
|
- IN UINTN StartBit,
|
|
|
- IN UINTN EndBit,
|
|
|
- IN UINT16 OrData
|
|
|
- )
|
|
|
-{
|
|
|
- ASSERT_INVALID_PCI_ADDRESS (Address);
|
|
|
- return MmioBitFieldOr16 (
|
|
|
- (UINTN)GetPciExpressAddress (Address),
|
|
|
- StartBit,
|
|
|
- EndBit,
|
|
|
- OrData
|
|
|
- );
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
|
|
|
- AND, and writes the result back to the bit field in the 16-bit register.
|
|
|
-
|
|
|
- Reads the 16-bit PCI configuration register specified by Address, performs a
|
|
|
- bitwise AND between the read result and the value specified by AndData, and
|
|
|
- writes the result to the 16-bit PCI configuration register specified by
|
|
|
- Address. The value written to the PCI configuration register is returned.
|
|
|
- This function must guarantee that all PCI read and write operations are
|
|
|
- serialized. Extra left bits in AndData are stripped.
|
|
|
-
|
|
|
- If Address > 0x0FFFFFFF, then ASSERT().
|
|
|
- If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
|
- If StartBit is greater than 15, then ASSERT().
|
|
|
- If EndBit is greater than 15, then ASSERT().
|
|
|
- If EndBit is less than StartBit, then ASSERT().
|
|
|
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
-
|
|
|
- @param Address The PCI configuration register to write.
|
|
|
- @param StartBit The ordinal of the least significant bit in the bit field.
|
|
|
- Range 0..15.
|
|
|
- @param EndBit The ordinal of the most significant bit in the bit field.
|
|
|
- Range 0..15.
|
|
|
- @param AndData The value to AND with the PCI configuration register.
|
|
|
-
|
|
|
- @return The value written back to the PCI configuration register.
|
|
|
-
|
|
|
-**/
|
|
|
-UINT16
|
|
|
-EFIAPI
|
|
|
-PciExpressBitFieldAnd16 (
|
|
|
- IN UINTN Address,
|
|
|
- IN UINTN StartBit,
|
|
|
- IN UINTN EndBit,
|
|
|
- IN UINT16 AndData
|
|
|
- )
|
|
|
-{
|
|
|
- ASSERT_INVALID_PCI_ADDRESS (Address);
|
|
|
- return MmioBitFieldAnd16 (
|
|
|
- (UINTN)GetPciExpressAddress (Address),
|
|
|
- StartBit,
|
|
|
- EndBit,
|
|
|
- AndData
|
|
|
- );
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
|
|
|
- bitwise OR, and writes the result back to the bit field in the
|
|
|
- 16-bit port.
|
|
|
-
|
|
|
- Reads the 16-bit PCI configuration register specified by Address, performs a
|
|
|
- bitwise AND followed by a bitwise OR between the read result and
|
|
|
- the value specified by AndData, and writes the result to the 16-bit PCI
|
|
|
- configuration register specified by Address. The value written to the PCI
|
|
|
- configuration register is returned. This function must guarantee that all PCI
|
|
|
- read and write operations are serialized. Extra left bits in both AndData and
|
|
|
- OrData are stripped.
|
|
|
-
|
|
|
- If Address > 0x0FFFFFFF, then ASSERT().
|
|
|
- If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
|
- If StartBit is greater than 15, then ASSERT().
|
|
|
- If EndBit is greater than 15, then ASSERT().
|
|
|
- If EndBit is less than StartBit, then ASSERT().
|
|
|
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
-
|
|
|
- @param Address The PCI configuration register to write.
|
|
|
- @param StartBit The ordinal of the least significant bit in the bit field.
|
|
|
- Range 0..15.
|
|
|
- @param EndBit The ordinal of the most significant bit in the bit field.
|
|
|
- Range 0..15.
|
|
|
- @param AndData The value to AND with the PCI configuration register.
|
|
|
- @param OrData The value to OR with the result of the AND operation.
|
|
|
-
|
|
|
- @return The value written back to the PCI configuration register.
|
|
|
-
|
|
|
-**/
|
|
|
-UINT16
|
|
|
-EFIAPI
|
|
|
-PciExpressBitFieldAndThenOr16 (
|
|
|
- IN UINTN Address,
|
|
|
- IN UINTN StartBit,
|
|
|
- IN UINTN EndBit,
|
|
|
- IN UINT16 AndData,
|
|
|
- IN UINT16 OrData
|
|
|
- )
|
|
|
-{
|
|
|
- ASSERT_INVALID_PCI_ADDRESS (Address);
|
|
|
- return MmioBitFieldAndThenOr16 (
|
|
|
- (UINTN)GetPciExpressAddress (Address),
|
|
|
- StartBit,
|
|
|
- EndBit,
|
|
|
- AndData,
|
|
|
- OrData
|
|
|
- );
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- Reads a 32-bit PCI configuration register.
|
|
|
-
|
|
|
- Reads and returns the 32-bit PCI configuration register specified by Address.
|
|
|
- This function must guarantee that all PCI read and write operations are
|
|
|
- serialized.
|
|
|
-
|
|
|
- If Address > 0x0FFFFFFF, then ASSERT().
|
|
|
- If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
|
-
|
|
|
- @param Address The address that encodes the PCI Bus, Device, Function and
|
|
|
- Register.
|
|
|
-
|
|
|
- @return The read value from the PCI configuration register.
|
|
|
-
|
|
|
-**/
|
|
|
-UINT32
|
|
|
-EFIAPI
|
|
|
-PciExpressRead32 (
|
|
|
- IN UINTN Address
|
|
|
- )
|
|
|
-{
|
|
|
- ASSERT_INVALID_PCI_ADDRESS (Address);
|
|
|
- return MmioRead32 ((UINTN)GetPciExpressAddress (Address));
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- Writes a 32-bit PCI configuration register.
|
|
|
-
|
|
|
- Writes the 32-bit PCI configuration register specified by Address with the
|
|
|
- value specified by Value. Value is returned. This function must guarantee
|
|
|
- that all PCI read and write operations are serialized.
|
|
|
-
|
|
|
- If Address > 0x0FFFFFFF, then ASSERT().
|
|
|
- If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
|
-
|
|
|
- @param Address The address that encodes the PCI Bus, Device, Function and
|
|
|
- Register.
|
|
|
- @param Value The value to write.
|
|
|
-
|
|
|
- @return The value written to the PCI configuration register.
|
|
|
-
|
|
|
-**/
|
|
|
-UINT32
|
|
|
-EFIAPI
|
|
|
-PciExpressWrite32 (
|
|
|
- IN UINTN Address,
|
|
|
- IN UINT32 Value
|
|
|
- )
|
|
|
-{
|
|
|
- ASSERT_INVALID_PCI_ADDRESS (Address);
|
|
|
- return MmioWrite32 ((UINTN)GetPciExpressAddress (Address), Value);
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- Performs a bitwise OR of a 32-bit PCI configuration register with
|
|
|
- a 32-bit value.
|
|
|
-
|
|
|
- Reads the 32-bit PCI configuration register specified by Address, performs a
|
|
|
- bitwise OR between the read result and the value specified by
|
|
|
- OrData, and writes the result to the 32-bit PCI configuration register
|
|
|
- specified by Address. The value written to the PCI configuration register is
|
|
|
- returned. This function must guarantee that all PCI read and write operations
|
|
|
- are serialized.
|
|
|
-
|
|
|
- If Address > 0x0FFFFFFF, then ASSERT().
|
|
|
- If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
|
-
|
|
|
- @param Address The address that encodes the PCI Bus, Device, Function and
|
|
|
- Register.
|
|
|
- @param OrData The value to OR with the PCI configuration register.
|
|
|
-
|
|
|
- @return The value written back to the PCI configuration register.
|
|
|
-
|
|
|
-**/
|
|
|
-UINT32
|
|
|
-EFIAPI
|
|
|
-PciExpressOr32 (
|
|
|
- IN UINTN Address,
|
|
|
- IN UINT32 OrData
|
|
|
- )
|
|
|
-{
|
|
|
- ASSERT_INVALID_PCI_ADDRESS (Address);
|
|
|
- return MmioOr32 ((UINTN)GetPciExpressAddress (Address), OrData);
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
|
|
|
- value.
|
|
|
-
|
|
|
- Reads the 32-bit PCI configuration register specified by Address, performs a
|
|
|
- bitwise AND between the read result and the value specified by AndData, and
|
|
|
- writes the result to the 32-bit PCI configuration register specified by
|
|
|
- Address. The value written to the PCI configuration register is returned.
|
|
|
- This function must guarantee that all PCI read and write operations are
|
|
|
- serialized.
|
|
|
-
|
|
|
- If Address > 0x0FFFFFFF, then ASSERT().
|
|
|
- If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
|
-
|
|
|
- @param Address The address that encodes the PCI Bus, Device, Function and
|
|
|
- Register.
|
|
|
- @param AndData The value to AND with the PCI configuration register.
|
|
|
-
|
|
|
- @return The value written back to the PCI configuration register.
|
|
|
-
|
|
|
-**/
|
|
|
-UINT32
|
|
|
-EFIAPI
|
|
|
-PciExpressAnd32 (
|
|
|
- IN UINTN Address,
|
|
|
- IN UINT32 AndData
|
|
|
- )
|
|
|
-{
|
|
|
- ASSERT_INVALID_PCI_ADDRESS (Address);
|
|
|
- return MmioAnd32 ((UINTN)GetPciExpressAddress (Address), AndData);
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
|
|
|
- value, followed a bitwise OR with another 32-bit value.
|
|
|
-
|
|
|
- Reads the 32-bit PCI configuration register specified by Address, performs a
|
|
|
- bitwise AND between the read result and the value specified by AndData,
|
|
|
- performs a bitwise OR between the result of the AND operation and
|
|
|
- the value specified by OrData, and writes the result to the 32-bit PCI
|
|
|
- configuration register specified by Address. The value written to the PCI
|
|
|
- configuration register is returned. This function must guarantee that all PCI
|
|
|
- read and write operations are serialized.
|
|
|
-
|
|
|
- If Address > 0x0FFFFFFF, then ASSERT().
|
|
|
- If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
|
-
|
|
|
- @param Address The address that encodes the PCI Bus, Device, Function and
|
|
|
- Register.
|
|
|
- @param AndData The value to AND with the PCI configuration register.
|
|
|
- @param OrData The value to OR with the result of the AND operation.
|
|
|
-
|
|
|
- @return The value written back to the PCI configuration register.
|
|
|
-
|
|
|
-**/
|
|
|
-UINT32
|
|
|
-EFIAPI
|
|
|
-PciExpressAndThenOr32 (
|
|
|
- IN UINTN Address,
|
|
|
- IN UINT32 AndData,
|
|
|
- IN UINT32 OrData
|
|
|
- )
|
|
|
-{
|
|
|
- ASSERT_INVALID_PCI_ADDRESS (Address);
|
|
|
- return MmioAndThenOr32 (
|
|
|
- (UINTN)GetPciExpressAddress (Address),
|
|
|
- AndData,
|
|
|
- OrData
|
|
|
- );
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- Reads a bit field of a PCI configuration register.
|
|
|
-
|
|
|
- Reads the bit field in a 32-bit PCI configuration register. The bit field is
|
|
|
- specified by the StartBit and the EndBit. The value of the bit field is
|
|
|
- returned.
|
|
|
-
|
|
|
- If Address > 0x0FFFFFFF, then ASSERT().
|
|
|
- If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
|
- If StartBit is greater than 31, then ASSERT().
|
|
|
- If EndBit is greater than 31, then ASSERT().
|
|
|
- If EndBit is less than StartBit, then ASSERT().
|
|
|
-
|
|
|
- @param Address The PCI configuration register to read.
|
|
|
- @param StartBit The ordinal of the least significant bit in the bit field.
|
|
|
- Range 0..31.
|
|
|
- @param EndBit The ordinal of the most significant bit in the bit field.
|
|
|
- Range 0..31.
|
|
|
-
|
|
|
- @return The value of the bit field read from the PCI configuration register.
|
|
|
-
|
|
|
-**/
|
|
|
-UINT32
|
|
|
-EFIAPI
|
|
|
-PciExpressBitFieldRead32 (
|
|
|
- IN UINTN Address,
|
|
|
- IN UINTN StartBit,
|
|
|
- IN UINTN EndBit
|
|
|
- )
|
|
|
-{
|
|
|
- ASSERT_INVALID_PCI_ADDRESS (Address);
|
|
|
- return MmioBitFieldRead32 (
|
|
|
- (UINTN)GetPciExpressAddress (Address),
|
|
|
- StartBit,
|
|
|
- EndBit
|
|
|
- );
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- Writes a bit field to a PCI configuration register.
|
|
|
-
|
|
|
- Writes Value to the bit field of the PCI configuration register. The bit
|
|
|
- field is specified by the StartBit and the EndBit. All other bits in the
|
|
|
- destination PCI configuration register are preserved. The new value of the
|
|
|
- 32-bit register is returned.
|
|
|
-
|
|
|
- If Address > 0x0FFFFFFF, then ASSERT().
|
|
|
- If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
|
- If StartBit is greater than 31, then ASSERT().
|
|
|
- If EndBit is greater than 31, then ASSERT().
|
|
|
- If EndBit is less than StartBit, then ASSERT().
|
|
|
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
-
|
|
|
- @param Address The PCI configuration register to write.
|
|
|
- @param StartBit The ordinal of the least significant bit in the bit field.
|
|
|
- Range 0..31.
|
|
|
- @param EndBit The ordinal of the most significant bit in the bit field.
|
|
|
- Range 0..31.
|
|
|
- @param Value The new value of the bit field.
|
|
|
-
|
|
|
- @return The value written back to the PCI configuration register.
|
|
|
-
|
|
|
-**/
|
|
|
-UINT32
|
|
|
-EFIAPI
|
|
|
-PciExpressBitFieldWrite32 (
|
|
|
- IN UINTN Address,
|
|
|
- IN UINTN StartBit,
|
|
|
- IN UINTN EndBit,
|
|
|
- IN UINT32 Value
|
|
|
- )
|
|
|
-{
|
|
|
- ASSERT_INVALID_PCI_ADDRESS (Address);
|
|
|
- return MmioBitFieldWrite32 (
|
|
|
- (UINTN)GetPciExpressAddress (Address),
|
|
|
- StartBit,
|
|
|
- EndBit,
|
|
|
- Value
|
|
|
- );
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
|
|
|
- writes the result back to the bit field in the 32-bit port.
|
|
|
-
|
|
|
- Reads the 32-bit PCI configuration register specified by Address, performs a
|
|
|
- bitwise OR between the read result and the value specified by
|
|
|
- OrData, and writes the result to the 32-bit PCI configuration register
|
|
|
- specified by Address. The value written to the PCI configuration register is
|
|
|
- returned. This function must guarantee that all PCI read and write operations
|
|
|
- are serialized. Extra left bits in OrData are stripped.
|
|
|
-
|
|
|
- If Address > 0x0FFFFFFF, then ASSERT().
|
|
|
- If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
|
- If StartBit is greater than 31, then ASSERT().
|
|
|
- If EndBit is greater than 31, then ASSERT().
|
|
|
- If EndBit is less than StartBit, then ASSERT().
|
|
|
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
-
|
|
|
- @param Address The PCI configuration register to write.
|
|
|
- @param StartBit The ordinal of the least significant bit in the bit field.
|
|
|
- Range 0..31.
|
|
|
- @param EndBit The ordinal of the most significant bit in the bit field.
|
|
|
- Range 0..31.
|
|
|
- @param OrData The value to OR with the PCI configuration register.
|
|
|
-
|
|
|
- @return The value written back to the PCI configuration register.
|
|
|
-
|
|
|
-**/
|
|
|
-UINT32
|
|
|
-EFIAPI
|
|
|
-PciExpressBitFieldOr32 (
|
|
|
- IN UINTN Address,
|
|
|
- IN UINTN StartBit,
|
|
|
- IN UINTN EndBit,
|
|
|
- IN UINT32 OrData
|
|
|
- )
|
|
|
-{
|
|
|
- ASSERT_INVALID_PCI_ADDRESS (Address);
|
|
|
- return MmioBitFieldOr32 (
|
|
|
- (UINTN)GetPciExpressAddress (Address),
|
|
|
- StartBit,
|
|
|
- EndBit,
|
|
|
- OrData
|
|
|
- );
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
|
|
|
- AND, and writes the result back to the bit field in the 32-bit register.
|
|
|
-
|
|
|
- Reads the 32-bit PCI configuration register specified by Address, performs a
|
|
|
- bitwise AND between the read result and the value specified by AndData, and
|
|
|
- writes the result to the 32-bit PCI configuration register specified by
|
|
|
- Address. The value written to the PCI configuration register is returned.
|
|
|
- This function must guarantee that all PCI read and write operations are
|
|
|
- serialized. Extra left bits in AndData are stripped.
|
|
|
-
|
|
|
- If Address > 0x0FFFFFFF, then ASSERT().
|
|
|
- If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
|
- If StartBit is greater than 31, then ASSERT().
|
|
|
- If EndBit is greater than 31, then ASSERT().
|
|
|
- If EndBit is less than StartBit, then ASSERT().
|
|
|
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
-
|
|
|
- @param Address The PCI configuration register to write.
|
|
|
- @param StartBit The ordinal of the least significant bit in the bit field.
|
|
|
- Range 0..31.
|
|
|
- @param EndBit The ordinal of the most significant bit in the bit field.
|
|
|
- Range 0..31.
|
|
|
- @param AndData The value to AND with the PCI configuration register.
|
|
|
-
|
|
|
- @return The value written back to the PCI configuration register.
|
|
|
-
|
|
|
-**/
|
|
|
-UINT32
|
|
|
-EFIAPI
|
|
|
-PciExpressBitFieldAnd32 (
|
|
|
- IN UINTN Address,
|
|
|
- IN UINTN StartBit,
|
|
|
- IN UINTN EndBit,
|
|
|
- IN UINT32 AndData
|
|
|
- )
|
|
|
-{
|
|
|
- ASSERT_INVALID_PCI_ADDRESS (Address);
|
|
|
- return MmioBitFieldAnd32 (
|
|
|
- (UINTN)GetPciExpressAddress (Address),
|
|
|
- StartBit,
|
|
|
- EndBit,
|
|
|
- AndData
|
|
|
- );
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
|
|
|
- bitwise OR, and writes the result back to the bit field in the
|
|
|
- 32-bit port.
|
|
|
-
|
|
|
- Reads the 32-bit PCI configuration register specified by Address, performs a
|
|
|
- bitwise AND followed by a bitwise OR between the read result and
|
|
|
- the value specified by AndData, and writes the result to the 32-bit PCI
|
|
|
- configuration register specified by Address. The value written to the PCI
|
|
|
- configuration register is returned. This function must guarantee that all PCI
|
|
|
- read and write operations are serialized. Extra left bits in both AndData and
|
|
|
- OrData are stripped.
|
|
|
-
|
|
|
- If Address > 0x0FFFFFFF, then ASSERT().
|
|
|
- If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
|
- If StartBit is greater than 31, then ASSERT().
|
|
|
- If EndBit is greater than 31, then ASSERT().
|
|
|
- If EndBit is less than StartBit, then ASSERT().
|
|
|
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
-
|
|
|
- @param Address The PCI configuration register to write.
|
|
|
- @param StartBit The ordinal of the least significant bit in the bit field.
|
|
|
- Range 0..31.
|
|
|
- @param EndBit The ordinal of the most significant bit in the bit field.
|
|
|
- Range 0..31.
|
|
|
- @param AndData The value to AND with the PCI configuration register.
|
|
|
- @param OrData The value to OR with the result of the AND operation.
|
|
|
-
|
|
|
- @return The value written back to the PCI configuration register.
|
|
|
-
|
|
|
-**/
|
|
|
-UINT32
|
|
|
-EFIAPI
|
|
|
-PciExpressBitFieldAndThenOr32 (
|
|
|
- IN UINTN Address,
|
|
|
- IN UINTN StartBit,
|
|
|
- IN UINTN EndBit,
|
|
|
- IN UINT32 AndData,
|
|
|
- IN UINT32 OrData
|
|
|
- )
|
|
|
-{
|
|
|
- ASSERT_INVALID_PCI_ADDRESS (Address);
|
|
|
- return MmioBitFieldAndThenOr32 (
|
|
|
- (UINTN)GetPciExpressAddress (Address),
|
|
|
- StartBit,
|
|
|
- EndBit,
|
|
|
- AndData,
|
|
|
- OrData
|
|
|
- );
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- Reads a range of PCI configuration registers into a caller supplied buffer.
|
|
|
-
|
|
|
- Reads the range of PCI configuration registers specified by StartAddress and
|
|
|
- Size into the buffer specified by Buffer. This function only allows the PCI
|
|
|
- configuration registers from a single PCI function to be read. Size is
|
|
|
- returned. When possible 32-bit PCI configuration read cycles are used to read
|
|
|
- from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
|
|
|
- and 16-bit PCI configuration read cycles may be used at the beginning and the
|
|
|
- end of the range.
|
|
|
-
|
|
|
- If StartAddress > 0x0FFFFFFF, then ASSERT().
|
|
|
- If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
|
|
|
- If Size > 0 and Buffer is NULL, then ASSERT().
|
|
|
-
|
|
|
- @param StartAddress The starting address that encodes the PCI Bus, Device,
|
|
|
- Function and Register.
|
|
|
- @param Size The size in bytes of the transfer.
|
|
|
- @param Buffer The pointer to a buffer receiving the data read.
|
|
|
-
|
|
|
- @return Size read data from StartAddress.
|
|
|
-
|
|
|
-**/
|
|
|
-UINTN
|
|
|
-EFIAPI
|
|
|
-PciExpressReadBuffer (
|
|
|
- IN UINTN StartAddress,
|
|
|
- IN UINTN Size,
|
|
|
- OUT VOID *Buffer
|
|
|
- )
|
|
|
-{
|
|
|
- UINTN ReturnValue;
|
|
|
-
|
|
|
- ASSERT_INVALID_PCI_ADDRESS (StartAddress);
|
|
|
- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
|
|
|
-
|
|
|
- if (Size == 0) {
|
|
|
- return Size;
|
|
|
- }
|
|
|
-
|
|
|
- ASSERT (Buffer != NULL);
|
|
|
-
|
|
|
- //
|
|
|
- // Save Size for return
|
|
|
- //
|
|
|
- ReturnValue = Size;
|
|
|
-
|
|
|
- if ((StartAddress & 1) != 0) {
|
|
|
- //
|
|
|
- // Read a byte if StartAddress is byte aligned
|
|
|
- //
|
|
|
- *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);
|
|
|
- StartAddress += sizeof (UINT8);
|
|
|
- Size -= sizeof (UINT8);
|
|
|
- Buffer = (UINT8*)Buffer + 1;
|
|
|
- }
|
|
|
-
|
|
|
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
|
|
|
- //
|
|
|
- // Read a word if StartAddress is word aligned
|
|
|
- //
|
|
|
- WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));
|
|
|
-
|
|
|
- StartAddress += sizeof (UINT16);
|
|
|
- Size -= sizeof (UINT16);
|
|
|
- Buffer = (UINT16*)Buffer + 1;
|
|
|
- }
|
|
|
-
|
|
|
- while (Size >= sizeof (UINT32)) {
|
|
|
- //
|
|
|
- // Read as many double words as possible
|
|
|
- //
|
|
|
- WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartAddress));
|
|
|
-
|
|
|
- StartAddress += sizeof (UINT32);
|
|
|
- Size -= sizeof (UINT32);
|
|
|
- Buffer = (UINT32*)Buffer + 1;
|
|
|
- }
|
|
|
-
|
|
|
- if (Size >= sizeof (UINT16)) {
|
|
|
- //
|
|
|
- // Read the last remaining word if exist
|
|
|
- //
|
|
|
- WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));
|
|
|
- StartAddress += sizeof (UINT16);
|
|
|
- Size -= sizeof (UINT16);
|
|
|
- Buffer = (UINT16*)Buffer + 1;
|
|
|
- }
|
|
|
-
|
|
|
- if (Size >= sizeof (UINT8)) {
|
|
|
- //
|
|
|
- // Read the last remaining byte if exist
|
|
|
- //
|
|
|
- *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);
|
|
|
- }
|
|
|
-
|
|
|
- return ReturnValue;
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- Copies the data in a caller supplied buffer to a specified range of PCI
|
|
|
- configuration space.
|
|
|
-
|
|
|
- Writes the range of PCI configuration registers specified by StartAddress and
|
|
|
- Size from the buffer specified by Buffer. This function only allows the PCI
|
|
|
- configuration registers from a single PCI function to be written. Size is
|
|
|
- returned. When possible 32-bit PCI configuration write cycles are used to
|
|
|
- write from StartAdress to StartAddress + Size. Due to alignment restrictions,
|
|
|
- 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
|
|
|
- and the end of the range.
|
|
|
-
|
|
|
- If StartAddress > 0x0FFFFFFF, then ASSERT().
|
|
|
- If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
|
|
|
- If Size > 0 and Buffer is NULL, then ASSERT().
|
|
|
-
|
|
|
- @param StartAddress The starting address that encodes the PCI Bus, Device,
|
|
|
- Function and Register.
|
|
|
- @param Size The size in bytes of the transfer.
|
|
|
- @param Buffer The pointer to a buffer containing the data to write.
|
|
|
-
|
|
|
- @return Size written to StartAddress.
|
|
|
-
|
|
|
-**/
|
|
|
-UINTN
|
|
|
-EFIAPI
|
|
|
-PciExpressWriteBuffer (
|
|
|
- IN UINTN StartAddress,
|
|
|
- IN UINTN Size,
|
|
|
- IN VOID *Buffer
|
|
|
- )
|
|
|
-{
|
|
|
- UINTN ReturnValue;
|
|
|
-
|
|
|
- ASSERT_INVALID_PCI_ADDRESS (StartAddress);
|
|
|
- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
|
|
|
-
|
|
|
- if (Size == 0) {
|
|
|
- return 0;
|
|
|
- }
|
|
|
-
|
|
|
- ASSERT (Buffer != NULL);
|
|
|
-
|
|
|
- //
|
|
|
- // Save Size for return
|
|
|
- //
|
|
|
- ReturnValue = Size;
|
|
|
-
|
|
|
- if ((StartAddress & 1) != 0) {
|
|
|
- //
|
|
|
- // Write a byte if StartAddress is byte aligned
|
|
|
- //
|
|
|
- PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);
|
|
|
- StartAddress += sizeof (UINT8);
|
|
|
- Size -= sizeof (UINT8);
|
|
|
- Buffer = (UINT8*)Buffer + 1;
|
|
|
- }
|
|
|
-
|
|
|
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
|
|
|
- //
|
|
|
- // Write a word if StartAddress is word aligned
|
|
|
- //
|
|
|
- PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));
|
|
|
- StartAddress += sizeof (UINT16);
|
|
|
- Size -= sizeof (UINT16);
|
|
|
- Buffer = (UINT16*)Buffer + 1;
|
|
|
- }
|
|
|
-
|
|
|
- while (Size >= sizeof (UINT32)) {
|
|
|
- //
|
|
|
- // Write as many double words as possible
|
|
|
- //
|
|
|
- PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer));
|
|
|
- StartAddress += sizeof (UINT32);
|
|
|
- Size -= sizeof (UINT32);
|
|
|
- Buffer = (UINT32*)Buffer + 1;
|
|
|
- }
|
|
|
-
|
|
|
- if (Size >= sizeof (UINT16)) {
|
|
|
- //
|
|
|
- // Write the last remaining word if exist
|
|
|
- //
|
|
|
- PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));
|
|
|
- StartAddress += sizeof (UINT16);
|
|
|
- Size -= sizeof (UINT16);
|
|
|
- Buffer = (UINT16*)Buffer + 1;
|
|
|
- }
|
|
|
-
|
|
|
- if (Size >= sizeof (UINT8)) {
|
|
|
- //
|
|
|
- // Write the last remaining byte if exist
|
|
|
- //
|
|
|
- PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);
|
|
|
- }
|
|
|
-
|
|
|
- return ReturnValue;
|
|
|
-}
|