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+# Introduction
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+
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+## EDK2 RISC-V Platform Packages
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+RISC-V platform package provides the generic and common modules for RISC-V
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+platforms. RISC-V platform package could include RiscPlatformPkg.dec to
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+use the common drivers, libraries, definitions, PCDs and etc. for the
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+platform development.
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+
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+There are two packages to support RISC-V:
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+- `edk2-platforms/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec`
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+- `edk2-platforms/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec`
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+
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+`RiscVPlatformPkg` provides SEC phase and NULL libs.
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+`RiscVProcessorPkg` provides many libraries, PEIMs and DXE drivers.
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+
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+### Download the sources ###
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+```
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+git clone https://github.com/tianocore/edk2.git
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+
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+git clone https://github.com/changab/edk2-platforms.git
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+# Check out branch: riscv-smode-lib
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+```
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+
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+To build it, you have to follow the regular steps for EDK2 and additionally set
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+an environmen variable to point to your RISC-V toolchain installation,
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+including the binary prefixes:
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+
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+```
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+export GCC5_RISCV64_PREFIX=/riscv-gnu-toolchain-binaries/bin/riscv64-unknown-elf-
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+```
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+
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+Then you can build the image for the SiFive HifiveUnleashed platform:
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+
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+```
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+build -a RISCV64 -t GCC5 -p Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
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+```
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+
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+### EDK2 project
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+All changes in edk2 are upstream, however, most of the RISC-V code is in
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+edk2-platforms. Therefore you have to check out the branch `riscv-smode-lib` on
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+`github.com/changab/edk2-platforms`.
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+
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+The build architecture which is supported and verified so far is `RISCV64`.
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+The latest master of the RISC-V toolchain https://github.com/riscv/riscv-gnu-toolchain
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+should work but the latest verified commit is `b468107e701433e1caca3dbc8aef8d40`.
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+Toolchain tag is "GCC5" declared in `tools_def.txt`
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+
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+## RISC-V Platform PCD settings
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+### EDK2 Firmware Volume Settings
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+EDK2 Firmware volume related PCDs which declared in platform FDF file.
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+
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+| **PCD name** |**Usage**|
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+|--------------|---------|
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+|PcdRiscVSecFvBase| The base address of SEC Firmware Volume|
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+|PcdRiscVSecFvSize| The size of SEC Firmware Volume|
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+|PcdRiscVPeiFvBase| The base address of PEI Firmware Volume|
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+|PcdRiscVPeiFvSize| The size of SEC Firmware Volume|
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+|PcdRiscVDxeFvBase| The base address of DXE Firmware Volume|
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+|PcdRiscVDxeFvSize| The size of SEC Firmware Volume|
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+
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+### EDK2 EFI Variable Region Settings
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+The PCD settings regard to EFI Variable
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+
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+| **PCD name** |**Usage**|
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+|--------------|---------|
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+|PcdVariableFdBaseAddress| The EFI variable firmware device base address|
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+|PcdVariableFdSize| The EFI variable firmware device size|
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+|PcdVariableFdBlockSize| The block size of EFI variable firmware device|
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+|PcdPlatformFlashNvStorageVariableBase| EFI variable base address within firmware device|
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+|PcdPlatformFlashNvStorageFtwWorkingBase| The base address of EFI variable fault tolerance worksapce (FTW) within firmware device|
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+|PcdPlatformFlashNvStorageFtwSpareBase| The base address of EFI variable spare FTW within firmware device|
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+
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+### RISC-V Physical Memory Protection (PMP) Region Settings
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+Below PCDs could be set in platform FDF file.
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+
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+| **PCD name** |**Usage**|
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+|--------------|---------|
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+|PcdFwStartAddress| The starting address of firmware region to protected by PMP|
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+|PcdFwEndAddress| The ending address of firmware region to protected by PMP|
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+
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+### RISC-V Processor HART Settings
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+
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+| **PCD name** |**Usage**|
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+|--------------|---------|
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+|PcdHartCount| Number of RISC-V HARTs, the value is processor-implementation specific|
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+|PcdBootHartId| The ID of RISC-V HART to execute main fimrware code and boot system to OS|
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+
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+### RISC-V OpenSBI Settings
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+
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+| **PCD name** |**Usage**|
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+|--------------|---------|
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+|PcdScratchRamBase| The base address of OpenSBI scratch buffer for all RISC-V HARTs|
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+|PcdScratchRamSize| The total size of OpenSBI scratch buffer for all RISC-V HARTs|
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+|PcdOpenSbiStackSize| The size of initial stack of each RISC-V HART for booting system use OpenSBI|
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+|PcdTemporaryRamBase| The base address of temporary memory for PEI phase|
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+|PcdTemporaryRamSize| The temporary memory size for PEI phase|
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+
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+## Supported Operating Systems
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+Only support to boot to EFI Shell so far.
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+
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+Porting GRUB2 and Linux EFISTUB is in progress.
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+
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+## Known Issues and Limitations
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+Only RISC-V RV64 is verified.
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