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@@ -1,7 +1,7 @@
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/** @file
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This file is PeiCpuPolicy library.
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-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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+Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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@@ -45,13 +45,31 @@ LoadCpuConfigLibPreMemConfigDefault (
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CpuConfigLibPreMemConfig->BootFrequency = 1; // Maximum non-turbo Performance
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CpuConfigLibPreMemConfig->ActiveCoreCount = 0; // All cores active
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CpuConfigLibPreMemConfig->VmxEnable = CPU_FEATURE_ENABLE;
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- CpuConfigLibPreMemConfig->CpuRatio = ((AsmReadMsr64 (MSR_PLATFORM_INFO) >> N_PLATFORM_INFO_MAX_RATIO) & B_PLATFORM_INFO_RATIO_MASK);
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+ CpuConfigLibPreMemConfig->CpuRatio = RShiftU64 (AsmReadMsr64 (MSR_PLATFORM_INFO), N_PLATFORM_INFO_MAX_RATIO) & B_PLATFORM_INFO_RATIO_MASK;
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+
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///
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/// FCLK Frequency
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///
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- CpuFamily = GetCpuFamily();
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- CpuSku = GetCpuSku();
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- MchBar = MmioRead64 (MmPciBase (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN) + R_SA_MCHBAR) &~BIT0;
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+ CpuFamily = GetCpuFamily ();
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+ CpuSku = GetCpuSku ();
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+
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+ DEBUG_CODE_BEGIN ();
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+ ///
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+ /// Ensure the upper 7-bits [38:32] of MCHBAR are zero so we can access MCHBAR in 32-bit mode.
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+ ///
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+ MchBar = MmioRead32 (MmPciBase (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN) + R_SA_MCHBAR + 0x4) & 0x7F;
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+ if (MchBar != 0x0) {
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+ DEBUG ((
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+ DEBUG_ERROR,
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+ "Error: [%a]:[%dL] MCHBAR configured to >4GB\n",
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+ __FUNCTION__,
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+ __LINE__
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+ ));
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+ }
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+ ASSERT (MchBar == 0x0);
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+ DEBUG_CODE_END ();
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+
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+ MchBar = MmioRead32 (MmPciBase (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN) + R_SA_MCHBAR) &~BIT0;
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if (IsPchLinkDmi (CpuFamily) && (MmioRead16 (MmPciBase (SA_PEG_BUS_NUM, SA_PEG_DEV_NUM, SA_PEG10_FUN_NUM) + PCI_VENDOR_ID_OFFSET) != 0xFFFF)) {
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PegDisabled = MmioRead32 ((UINTN) MchBar + R_SA_MCHBAR_BIOS_RESET_CPL_OFFSET) & BIT3;
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} else {
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@@ -67,6 +85,8 @@ LoadCpuConfigLibPreMemConfigDefault (
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} else {
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CpuConfigLibPreMemConfig->FClkFrequency = 0; // 800MHz
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}
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+
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+ CpuConfigLibPreMemConfig->PeciC10Reset = 1; // Disables Peci Reset on C10 exit
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}
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/**
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