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@@ -15,6 +15,8 @@
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#include <Uefi.h>
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#include <PlatformArch.h>
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+#include <Library/BaseMemoryLib.h>
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+#include <Library/CpldD06.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/LpcLib.h>
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@@ -33,6 +35,94 @@ REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = {
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{0xFFFF,0xFFFF,0xFFFF,0xFFFF}
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};
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+//Cpu0 Riser type is (X16 + X8) & Cpu1 Riser type is (X16 + X8)
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+REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P_Type1 [PCIEDEVICE_REPORT_MAX] = {
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+ {0x01,0,0,0},
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+ {0x03,0,0,1},
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+ {0xFF,0xFF,0xFF,2},
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+ {0x81,0,0,3},
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+ {0x84,0,0,4},
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+ {0xFF,0xFF,0xFF,5}
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+};
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+
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+//Cpu0 Riser type is (X16 + X8) & Cpu1 Riser type is (3 * X8)
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+REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P_Type2 [PCIEDEVICE_REPORT_MAX] = {
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+ {0x01,0,0,0},
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+ {0x03,0,0,1},
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+ {0xFF,0xFF,0xFF,2},
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+ {0xFF,0xFF,0xFF,3},
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+ {0x81,0,0,4},
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+ {0x85,0,0,5}
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+};
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+
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+//Cpu0 Riser type is (3 * X8) & Cpu1 Riser type is (X16 + X8)
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+REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P_Type3 [PCIEDEVICE_REPORT_MAX] = {
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+ {0xFF,0xFF,0xFF,0},
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+ {0x01,0,0,1},
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+ {0x04,0,0,2},
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+ {0x81,0,0,3},
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+ {0x84,0,0,4},
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+ {0xFF,0xFF,0xFF,5}
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+};
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+
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+//Cpu0 Riser type is (3 * X8) & Cpu1 Riser type is (3 * X8)
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+REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P_Type4 [PCIEDEVICE_REPORT_MAX] = {
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+ {0xFF,0xFF,0xFF,0},
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+ {0x01,0,0,1},
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+ {0x04,0,0,2},
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+ {0xFF,0xFF,0xFF,3},
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+ {0x81,0,0,4},
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+ {0x85,0,0,5}
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+};
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+
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+VOID
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+GetPciDidVid (
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+ REPORT_PCIEDIDVID2BMC *Report
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+ )
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+{
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+ UINT32 PresentStatus;
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+ UINT32 CardType;
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+ UINT8 Cpu0CardType = 0;
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+ UINT8 Cpu1CardType = 0;
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+
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+ PresentStatus = MmioRead32 (CPLD_BASE_ADDRESS + CPLD_RISER_PRSNT_FLAG);
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+ CardType = MmioRead32 (CPLD_BASE_ADDRESS + CPLD_RISER2_BOARD_ID);
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+
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+ // Offset 0x40: Bit7 = 1 CPU0 Riser present
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+ if ((PresentStatus & CPU0_RISER_PRESENT) != 0) {
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+ Cpu0CardType = (UINT8) (PresentStatus >> 8);
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+ }
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+
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+ // Offset 0x40: Bit6 = 1 CPU1 Riser present
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+ if ((PresentStatus & CPU1_RISER_PRESENT) != 0) {
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+ Cpu1CardType = (UINT8)CardType;
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+ }
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+
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+ if (OemIsMpBoot ()) {
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+ if (Cpu0CardType == CPLD_X16_X8_BOARD_ID) {
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+ if (Cpu1CardType == CPLD_X16_X8_BOARD_ID) {
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+ (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P_Type1,
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+ sizeof (PcieDeviceToReport_2P_Type1));
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+ } else {
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+ (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P_Type2,
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+ sizeof (PcieDeviceToReport_2P_Type2));
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+ }
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+ } else {
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+ if (Cpu1CardType == CPLD_X16_X8_BOARD_ID) {
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+ (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P_Type3,
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+ sizeof (PcieDeviceToReport_2P_Type3));
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+ } else {
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+ (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P_Type4,
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+ sizeof (PcieDeviceToReport_2P_Type4));
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+ }
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+ }
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+ } else {
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+ (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport,
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+ sizeof (PcieDeviceToReport));
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+ }
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+}
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+
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+
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// Right now we only support 1P
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BOOLEAN
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OemIsSocketPresent (
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