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+/** @file
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+ Interface header file for the Enhanced warning log library class.
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+
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+ @copyright
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+ Copyright 2018 - 2021 Intel Corporation. <BR>
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+
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+ SPDX-License-Identifier: BSD-2-Clause-Patent
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+**/
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+
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+#ifndef _ENHANCED_WARNING_LOG_LIB_
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+#define _ENHANCED_WARNING_LOG_LIB_
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+
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+#include <Uefi.h>
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+#include <MrcCommonTypes.h>
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+
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+#pragma pack(1)
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+
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+///
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+/// Enhanced Warning Log Identification GUID
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+/// This GUID is used for HOB, UEFI variables, or UEFI Configuration Table as needed by platform implementations
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+/// {D8E05800-005E-4462-AA3D-9C6B4704920B}
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+///
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+#define EWL_ID_GUID { 0xd8e05800, 0x5e, 0x4462, { 0xaa, 0x3d, 0x9c, 0x6b, 0x47, 0x4, 0x92, 0xb } };
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+
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+///
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+/// Enhanced Warning Log Revision GUID
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+/// Rev 1: {75713370-3805-46B0-9FED-60F282486CFC}
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+///
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+#define EWL_REVISION1_GUID { 0x75713370, 0x3805, 0x46b0, { 0x9f, 0xed, 0x60, 0xf2, 0x82, 0x48, 0x6c, 0xfc } };
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+
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+///
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+/// Enhanced Warning Log Header
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+///
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+typedef struct {
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+ EFI_GUID EwlGuid; /// GUID that uniquely identifies the EWL revision
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+ UINT32 Size; /// Total size in bytes including the header and buffer
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+ UINT32 FreeOffset; /// Offset of the beginning of the free space from byte 0
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+ /// of the buffer immediately following this structure
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+ /// Can be used to determine if buffer has sufficient space for next entry
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+ UINT32 Crc; /// 32-bit CRC generated over the whole size minus this crc field
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+ /// Note: UEFI 32-bit CRC implementation (CalculateCrc32) (References [7])
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+ /// Consumers can ignore CRC check if not needed.
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+ UINT32 Reserved; /// Reserved for future use, must be initialized to 0
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+} EWL_HEADER;
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+
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+///
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+/// List of all entry types supported by this revision of EWL
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+///
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+typedef enum {
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+ EwlType0 = 0,
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+ EwlType1 = 1,
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+ EwlType2 = 2,
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+ EwlType3 = 3,
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+ EwlType4 = 4,
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+ EwlType5 = 5,
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+ EwlType6 = 6,
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+ EwlType7 = 7,
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+ EwlType8 = 8,
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+ EwlType9 = 9,
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+ EwlType10 = 10,
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+ EwlType11 = 11,
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+ EwlType12 = 12,
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+ EwlType13 = 13,
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+ EwlType14 = 14,
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+ EwlType15 = 15,
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+ EwlType16 = 16,
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+ EwlType17 = 17,
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+ EwlType18 = 18,
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+ EwlType19 = 19,
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+ EwlType20 = 20,
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+ EwlType21 = 21,
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+ EwlType22 = 22,
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+ EwlType23 = 23,
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+ EwlType24 = 24,
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+ EwlType25 = 25,
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+ EwlType26 = 26,
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+ EwlType27 = 27,
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+ EwlType28 = 28,
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+ EwlType29 = 29,
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+ EwlTypeMax,
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+ EwlTypeOem = 0x8000,
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+ EwlTypeDelim = MAX_INT32
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+ } EWL_TYPE;
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+
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+///
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+/// EWL severities
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+///
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+typedef enum {
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+ EwlSeverityInfo,
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+ EwlSeverityWarning,
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+ EwlSeverityFatal,
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+ EwlSeverityMax,
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+ EwlSeverityDelim = MAX_INT32
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+ } EWL_SEVERITY;
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+
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+///
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+/// EWL Size\Type Structure for error checking
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+///
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+typedef struct {
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+ EWL_TYPE Type;
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+ UINT16 Size;
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+} EWL_SIZE_CHECK;
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+
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+///
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+/// Generic entry header for parsing the log
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+///
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+typedef struct {
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+ EWL_TYPE Type;
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+ UINT16 Size; /// Entries will be packed by byte in contiguous space
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+ EWL_SEVERITY Severity; /// Warning, error, informational, this may be extended in the future
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+} EWL_ENTRY_HEADER;
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+
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+///
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+/// Legacy content provides context of the warning
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+///
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+typedef struct {
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+ UINT8 MajorCheckpoint; // EWL Spec - Appendix B
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+ UINT8 MinorCheckpoint;
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+ UINT8 MajorWarningCode; // EWL Spec - Appendix A
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+ UINT8 MinorWarningCode;
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+} EWL_ENTRY_CONTEXT;
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+
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+///
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+/// Legacy content to specify memory location
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+///
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+typedef struct {
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+ UINT8 Socket; /// 0xFF = n/a
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+ UINT8 Channel; /// 0xFF = n/a
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+ UINT8 Dimm; /// 0xFF = n/a
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+ UINT8 Rank; /// 0xFF = n/a
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+} EWL_ENTRY_MEMORY_LOCATION;
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+
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+///
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+/// Type 1 = Legacy memory warning log content plus checkpoint
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+///
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+typedef struct {
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+ EWL_ENTRY_HEADER Header;
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+ EWL_ENTRY_CONTEXT Context;
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+ EWL_ENTRY_MEMORY_LOCATION MemoryLocation;
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+} EWL_ENTRY_TYPE1;
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+
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+///
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+/// Type 2 = Enhanced type for data IO errors per device, per bit.
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+/// Primarily associated with MRC training failures. Checkpoint information provides additional
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+/// details to identify associated training step.
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+///
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+typedef struct {
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+ EWL_ENTRY_HEADER Header;
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+ EWL_ENTRY_CONTEXT Context;
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+ EWL_ENTRY_MEMORY_LOCATION MemoryLocation;
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+ UINT8 Strobe; /// 0xFF = n/a; include mapping of Dqs to Dq bits
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+ UINT8 Bit; /// 0xFF = n/a; Dq bit# within strobe group
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+ MRC_LT Level; /// MrcGtDelim = n/a; Check BIOS SSA spec (References [1])
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+ MRC_GT Group; /// MrcGtDelim = n/a; Check BIOS SSA spec (References [1])
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+ UINT8 EyeSize; /// 0xFF = n/a
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+} EWL_ENTRY_TYPE2;
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+
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+///
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+/// Type 3 = Enhanced type for command, control IO errors
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+/// Primarily associated with MRC training failures. Checkpoint information provides additional
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+/// details to identify associated training step.
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+///
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+typedef struct {
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+ EWL_ENTRY_HEADER Header;
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+ EWL_ENTRY_CONTEXT Context;
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+ EWL_ENTRY_MEMORY_LOCATION MemoryLocation;
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+ MRC_LT Level; /// MrcGtDelim = n/a; Check BIOS SSA spec (References [1])
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+ MRC_GT Group; /// MrcGtDelim = n/a; Check BIOS SSA spec (References [1])
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+ GSM_CSN Signal; /// GsmCsnDelim = n/a
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+ UINT8 EyeSize; /// 0xFF = n/a
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+} EWL_ENTRY_TYPE3;
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+
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+///
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+/// Requisite definitions for Type 4
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+///
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+/// Advanced Memtest Types
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+///
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+typedef enum {
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+ AdvMtMax = 20,
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+ AdvMtDelim = MAX_INT32
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+ } ADV_MT_TYPE;
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+
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+///
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+/// Advanced Memtest Error log structure based on processor specific CSR definitions
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+///
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+typedef struct {
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+ UINT32 Dat0S;
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+ UINT32 Dat1S;
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+ UINT32 Dat2S;
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+ UINT32 Dat3S;
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+ UINT32 EccS;
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+ UINT32 Chunk;
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+ UINT32 Column;
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+ UINT32 ColumnExt;
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+ UINT32 Row;
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+ UINT32 RowExt;
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+ UINT32 Bank;
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+ UINT32 Rank;
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+ UINT32 Subrank;
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+} EWL_ADV_MT_STATUS;
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+
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+///
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+/// Type 4 = Enhanced type for DRAM Advanced Memtest errors
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+///
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+typedef struct {
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+ EWL_ENTRY_HEADER Header;
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+ EWL_ENTRY_CONTEXT Context;
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+ EWL_ENTRY_MEMORY_LOCATION MemoryLocation;
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+ ADV_MT_TYPE MemtestType;
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+ EWL_ADV_MT_STATUS AdvMemtestErrorInfo;
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+ UINT32 Count;
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+} EWL_ENTRY_TYPE4;
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+
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+///
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+/// Type 5 = Legacy Memtest accumulated DQ errors
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+///
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+typedef struct {
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+ EWL_ENTRY_HEADER Header;
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+ EWL_ENTRY_CONTEXT Context;
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+ EWL_ENTRY_MEMORY_LOCATION MemoryLocation;
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+ UINT8 SubRank;
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+ UINT8 BankAddress;
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+ UINT8 DqBytes[9]; /// Byte 0 = DQ[7:0], byte 1 = DQ[15:8], etc.
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+} EWL_ENTRY_TYPE5;
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+
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+///
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+/// Type 6 = Legacy UPI/KTIRC warning log content plus checkpoint
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+///
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+typedef struct {
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+ EWL_ENTRY_HEADER Header;
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+ EWL_ENTRY_CONTEXT Context;
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+ UINT8 SocketMask; /// Bitmask of CPU Sockets affected; 0xFF = SystemWide
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+ UINT8 SocketType; /// 0 = CPU Socket, 1 = FPGA, 0xFF = System Wide Warning
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+ UINT8 Port; /// 0xFF = n/a; bitmask of affected port(s)
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+} EWL_ENTRY_TYPE6;
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+
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+///
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+/// Type 7 = CPU BIST failures
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+///
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+typedef struct{
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+ EWL_ENTRY_HEADER Header;
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+ EWL_ENTRY_CONTEXT Context;
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+ UINT8 Socket; /// Socket number, 0 based
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+ UINT32 Core; /// Core number, 0 based
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+} EWL_ENTRY_TYPE7;
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+
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+///
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+/// IIO Link Error log structure primary based on PCIE Specification 3.0 (References [8])
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+///
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+typedef struct {
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+ UINT8 Socket; /// Socket number, 0 based
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+ UINT8 Stack; /// 0-4, 0 = Cstack, 1-3 = Pstack, 4 MCP-stack (Only SKX-F)
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+ UINT8 Port; /// 0-3
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+ UINT8 LtssmMainState; /// Link state
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+ UINT8 LtssmSubState; /// Check Appendix C to review states definitions
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+ UINT32 DidVid; /// [31:16] DeviceID, [15:0] VendorID of the device
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+ /// attached to the Root Port
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+} EWL_IIO_LINK_DESCRIPTION;
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+
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+///
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+/// Type 8 = IIO Link Degraded width
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+///
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+typedef struct {
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+ EWL_ENTRY_HEADER Header;
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+ EWL_ENTRY_CONTEXT Context;
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+ EWL_IIO_LINK_DESCRIPTION LinkDescription;
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+ UINT8 ExpectedLinkWidth; /// Check register "Link Capabilities Register" over
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+ UINT8 ActualLinkWidth; /// PCIE Specification 3.0 (References [8])
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+} EWL_ENTRY_TYPE8;
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+
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+///
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+/// Type 9 = IIO Link Degraded speed
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+///
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+typedef struct {
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+ EWL_ENTRY_HEADER Header;
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+ EWL_ENTRY_CONTEXT Context;
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+ EWL_IIO_LINK_DESCRIPTION LinkDescription;
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+ UINT8 ExpectedLinkSpeed; /// Check register "Link Capabilities Register" over
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+ UINT8 ActualLinkSpeed; /// PCIE Specification 3.0 (References [8])
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+} EWL_ENTRY_TYPE9;
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+
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+///
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+/// Type 10 = Dq Swizzle Discovery errors
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+/// Error if 0 or greater than 1 bit set in SwizzledDqLanes per strobe
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+///
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+typedef struct {
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+ EWL_ENTRY_HEADER Header;
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+ EWL_ENTRY_CONTEXT Context;
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+ EWL_ENTRY_MEMORY_LOCATION MemoryLocation;
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+ UINT8 SwizzlePattern; /// DQ pattern sent from device
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+ UINT8 SwizzledDqLanes; /// DQ pattern received at Host
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+ UINT8 LanesPerStrobe; /// 4 or 8
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+ UINT8 Strobe; /// DQS number to identify device
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+} EWL_ENTRY_TYPE10;
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+
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+///
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+/// Type 13 = NVMDIMM Training Failure
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+/// Reported when a training issue is encountered
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+/// Includes additional details on the NVMDIMM SPD and FW revisions
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+///
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+typedef struct {
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+ EWL_ENTRY_HEADER Header;
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+ EWL_ENTRY_CONTEXT Context;
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+ EWL_ENTRY_MEMORY_LOCATION MemoryLocation;
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+ UINT16 RevisionNvmdimmFw;
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+ UINT8 RevisionNvmdimmSpd;
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+} EWL_ENTRY_TYPE13;
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+
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+///
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+/// Type 17 = ME communication failures
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+/// Failure to communicate with Manageability Engine
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+///
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+typedef struct {
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+ EWL_ENTRY_HEADER Header;
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+ EWL_ENTRY_CONTEXT Context;
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+ UINT32 Revision; /// ME API Revision
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+ UINT32 Mefs1; /// ME Firmware Status 1 (HECI-1 HFS)
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+ UINT32 Mefs2; /// ME Firmware Status 2 (HECI-1 GS_SHDW)
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+ UINT8 HeciDevice; /// HECI device (1, 2, or 3)
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+ UINT8 MeAddress; /// HECI address of ME entity
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+ UINT8 SendStatus; /// Status of send operation
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+ UINT8 ReceiveStatus; /// Status of receive operation
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+ UINT64 Request; /// First 8 bytes of request message
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+ UINT32 Response; /// First 4 bytes of response message
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+} EWL_ENTRY_TYPE17;
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+
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+///
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+/// To get more information about Machine-Check Architecture please check Chapter 15 from Vol. 3B
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+/// of the Intel(R) 64 and IA-32 Architectures Software Developer's Manual (References [6]) for a
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+/// general review.
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+///
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+/// Type 20 = CPU Machine Check Errors
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+///
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+typedef struct {
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+ EWL_ENTRY_HEADER Header;
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+ EWL_ENTRY_CONTEXT Context;
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+ UINT32 CpuId; /// Refer to CPUID(EAX = 1) instruction to get Type, Family,
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+ /// Model, and Stepping ID from (References [6])
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+ UINT8 Socket; /// Socket number, 0 based
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+ UINT32 Core; /// Core number, 0 based
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+ UINT32 McBankNum; /// Please refer to mcBankTable
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+ UINT32 McBankStatus; /// Check register IA32_MCi_STATUS MSRs (References [6]&[5])
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+ UINT32 McBankAddr; /// Check register IA32_MCi_ADDR MSRs (References [6]&[5])
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+ UINT32 McBankMisc; /// Check register IA32_MCi_MISC MSRs (References [6]&[5])
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+} EWL_ENTRY_TYPE20;
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+
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+///
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+/// Requisite definitions for Type 21
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+///
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+/// Reasons for Topology degradation
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+///
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+typedef enum {
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+ Undefined = 0,
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+ LinkFail = 1,
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+ InvalidTopology = 2,
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+ FeatureVsTopology = 3,
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+ DegradeReasonMax,
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+ DegradeReasonDelim = MAX_INT32
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+ } TOPOLOGY_DEGRADE_REASON;
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+
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+///
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+/// Type 21: Warning for tracking changes to KTI/UPI topology
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+///
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+/// Topology will be represented with a UINT64 bit array
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+/// 0 indicates absent or inactive link
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+/// 1 indicates active KTI/UPI link
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+///
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+/// Link Bit array member variables follow this format
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+/// Each nibble corresponds to a socket:
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+/// Each socket has MAX_FW_KTI_PORTS bits
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+/// [(8*MAX_FW_KTI_PORTS - 1):7*MAX_FW_KTI_PORTS] - link bit mask for socket 7
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+/// [(7*MAX_FW_KTI_PORTS - 1):6*MAX_FW_KTI_PORTS] - link bit mask for socket 6
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+/// ....
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+/// [(2*MAX_FW_KTI_PORTS - 1): MAX_FW_KTI_PORTS] - link bit mask for socket 1
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+/// [(MAX_FW_KTI_PORTS - 1) : 0] - link bit mask for socket 0
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+///
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+/// Bit 0 indicates an active link on port socket 0 port 0
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+/// Bit 1 indicates an active link on port socket 0 port 1
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+/// and so on.
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+
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+typedef struct {
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+ EWL_ENTRY_HEADER Header;
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+ TOPOLOGY_DEGRADE_REASON Reason;
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+ UINT64 DegradedFrom; /// Link Bit Array
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+ UINT64 NewTopology; /// Link Bit Array
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+} EWL_ENTRY_TYPE21;
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+
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+///
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+/// To get more information about Machine-Check Architecture please check Chapter 15 from Vol. 3B
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+/// of the Intel 64 and IA-32 Architectures Software Developer's Manual (References [6]) for a
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+/// general review.
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+///
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+/// Type 22 = CPU Machine Check Errors. 2nd Version.
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+///
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+typedef struct {
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+ EWL_ENTRY_HEADER Header;
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+ EWL_ENTRY_CONTEXT Context;
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+ UINT32 CpuId; /// Refer to CPUID(EAX=1) instruction to get Type, Family,
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+ /// Model, and Stepping ID from (References [6])
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|
|
+ UINT8 Socket; /// Socket number, 0 based
|
|
|
+ UINT32 Core; /// Core number, 0 based
|
|
|
+ UINT32 McBankNum; /// Please refer to mcBankTable
|
|
|
+ UINT64 McBankStatus; /// Check register IA32_MCi_STATUS MSRs (References [6]&[5])
|
|
|
+ UINT64 McBankAddr; /// Check register IA32_MCi_ADDR MSRs (References [6]&[5])
|
|
|
+ UINT64 McBankMisc; /// Check register IA32_MCi_MISC MSRs (References [6]&[5])
|
|
|
+} EWL_ENTRY_TYPE22;
|
|
|
+
|
|
|
+//
|
|
|
+// Memory Boot Health check Warning log.
|
|
|
+//
|
|
|
+typedef struct {
|
|
|
+ EWL_ENTRY_HEADER Header;
|
|
|
+ EWL_ENTRY_CONTEXT Context;
|
|
|
+ EWL_ENTRY_MEMORY_LOCATION MemoryLocation;
|
|
|
+ MRC_GT Group; /// MrcGtDelim = n/a;
|
|
|
+ INT16 Offset; /// Signal offset size that caused the error
|
|
|
+} EWL_ENTRY_TYPE25;
|
|
|
+
|
|
|
+//
|
|
|
+// Memory Power Management Errors
|
|
|
+//
|
|
|
+typedef struct {
|
|
|
+ EWL_ENTRY_HEADER Header;
|
|
|
+ EWL_ENTRY_CONTEXT Context;
|
|
|
+ EWL_ENTRY_MEMORY_LOCATION MemoryLocation;
|
|
|
+} EWL_ENTRY_TYPE26;
|
|
|
+
|
|
|
+///
|
|
|
+/// Type 27 = NVMDIMM Media Log
|
|
|
+/// Reported NVMDIMM Media log
|
|
|
+///
|
|
|
+typedef struct {
|
|
|
+ EWL_ENTRY_HEADER Header;
|
|
|
+ EWL_ENTRY_CONTEXT Context;
|
|
|
+ EWL_ENTRY_MEMORY_LOCATION MemoryLocation;
|
|
|
+ UINT64 TimeStamp;
|
|
|
+ UINT64 DPA;
|
|
|
+ UINT64 PDA;
|
|
|
+ UINT8 Range;
|
|
|
+ UINT8 ErrorType;
|
|
|
+ UINT8 ErrorFlag;
|
|
|
+ UINT8 TransacationType;
|
|
|
+ UINT16 SequenceNumber;
|
|
|
+ UINT16 Rsvd;
|
|
|
+} EWL_ENTRY_TYPE27;
|
|
|
+
|
|
|
+///
|
|
|
+/// Type 28 = NVMDIMM Thermal Log
|
|
|
+/// Reported NVMDIMM Thermal log
|
|
|
+///
|
|
|
+typedef struct {
|
|
|
+ EWL_ENTRY_HEADER Header;
|
|
|
+ EWL_ENTRY_CONTEXT Context;
|
|
|
+ EWL_ENTRY_MEMORY_LOCATION MemoryLocation;
|
|
|
+ UINT64 TimeStamp;
|
|
|
+ UINT32 HostReportedTempData;
|
|
|
+ UINT16 SequenceNumber;
|
|
|
+ UINT16 Rsvd;
|
|
|
+} EWL_ENTRY_TYPE28;
|
|
|
+
|
|
|
+//
|
|
|
+// RMT minimum margin check warning log.
|
|
|
+//
|
|
|
+typedef struct {
|
|
|
+ EWL_ENTRY_HEADER Header;
|
|
|
+ EWL_ENTRY_CONTEXT Context;
|
|
|
+ EWL_ENTRY_MEMORY_LOCATION MemoryLocation;
|
|
|
+ MRC_GT Group;
|
|
|
+ INT16 NegativeMargin;
|
|
|
+ INT16 PositiveMargin;
|
|
|
+ INT16 MinimumMargin;
|
|
|
+} EWL_ENTRY_TYPE29;
|
|
|
+
|
|
|
+#pragma pack()
|
|
|
+
|
|
|
+///
|
|
|
+/// Enhanced Warning Log Spec defined data log structure
|
|
|
+///
|
|
|
+typedef struct {
|
|
|
+ EWL_HEADER Header; /// The size will vary by implementation and should not be assumed
|
|
|
+ UINT8 Buffer[4 * 1024]; /// The spec requirement is that the buffer follow the header
|
|
|
+} EWL_PUBLIC_DATA;
|
|
|
+
|
|
|
+///
|
|
|
+/// EWL private data structure. This is going to be implementation dependent
|
|
|
+/// When we separate OEM hooks via a PPI, we can remove this
|
|
|
+///
|
|
|
+typedef struct {
|
|
|
+ UINT32 bufSizeOverflow; // Number of bytes that could not be added to buffer
|
|
|
+ UINT32 numEntries; // Number of entries currently logged
|
|
|
+ EWL_PUBLIC_DATA status; // Spec defined EWL
|
|
|
+} EWL_PRIVATE_DATA;
|
|
|
+
|
|
|
+#endif // #ifndef _ENHANCED_WARNING_LOG_LIB_
|