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@@ -1,7 +1,7 @@
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/** @file
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GPIO definition table for KabylakeRvp3
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-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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@@ -423,4 +423,119 @@ GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSpdLpddr32133[] = {
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};
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GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSpdLpddr32133Size = sizeof (mSpdLpddr32133);
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+/**
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+ Hynix H9CCNNN8JTMLAR-NTM_178b_DDP LPDDR3, 4Gb die (128Mx32), x32
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+ or Elpida EDF8132A1MC-GD-F
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+ or Samsung K4E8E304EB-EGCE
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+ 1600, 12-15-15-34
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+ 2 rank per channel, 2 SDRAMs per rank, 4x4Gb = 2GB total per channel
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+**/
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+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSkylakeRvp3Spd[] = {
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+ 0x24, ///< 0 Number of Serial PD Bytes Written / SPD Device Size
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+ 0x20, ///< 1 SPD Revision
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+ 0x0F, ///< 2 DRAM Device Type
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+ 0x0E, ///< 3 Module Type
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+ 0x14, ///< 4 SDRAM Density and Banks: 8 Banks, 4 Gb SDRAM density
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+ 0x11, ///< 5 SDRAM Addressing: 14 Rows, 10 Columns
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+ 0x95, ///< 6 SDRAM Package Type: DDP, 1 Channel per die, Signal Loading Matrix 1
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+ 0x00, ///< 7 SDRAM Optional Features
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+ 0x00, ///< 8 SDRAM Thermal and Refresh Options
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+ 0x00, ///< 9 Other SDRAM Optional Features
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+ 0x00, ///< 10 Reserved - must be coded as 0x00
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+ 0x03, ///< 11 Module Nominal Voltage, VDD
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+ 0x0B, ///< 12 Module Organization, SDRAM width: 32 bits, 2 Ranks
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+ 0x23, ///< 13 Module Memory Bus Width: 2 channels, 64 bit channel bus width
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+ 0x00, ///< 14 Module Thermal Sensor
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+ 0x00, ///< 15 Extended Module Type
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+ 0x00, ///< 16 Reserved - must be coded as 0x00
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+ 0x00, ///< 17 Timebases
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+ 0x0A, ///< 18 SDRAM Minimum Cycle Time (tCKmin)
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+ 0xFF, ///< 19 SDRAM Minimum Cycle Time (tCKmax)
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+ 0x54, ///< 20 CAS Latencies Supported, First Byte (tCk): 12 10 8
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+ 0x00, ///< 21 CAS Latencies Supported, Second Byte
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+ 0x00, ///< 22 CAS Latencies Supported, Third Byte
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+ 0x00, ///< 23 CAS Latencies Supported, Fourth Byte
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+ 0x78, ///< 24 Minimum CAS Latency Time (tAAmin)
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+ 0x00, ///< 25 Read and Write Latency Set Options
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+ 0x90, ///< 26 Minimum RAS# to CAS# Delay Time (tRCDmin)
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+ 0xA8, ///< 27 Minimum Row Precharge Delay Time for all banks (tRPab)
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+ 0x90, ///< 28 Minimum Row Precharge Delay Time per bank (tRPpb)
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+ 0x10, ///< 29 Minimum Refresh Recovery Delay Time for all banks (tRFCab), Least Significant Byte
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+ 0x04, ///< 30 Minimum Refresh Recovery Delay Time for all banks (tRFCab), Most Significant Byte
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+ 0xE0, ///< 31 Minimum Refresh Recovery Delay Time for per bank (tRFCpb), Least Significant Byte
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+ 0x01, ///< 32 Minimum Refresh Recovery Delay Time for per bank (tRFCpb), Most Significant Byte
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+ 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 Connector to SDRAM Bit Mapping
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+ 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 77 Connector to SDRAM Bit Mapping
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+ 0, 0, ///< 78 - 79
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
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+ 0x00, ///< 120 Fine Offset for Minimum Row Precharge Delay Time per bank (tRPpb)
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+ 0x00, ///< 121 Fine Offset for Minimum Row Precharge Delay Time for all banks (tRPab)
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+ 0x00, ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
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+ 0x00, ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin)
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+ 0x7F, ///< 124 Fine Offset for SDRAM Minimum Cycle Time (tCKmax)
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+ 0x00, ///< 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
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+ 0x00, ///< 126 CRC A
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+ 0x00, ///< 127 CRC B
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+ 0, 0, ///< 128 - 129
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
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+ 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte
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+ 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte
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+ 0x00, ///< 322 Module Manufacturing Location
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+ 0x00, ///< 323 Module Manufacturing Date Year
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+ 0x00, ///< 324 Module Manufacturing Date Week
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+ 0x55, ///< 325 Module Serial Number A
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+ 0x00, ///< 326 Module Serial Number B
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+ 0x00, ///< 327 Module Serial Number C
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+ 0x00, ///< 328 Module Serial Number D
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+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
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+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number
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+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number
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+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number
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+ 0x00, ///< 349 Module Revision Code
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+ 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte
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+ 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte
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+ 0x00, ///< 352 DRAM Stepping
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+ 0, 0, 0, 0, 0, 0, 0, ///< 353 - 359
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 440 - 449
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509
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+ 0, 0 ///< 510 - 511
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+};
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+GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSkylakeRvp3SpdSize = sizeof (mSkylakeRvp3Spd);
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#endif // _KABYLAKE_RVP3_SPD_TABLE_H_
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