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Silicon/NXP: Remove unnecessary PCDs

The memory map of an SOC is fixed in hardware. it doesn't change with
platform that uses SOC. So, there is no need to keep PCDs for these values
and we can use macros for these in SOC header file.

Any Platform using the SOC, can make use of the SOC header file.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
Pankaj Bansal 4 years ago
parent
commit
3a9dba529f

+ 8 - 7
Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c

@@ -1,7 +1,7 @@
 /** @file
   LS1043 DXE platform driver.
 
-  Copyright 2018-2019 NXP
+  Copyright 2018-2020 NXP
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -14,6 +14,7 @@
 #include <Library/PcdLib.h>
 #include <Library/UefiBootServicesTableLib.h>
 #include <Library/UefiLib.h>
+#include <Soc.h>
 
 #include <Protocol/NonDiscoverableDevice.h>
 
@@ -22,7 +23,7 @@ typedef struct {
   UINT8 EndDesc;
 } ADDRESS_SPACE_DESCRIPTOR;
 
-STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[FixedPcdGet64 (PcdNumI2cController)];
+STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[LS1043A_I2C_NUM_CONTROLLERS];
 
 STATIC
 EFI_STATUS
@@ -65,19 +66,19 @@ PopulateI2cInformation (
 {
   UINT32 Index;
 
-  for (Index = 0; Index < FixedPcdGet32 (PcdNumI2cController); Index++) {
+  for (Index = 0; Index < ARRAY_SIZE (mI2cDesc); Index++) {
     mI2cDesc[Index].StartDesc.Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
     mI2cDesc[Index].StartDesc.Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
     mI2cDesc[Index].StartDesc.ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
     mI2cDesc[Index].StartDesc.GenFlag = 0;
     mI2cDesc[Index].StartDesc.SpecificFlag = 0;
     mI2cDesc[Index].StartDesc.AddrSpaceGranularity = 32;
-    mI2cDesc[Index].StartDesc.AddrRangeMin = FixedPcdGet64 (PcdI2c0BaseAddr) +
-                                             (Index * FixedPcdGet32 (PcdI2cSize));
+    mI2cDesc[Index].StartDesc.AddrRangeMin = LS1043A_I2C0_PHYS_ADDRESS +
+                                             (Index * LS1043A_I2C_SIZE);
     mI2cDesc[Index].StartDesc.AddrRangeMax = mI2cDesc[Index].StartDesc.AddrRangeMin +
-                                             FixedPcdGet32 (PcdI2cSize) - 1;
+                                             LS1043A_I2C_SIZE - 1;
     mI2cDesc[Index].StartDesc.AddrTranslationOffset = 0;
-    mI2cDesc[Index].StartDesc.AddrLen = FixedPcdGet32 (PcdI2cSize);
+    mI2cDesc[Index].StartDesc.AddrLen = LS1043A_I2C_SIZE;
 
     mI2cDesc[Index].EndDesc = ACPI_END_TAG_DESCRIPTOR;
   }

+ 3 - 7
Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf

@@ -2,7 +2,7 @@
 #
 #  Component description file for LS1043 DXE platform driver.
 #
-#  Copyright 2018-2019 NXP
+#  Copyright 2018-2020 NXP
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -21,9 +21,10 @@
 
 [Packages]
   ArmPkg/ArmPkg.dec
-  MdePkg/MdePkg.dec
   MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
   Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
+  Silicon/NXP/LS1043A/LS1043A.dec
   Silicon/NXP/NxpQoriqLs.dec
 
 [LibraryClasses]
@@ -43,10 +44,5 @@
   gEdkiiNonDiscoverableDeviceProtocolGuid        ## PRODUCES
   gDs1307RealTimeClockLibI2cMasterProtocolGuid   ## PRODUCES
 
-[FixedPcd]
-  gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
-  gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
-  gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
-
 [Depex]
   TRUE

+ 2 - 19
Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf

@@ -1,7 +1,7 @@
 #  @file
 #
 #  Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
-#  Copyright 2017, 2019 NXP
+#  Copyright 2017, 2019-2020 NXP
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -19,6 +19,7 @@
   ArmPlatformPkg/ArmPlatformPkg.dec
   EmbeddedPkg/EmbeddedPkg.dec
   MdePkg/MdePkg.dec
+  Silicon/NXP/LS1043A/LS1043A.dec
   Silicon/NXP/NxpQoriqLs.dec
 
 [LibraryClasses]
@@ -35,21 +36,3 @@
 
 [FixedPcd]
   gArmTokenSpaceGuid.PcdArmPrimaryCore
-  gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
-  gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
-  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
-  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
-  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
-  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size
-  gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr
-  gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize
-  gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr
-  gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize
-  gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
-  gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize
-  gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
-  gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize
-  gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
-  gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize
-  gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
-  gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize

+ 37 - 42
Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c

@@ -6,7 +6,7 @@
 *
 *  Copyright (c) 2011, ARM Limited. All rights reserved.
 *  Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
-*  Copyright 2017, 2019 NXP
+*  Copyright 2017, 2019-2020 NXP
 *
 *  SPDX-License-Identifier: BSD-2-Clause-Patent
 *
@@ -16,7 +16,7 @@
 #include <Library/DebugLib.h>
 #include <Library/PcdLib.h>
 #include <Library/MemoryAllocationLib.h>
-#include <DramInfo.h>
+#include <Soc.h>
 
 #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS          25
 
@@ -38,7 +38,6 @@ ArmPlatformGetVirtualMemoryMap (
 {
   UINTN                            Index;
   ARM_MEMORY_REGION_DESCRIPTOR     *VirtualMemoryTable;
-  DRAM_INFO                        DramInfo;
 
   Index = 0;
 
@@ -51,24 +50,20 @@ ArmPlatformGetVirtualMemoryMap (
     return;
   }
 
-  if (GetDramBankInfo (&DramInfo)) {
-    DEBUG ((DEBUG_ERROR, "Failed to get DRAM information, exiting...\n"));
-    return;
-  }
+  VirtualMemoryTable[Index].PhysicalBase = LS1043A_DRAM0_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].VirtualBase  = LS1043A_DRAM0_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].Length       = LS1043A_DRAM0_SIZE;
+  VirtualMemoryTable[Index++].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
 
-
-  for (Index = 0; Index < DramInfo.NumOfDrams; Index++) {
-    // DRAM1 (Must be 1st entry)
-    VirtualMemoryTable[Index].PhysicalBase = DramInfo.DramRegion[Index].BaseAddress;
-    VirtualMemoryTable[Index].VirtualBase  = DramInfo.DramRegion[Index].BaseAddress;
-    VirtualMemoryTable[Index].Length       = DramInfo.DramRegion[Index].Size;
-    VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
-  }
+  VirtualMemoryTable[Index].PhysicalBase = LS1043A_DRAM1_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].VirtualBase  = LS1043A_DRAM1_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].Length       = LS1043A_DRAM1_SIZE;
+  VirtualMemoryTable[Index++].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
 
   // CCSR Space
-  VirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdCcsrBaseAddr);
-  VirtualMemoryTable[Index].VirtualBase  = FixedPcdGet64 (PcdCcsrBaseAddr);
-  VirtualMemoryTable[Index].Length       = FixedPcdGet64 (PcdCcsrSize);
+  VirtualMemoryTable[Index].PhysicalBase = LS1043A_CCSR_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].VirtualBase  = LS1043A_CCSR_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].Length       = LS1043A_CCSR_SIZE;
   VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
 
   // IFC region 1
@@ -85,51 +80,51 @@ ArmPlatformGetVirtualMemoryMap (
   //             For write transactions from non-core masters (like system DMA), the address
   //                should be 16 byte aligned and the data size should be multiple of 16 bytes.
   //
-  VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
-  VirtualMemoryTable[Index].VirtualBase  = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
-  VirtualMemoryTable[Index].Length       = FixedPcdGet64 (PcdIfcRegion1Size);
+  VirtualMemoryTable[++Index].PhysicalBase = LS1043A_IFC0_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].VirtualBase  = LS1043A_IFC0_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].Length       = LS1043A_IFC0_SIZE;
   VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
 
   // QMAN SWP
-  VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQmanSwpBaseAddr);
-  VirtualMemoryTable[Index].VirtualBase  = FixedPcdGet64 (PcdQmanSwpBaseAddr);
-  VirtualMemoryTable[Index].Length       = FixedPcdGet64 (PcdQmanSwpSize);
+  VirtualMemoryTable[++Index].PhysicalBase = LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].VirtualBase  = LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].Length       = LS1043A_QMAN_SW_PORTAL_SIZE;
   VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
 
   // BMAN SWP
-  VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdBmanSwpBaseAddr);
-  VirtualMemoryTable[Index].VirtualBase  = FixedPcdGet64 (PcdBmanSwpBaseAddr);
-  VirtualMemoryTable[Index].Length       = FixedPcdGet64 (PcdBmanSwpSize);
+  VirtualMemoryTable[++Index].PhysicalBase = LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].VirtualBase  = LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].Length       = LS1043A_QMAN_SW_PORTAL_SIZE;
   VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
 
   // IFC region 2
-  VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
-  VirtualMemoryTable[Index].VirtualBase  = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
-  VirtualMemoryTable[Index].Length       = FixedPcdGet64 (PcdIfcRegion2Size);
+  VirtualMemoryTable[++Index].PhysicalBase = LS1043A_IFC1_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].VirtualBase  = LS1043A_IFC1_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].Length       = LS1043A_IFC1_SIZE;
   VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
 
   // PCIe1
-  VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
-  VirtualMemoryTable[Index].VirtualBase  = FixedPcdGet64 (PcdPciExp1BaseAddr);
-  VirtualMemoryTable[Index].Length       = FixedPcdGet64 (PcdPciExp1BaseSize);
+  VirtualMemoryTable[++Index].PhysicalBase = LS1043A_PCI0_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].VirtualBase  = LS1043A_PCI0_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].Length       = LS1043A_PCI_SIZE;
   VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
 
   // PCIe2
-  VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
-  VirtualMemoryTable[Index].VirtualBase  = FixedPcdGet64 (PcdPciExp2BaseAddr);
-  VirtualMemoryTable[Index].Length       = FixedPcdGet64 (PcdPciExp2BaseSize);
+  VirtualMemoryTable[++Index].PhysicalBase = LS1043A_PCI1_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].VirtualBase  = LS1043A_PCI1_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].Length       = LS1043A_PCI_SIZE;
   VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
 
   // PCIe3
-  VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
-  VirtualMemoryTable[Index].VirtualBase  = FixedPcdGet64 (PcdPciExp3BaseAddr);
-  VirtualMemoryTable[Index].Length       = FixedPcdGet64 (PcdPciExp3BaseSize);
+  VirtualMemoryTable[++Index].PhysicalBase = LS1043A_PCI2_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].VirtualBase  = LS1043A_PCI2_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].Length       = LS1043A_PCI_SIZE;
   VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
 
   // QSPI region
-  VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
-  VirtualMemoryTable[Index].VirtualBase  = FixedPcdGet64 (PcdQspiRegionBaseAddr);
-  VirtualMemoryTable[Index].Length       = FixedPcdGet64 (PcdQspiRegionSize);
+  VirtualMemoryTable[++Index].PhysicalBase = LS1043A_QSPI_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].VirtualBase  = LS1043A_QSPI_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].Length       = LS1043A_QSPI_SIZE;
   VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
 
   // End of Table

+ 2 - 0
Silicon/NXP/Include/Chassis2/NxpSoc.h

@@ -12,6 +12,8 @@
 
 #define CLK_FREQ                   100000000
 
+#define CHASSIS2_DCFG_ADDRESS      0x1EE0000
+
 /* SMMU Defintions */
 #define SMMU_BASE_ADDR             0x09000000
 #define SMMU_REG_SCR0              (SMMU_BASE_ADDR + 0x0)

+ 44 - 0
Silicon/NXP/LS1043A/Include/Soc.h

@@ -0,0 +1,44 @@
+/** @file
+
+  Copyright 2020 NXP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef SOC_H__
+#define SOC_H__
+
+/**
+  Soc Memory Map
+**/
+#define LS1043A_DRAM0_PHYS_ADDRESS   0x80000000
+#define LS1043A_DRAM0_SIZE           SIZE_2GB
+#define LS1043A_DRAM1_PHYS_ADDRESS   0x880000000
+#define LS1043A_DRAM1_SIZE           0x780000000 // 30 GB
+
+#define LS1043A_CCSR_PHYS_ADDRESS    0x1000000
+#define LS1043A_CCSR_SIZE            0xF000000
+
+#define LS1043A_IFC0_PHYS_ADDRESS    0x60000000
+#define LS1043A_IFC0_SIZE            SIZE_512MB
+#define LS1043A_IFC1_PHYS_ADDRESS    0x620000000
+#define LS1043A_IFC1_SIZE            0xE0000000 // 3.5 GB
+
+#define LS1043A_QSPI_PHYS_ADDRESS    0x40000000
+#define LS1043A_QSPI_SIZE            SIZE_512MB
+
+#define LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS    0x500000000
+#define LS1043A_QMAN_SW_PORTAL_SIZE            SIZE_128MB
+#define LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS    0x508000000
+#define LS1043A_BMAN_SW_PORTAL_SIZE            SIZE_128MB
+
+#define LS1043A_PCI0_PHYS_ADDRESS    0x4000000000
+#define LS1043A_PCI1_PHYS_ADDRESS    0x4800000000
+#define LS1043A_PCI2_PHYS_ADDRESS    0x5000000000
+#define LS1043A_PCI_SIZE             SIZE_32GB
+
+#define LS1043A_I2C0_PHYS_ADDRESS    0x2180000
+#define LS1043A_I2C_SIZE             0x10000
+#define LS1043A_I2C_NUM_CONTROLLERS  4
+
+#endif // SOC_H__

+ 0 - 26
Silicon/NXP/LS1043A/LS1043A.dsc.inc

@@ -26,32 +26,6 @@
 [PcdsFixedAtBuild.common]
   gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
 
-  #
-  # CCSR Address Space and other attached Memories
-  #
-  gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
-  gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
-  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000
-  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000
-  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000
-  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000
-  gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000
-  gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000
-  gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000
-  gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000
-  gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000
-  gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000
-  gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000
-  gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000
-  gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000
-  gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000
-  gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000
-  gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000
-  gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
-  gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
-  gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
-  gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
-
   #
   # Big Endian IPs
   #

+ 1 - 1
Silicon/NXP/Library/SocLib/Chassis2/Soc.c

@@ -34,7 +34,7 @@ GetSysInfo (
   CCSR_GUR     *GurBase;
   UINTN        SysClk;
 
-  GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+  GurBase = (CCSR_GUR *)CHASSIS2_DCFG_ADDRESS;
   SysClk = CLK_FREQ;
 
   SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);

+ 0 - 1
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf

@@ -36,5 +36,4 @@
 [FixedPcd]
   gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
   gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
-  gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
   gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv

+ 0 - 47
Silicon/NXP/NxpQoriqLs.dec

@@ -22,53 +22,6 @@
   gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}
 
 [PcdsFixedAtBuild.common]
-  #
-  # Pcds for I2C Controller
-  #
-  gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|0|UINT32|0x00000001
-  gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|0|UINT32|0x00000002
-
-  #
-  # Pcds for base address and size
-  #
-  gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x0|UINT64|0x00000100
-  gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x0|UINT64|0x00000103
-  gNxpQoriqLsTokenSpaceGuid.PcdDdrBaseAddr|0x0|UINT64|0x00000105
-  gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x0|UINT64|0x00000106
-  gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x0|UINT64|0x00000107
-  gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x0|UINT64|0x00000108
-  gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x0|UINT32|0x00000109
-  gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x0|UINT64|0x0000010A
-  gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x0|UINT64|0x0000010B
-  gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x0|UINT32|0x0000010C
-  gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x0000010D
-  gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0|UINT64|0x0000010E
-  gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0|UINT64|0x0000010F
-  gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0|UINT64|0x00000110
-  gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0|UINT64|0x00000111
-  gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x0|UINT64|0x00000112
-  gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x0|UINT64|0x00000113
-  gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x0|UINT64|0x00000114
-  gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x0|UINT64|0x00000115
-  gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x0|UINT64|0x00000116
-  gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x0|UINT64|0x00000117
-  gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr|0x0|UINT64|0x0000118
-  gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize|0x0|UINT64|0x0000119
-  gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x0|UINT64|0x0000011A
-  gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x0|UINT64|0x0000011B
-  gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x0|UINT64|0x0000011C
-  gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x0|UINT64|0x0000011D
-  gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x00000122
-  gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000123
-
-  #
-  # IFC PCDs
-  #
-  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x0|UINT64|0x00000190
-  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x0|UINT64|0x00000191
-  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0|UINT64|0x00000192
-  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x0|UINT64|0x00000193
-
   #
   # Platform PCDs
   #