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+/** @file
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+ Header file for Platform Boards Configurations.
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+
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+
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+ Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
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+ SPDX-License-Identifier: BSD-2-Clause-Patent
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+**/
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+
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+#ifndef _PLATFORM_BOARD_CONFIG_H
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+#define _PLATFORM_BOARD_CONFIG_H
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+
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+#include <ConfigBlock.h>
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+#include <PchPolicyCommon.h>
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+#include <ConfigBlock/MemoryConfig.h>
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+#include <GpioConfig.h>
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+#include <TbtBoardInfo.h>
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+
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+#define IS_ALIGNED(addr, size) (((addr) & (size - 1)) ? 0 : 1)
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+#define ALIGN16(size) (IS_ALIGNED(size, 16) ? size : ((size + 16) & 0xFFF0))
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+
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+#define BOARD_CONFIG_BLOCK_PEI_PREMEM_VERSION 0x00000001
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+#define BOARD_CONFIG_BLOCK_PEI_POSTMEM_VERSION 0x00000001
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+#define BOARD_CONFIG_BLOCK_DXE_VERSION 0x00000001
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+#define BOARD_NO_BATTERY_SUPPORT 0
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+#define BOARD_REAL_BATTERY_SUPPORTED BIT0
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+#define BOARD_VIRTUAL_BATTERY_SUPPORTED BIT1
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+
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+#pragma pack(1)
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+
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+typedef struct {
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+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
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+} BOARD_CONFIG_BLOCK;
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+
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+typedef struct {
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+ UINT8 GpioSupport;
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+ UINT32 WakeGpioNo;
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+ UINT8 HoldRstExpanderNo;
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+ UINT32 HoldRstGpioNo;
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+ BOOLEAN HoldRstActive;
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+ UINT8 PwrEnableExpanderNo;
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+ UINT32 PwrEnableGpioNo;
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+ BOOLEAN PwrEnableActive;
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+} SWITCH_GRAPHIC_GPIO;
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+
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+typedef struct {
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+ UINT8 ClkReqNumber : 4;
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+ UINT8 ClkReqSupported : 1;
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+ UINT8 DeviceResetPadActiveHigh : 1;
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+ UINT32 DeviceResetPad;
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+} ROOT_PORT_CLK_INFO;
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+
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+typedef struct {
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+ UINT8 Section;
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+ UINT8 Pin;
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+} EXPANDER_GPIO_CONFIG;
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+
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+typedef enum {
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+ BoardGpioTypePch,
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+ BoardGpioTypeExpander,
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+ BoardGpioTypeNotSupported = 0xFF
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+} BOARD_GPIO_TYPE;
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+
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+typedef struct {
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+ UINT8 Type;
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+ UINT8 Reserved[3]; // alignment for COMMON_GPIO_CONFIG
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+ union {
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+ UINT32 Pin;
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+ EXPANDER_GPIO_CONFIG Expander;
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+ } u;
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+} BOARD_GPIO_CONFIG;
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+
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+// Do not change the encoding. It must correspond with PCH_PCIE_CLOCK_USAGE from PCH RC.
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+#define NOT_USED 0xFF
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+#define FREE_RUNNING 0x80
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+#define LAN_CLOCK 0x70
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+#define PCIE_PEG 0x40
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+#define PCIE_PCH 0x00
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+
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+typedef struct {
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+ UINT32 ClockUsage;
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+ UINT32 ClkReqSupported;
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+} PCIE_CLOCK_CONFIG;
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+
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+typedef union {
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+ UINT64 Blob;
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+ BOARD_GPIO_CONFIG BoardGpioConfig;
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+ ROOT_PORT_CLK_INFO Info;
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+ PCIE_CLOCK_CONFIG PcieClock;
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+} PCD64_BLOB;
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+
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+typedef union {
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+ UINT32 Blob;
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+ USB20_AFE Info;
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+} PCD32_BLOB;
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+
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+#ifndef IO_EXPANDER_DISABLED
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+#define IO_EXPANDER_DISABLED 0xFF
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+#endif
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+
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+#define SPD_DATA_SIZE 512
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+
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+#pragma pack()
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+
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+#endif // _PLATFORM_BOARD_CONFIG_H
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+
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