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+/** @file
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+ Produces the CPU I/O 2 Protocol.
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+
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+ Copyright (c) 2022 Loongson Technology Corporation Limited. All rights reserved.<BR>
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+
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+ SPDX-License-Identifier: BSD-2-Clause-Patent
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+
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+**/
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+
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+#include <PiDxe.h>
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+
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+#include <Protocol/CpuIo2.h>
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+
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+#include <Library/BaseLib.h>
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+#include <Library/DebugLib.h>
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+#include <Library/IoLib.h>
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+#include <Library/PcdLib.h>
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+#include <Library/UefiBootServicesTableLib.h>
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+#include "PciCpuIo2Dxe.h"
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+
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+//
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+// Handle for the CPU I/O 2 Protocol
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+//
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+STATIC EFI_HANDLE mHandle = NULL;
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+
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+//
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+// Lookup table for increment values based on transfer widths
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+//
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+STATIC CONST UINT8 mInStride[] = {
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+ 1, // EfiCpuIoWidthUint8
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+ 2, // EfiCpuIoWidthUint16
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+ 4, // EfiCpuIoWidthUint32
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+ 8, // EfiCpuIoWidthUint64
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+ 0, // EfiCpuIoWidthFifoUint8
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+ 0, // EfiCpuIoWidthFifoUint16
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+ 0, // EfiCpuIoWidthFifoUint32
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+ 0, // EfiCpuIoWidthFifoUint64
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+ 1, // EfiCpuIoWidthFillUint8
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+ 2, // EfiCpuIoWidthFillUint16
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+ 4, // EfiCpuIoWidthFillUint32
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+ 8 // EfiCpuIoWidthFillUint64
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+};
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+
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+//
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+// Lookup table for increment values based on transfer widths
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+//
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+STATIC CONST UINT8 mOutStride[] = {
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+ 1, // EfiCpuIoWidthUint8
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+ 2, // EfiCpuIoWidthUint16
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+ 4, // EfiCpuIoWidthUint32
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+ 8, // EfiCpuIoWidthUint64
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+ 1, // EfiCpuIoWidthFifoUint8
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+ 2, // EfiCpuIoWidthFifoUint16
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+ 4, // EfiCpuIoWidthFifoUint32
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+ 8, // EfiCpuIoWidthFifoUint64
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+ 0, // EfiCpuIoWidthFillUint8
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+ 0, // EfiCpuIoWidthFillUint16
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+ 0, // EfiCpuIoWidthFillUint32
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+ 0 // EfiCpuIoWidthFillUint64
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+};
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+
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+/**
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+ Check parameters to a CPU I/O 2 Protocol service request.
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+
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+ The I/O operations are carried out exactly as requested. The caller is responsible
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+ for satisfying any alignment and I/O width restrictions that a PI System on a
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+ platform might require. For example on some platforms, width requests of
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+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
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+ be handled by the driver.
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+
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+ @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port operation.
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+ @param[in] Width Signifies the width of the I/O or Memory operation.
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+ @param[in] Address The base address of the I/O operation.
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+ @param[in] Count The number of I/O operations to perform. The number of
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+ bytes moved is Width size * Count, starting at Address.
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+ @param[in] Buffer For read operations, the destination buffer to store the results.
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+ For write operations, the source buffer from which to write data.
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+
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+ @retval EFI_SUCCESS The parameters for this request pass the checks.
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+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
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+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
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+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
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+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
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+ and Count is not valid for this PI system.
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+**/
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+EFI_STATUS
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+CpuIoCheckParameter (
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+ IN BOOLEAN MmioOperation,
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+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
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+ IN UINT64 Address,
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+ IN UINTN Count,
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+ IN VOID *Buffer
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+ )
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+{
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+ UINT64 MaxCount;
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+ UINT64 Limit;
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+
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+ //
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+ // Check to see if Buffer is NULL
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+ //
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+ if (Buffer == NULL) {
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+ return EFI_INVALID_PARAMETER;
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+ }
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+
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+ //
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+ // Check to see if Width is in the valid range
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+ //
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+ if ((UINT32)Width >= EfiCpuIoWidthMaximum) {
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+ return EFI_INVALID_PARAMETER;
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+ }
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+
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+ //
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+ // For FIFO type, the target address won't increase during the access,
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+ // so treat Count as 1
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+ //
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+ if ((Width >= EfiCpuIoWidthFifoUint8)
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+ && (Width <= EfiCpuIoWidthFifoUint64))
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+ {
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+ Count = 1;
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+ }
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+
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+ //
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+ // Check to see if Width is in the valid range for I/O Port operations
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+ //
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+ Width = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
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+ if ((!MmioOperation)
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+ && (Width == EfiCpuIoWidthUint64))
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+ {
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+ return EFI_INVALID_PARAMETER;
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+ }
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+
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+ //
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+ // Check to see if Address is aligned
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+ //
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+ if ((Address & (UINT64) (mInStride[Width] - 1)) != 0) {
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+ return EFI_UNSUPPORTED;
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+ }
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+
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+ //
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+ // Check to see if any address associated with this transfer exceeds the maximum
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+ // allowed address. The maximum address implied by the parameters passed in is
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+ // Address + Size * Count. If the following condition is met, then the transfer
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+ // is not supported.
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+ //
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+ // Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1
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+ //
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+ // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count
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+ // can also be the maximum integer value supported by the CPU, this range
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+ // check must be adjusted to avoid all overflow conditions.
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+ //
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+ // The following form of the range check is equivalent but assumes that
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+ // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1).
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+ //
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+ Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS);
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+ if (Count == 0) {
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+ if (Address > Limit) {
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+ return EFI_UNSUPPORTED;
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+ }
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+ } else {
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+ MaxCount = RShiftU64 (Limit, Width);
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+ if (MaxCount < (Count - 1)) {
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+ return EFI_UNSUPPORTED;
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+ }
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+ if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
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+ return EFI_UNSUPPORTED;
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+ }
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+ }
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+
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+ //
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+ // Check to see if Buffer is aligned
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+ //
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+ if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != 0) {
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+ return EFI_UNSUPPORTED;
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+ }
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+
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+ return EFI_SUCCESS;
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+}
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+
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+/**
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+ Reads memory-mapped registers.
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+
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+ The I/O operations are carried out exactly as requested. The caller is responsible
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+ for satisfying any alignment and I/O width restrictions that a PI System on a
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+ platform might require. For example on some platforms, width requests of
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+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
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+ be handled by the driver.
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+
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+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
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+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
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+ each of the Count operations that is performed.
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+
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+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
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+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
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+ incremented for each of the Count operations that is performed. The read or
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+ write operation is performed Count times on the same Address.
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+
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+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
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+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
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+ incremented for each of the Count operations that is performed. The read or
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+ write operation is performed Count times from the first element of Buffer.
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+
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+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
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+ @param[in] Width Signifies the width of the I/O or Memory operation.
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+ @param[in] Address The base address of the I/O operation.
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+ @param[in] Count The number of I/O operations to perform. The number of
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+ bytes moved is Width size * Count, starting at Address.
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+ @param[out] Buffer For read operations, the destination buffer to store the results.
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+ For write operations, the source buffer from which to write data.
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+
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+ @retval EFI_SUCCESS The data was read from or written to the PI system.
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+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
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+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
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+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
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+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
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+ and Count is not valid for this PI system.
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+**/
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+EFI_STATUS
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+EFIAPI
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+CpuMemoryServiceRead (
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+ IN EFI_CPU_IO2_PROTOCOL *This,
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+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
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+ IN UINT64 Address,
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+ IN UINTN Count,
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+ OUT VOID *Buffer
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+ )
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+{
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+ EFI_STATUS Status;
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+ UINT8 InStride;
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+ UINT8 OutStride;
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+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
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+ UINT8 *Uint8Buffer;
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+ Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
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+ if (EFI_ERROR (Status)) {
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+ return Status;
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+ }
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+
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+ //
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+ // Select loop based on the width of the transfer
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+ //
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+ InStride = mInStride[Width];
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+ OutStride = mOutStride[Width];
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+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
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+ for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
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+ if (OperationWidth == EfiCpuIoWidthUint8) {
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+ *Uint8Buffer = MmioRead8 ((UINTN)Address);
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+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
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+ *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
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+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
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+ *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
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+ } else if (OperationWidth == EfiCpuIoWidthUint64) {
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+ *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
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+ }
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+ }
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+ return EFI_SUCCESS;
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+}
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+
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+/**
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+ Writes memory-mapped registers.
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+
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+ The I/O operations are carried out exactly as requested. The caller is responsible
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+ for satisfying any alignment and I/O width restrictions that a PI System on a
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+ platform might require. For example on some platforms, width requests of
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+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
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+ be handled by the driver.
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+
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+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
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+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
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+ each of the Count operations that is performed.
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+
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+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
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+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
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+ incremented for each of the Count operations that is performed. The read or
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+ write operation is performed Count times on the same Address.
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+
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+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
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+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
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+ incremented for each of the Count operations that is performed. The read or
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+ write operation is performed Count times from the first element of Buffer.
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+
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+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
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+ @param[in] Width Signifies the width of the I/O or Memory operation.
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+ @param[in] Address The base address of the I/O operation.
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+ @param[in] Count The number of I/O operations to perform. The number of
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+ bytes moved is Width size * Count, starting at Address.
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+ @param[in] Buffer For read operations, the destination buffer to store the results.
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+ For write operations, the source buffer from which to write data.
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+
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+ @retval EFI_SUCCESS The data was read from or written to the PI system.
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+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
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+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
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+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
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+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
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+ and Count is not valid for this PI system.
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+**/
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+EFI_STATUS
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+EFIAPI
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+CpuMemoryServiceWrite (
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+ IN EFI_CPU_IO2_PROTOCOL *This,
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+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
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+ IN UINT64 Address,
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+ IN UINTN Count,
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+ IN VOID *Buffer
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+ )
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+{
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+ EFI_STATUS Status;
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+ UINT8 InStride;
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+ UINT8 OutStride;
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+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
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+ UINT8 *Uint8Buffer;
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+
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+ Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
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+ if (EFI_ERROR (Status)) {
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+ return Status;
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+ }
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+
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+ //
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+ // Select loop based on the width of the transfer
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+ //
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+ InStride = mInStride[Width];
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+ OutStride = mOutStride[Width];
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+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
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+ for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
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+ if (OperationWidth == EfiCpuIoWidthUint8) {
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+ MmioWrite8 ((UINTN)Address, *Uint8Buffer);
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+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
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+ MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
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+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
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+ MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
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+ } else if (OperationWidth == EfiCpuIoWidthUint64) {
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+ MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
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+ }
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+ }
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+ return EFI_SUCCESS;
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+}
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+
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+/**
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+ Reads I/O registers.
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+
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+ The I/O operations are carried out exactly as requested. The caller is responsible
|
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+ for satisfying any alignment and I/O width restrictions that a PI System on a
|
|
|
+ platform might require. For example on some platforms, width requests of
|
|
|
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
|
|
|
+ be handled by the driver.
|
|
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+
|
|
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+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
|
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+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
|
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+ each of the Count operations that is performed.
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+
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+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
|
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+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
|
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+ incremented for each of the Count operations that is performed. The read or
|
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+ write operation is performed Count times on the same Address.
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+
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+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
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+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
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+ incremented for each of the Count operations that is performed. The read or
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|
+ write operation is performed Count times from the first element of Buffer.
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|
|
+
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+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
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+ @param[in] Width Signifies the width of the I/O or Memory operation.
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+ @param[in] Address The base address of the I/O operation.
|
|
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+ @param[in] Count The number of I/O operations to perform. The number of
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+ bytes moved is Width size * Count, starting at Address.
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|
|
+ @param[out] Buffer For read operations, the destination buffer to store the results.
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|
|
+ For write operations, the source buffer from which to write data.
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|
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+
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+ @retval EFI_SUCCESS The data was read from or written to the PI system.
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+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
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+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
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+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
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+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
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+ and Count is not valid for this PI system.
|
|
|
+**/
|
|
|
+EFI_STATUS
|
|
|
+EFIAPI
|
|
|
+CpuIoServiceRead (
|
|
|
+ IN EFI_CPU_IO2_PROTOCOL *This,
|
|
|
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
|
|
|
+ IN UINT64 Address,
|
|
|
+ IN UINTN Count,
|
|
|
+ OUT VOID *Buffer
|
|
|
+ )
|
|
|
+{
|
|
|
+ EFI_STATUS Status;
|
|
|
+ UINT8 InStride;
|
|
|
+ UINT8 OutStride;
|
|
|
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
|
|
|
+ UINT8 *Uint8Buffer;
|
|
|
+
|
|
|
+ Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);
|
|
|
+ if (EFI_ERROR (Status)) {
|
|
|
+ return Status;
|
|
|
+ }
|
|
|
+ Address += PcdGet64 (PcdPciIoTranslation);
|
|
|
+
|
|
|
+ //
|
|
|
+ // Select loop based on the width of the transfer
|
|
|
+ //
|
|
|
+ InStride = mInStride[Width];
|
|
|
+ OutStride = mOutStride[Width];
|
|
|
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
|
|
|
+
|
|
|
+ for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
|
|
|
+ if (OperationWidth == EfiCpuIoWidthUint8) {
|
|
|
+ *Uint8Buffer = MmioRead8 ((UINTN)Address);
|
|
|
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
|
|
|
+ *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
|
|
|
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
|
|
|
+ *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
|
|
|
+ }
|
|
|
+ }
|
|
|
+ return EFI_SUCCESS;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ Write I/O registers.
|
|
|
+
|
|
|
+ The I/O operations are carried out exactly as requested. The caller is responsible
|
|
|
+ for satisfying any alignment and I/O width restrictions that a PI System on a
|
|
|
+ platform might require. For example on some platforms, width requests of
|
|
|
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
|
|
|
+ be handled by the driver.
|
|
|
+
|
|
|
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
|
|
|
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
|
|
|
+ each of the Count operations that is performed.
|
|
|
+
|
|
|
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
|
|
|
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
|
|
|
+ incremented for each of the Count operations that is performed. The read or
|
|
|
+ write operation is performed Count times on the same Address.
|
|
|
+
|
|
|
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
|
|
|
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
|
|
|
+ incremented for each of the Count operations that is performed. The read or
|
|
|
+ write operation is performed Count times from the first element of Buffer.
|
|
|
+
|
|
|
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
|
|
|
+ @param[in] Width Signifies the width of the I/O or Memory operation.
|
|
|
+ @param[in] Address The base address of the I/O operation.
|
|
|
+ @param[in] Count The number of I/O operations to perform. The number of
|
|
|
+ bytes moved is Width size * Count, starting at Address.
|
|
|
+ @param[in] Buffer For read operations, the destination buffer to store the results.
|
|
|
+ For write operations, the source buffer from which to write data.
|
|
|
+
|
|
|
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
|
|
|
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
|
|
|
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
|
|
|
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
|
|
|
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
|
|
|
+ and Count is not valid for this PI system.
|
|
|
+**/
|
|
|
+EFI_STATUS
|
|
|
+EFIAPI
|
|
|
+CpuIoServiceWrite (
|
|
|
+ IN EFI_CPU_IO2_PROTOCOL *This,
|
|
|
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
|
|
|
+ IN UINT64 Address,
|
|
|
+ IN UINTN Count,
|
|
|
+ IN VOID *Buffer
|
|
|
+ )
|
|
|
+{
|
|
|
+ EFI_STATUS Status;
|
|
|
+ UINT8 InStride;
|
|
|
+ UINT8 OutStride;
|
|
|
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
|
|
|
+ UINT8 *Uint8Buffer;
|
|
|
+
|
|
|
+ //
|
|
|
+ // Make sure the parameters are valid
|
|
|
+ //
|
|
|
+ Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);
|
|
|
+ if (EFI_ERROR (Status)) {
|
|
|
+ return Status;
|
|
|
+ }
|
|
|
+
|
|
|
+ Address += PcdGet64 (PcdPciIoTranslation);
|
|
|
+
|
|
|
+ //
|
|
|
+ // Select loop based on the width of the transfer
|
|
|
+ //
|
|
|
+ InStride = mInStride[Width];
|
|
|
+ OutStride = mOutStride[Width];
|
|
|
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
|
|
|
+
|
|
|
+ for (Uint8Buffer = (UINT8 *)Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
|
|
|
+ if (OperationWidth == EfiCpuIoWidthUint8) {
|
|
|
+ MmioWrite8 ((UINTN)Address, *Uint8Buffer);
|
|
|
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
|
|
|
+ MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
|
|
|
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
|
|
|
+ MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
|
|
|
+ }
|
|
|
+ }
|
|
|
+ return EFI_SUCCESS;
|
|
|
+}
|
|
|
+
|
|
|
+//
|
|
|
+// CPU I/O 2 Protocol instance
|
|
|
+//
|
|
|
+STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
|
|
|
+ {
|
|
|
+ CpuMemoryServiceRead,
|
|
|
+ CpuMemoryServiceWrite
|
|
|
+ },
|
|
|
+ {
|
|
|
+ CpuIoServiceRead,
|
|
|
+ CpuIoServiceWrite
|
|
|
+ }
|
|
|
+};
|
|
|
+
|
|
|
+/**
|
|
|
+ The user Entry Point for module CpuIo2Dxe. The user code starts with this function.
|
|
|
+
|
|
|
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
|
|
|
+ @param[in] SystemTable A pointer to the EFI System Table.
|
|
|
+
|
|
|
+ @retval EFI_SUCCESS The entry point is executed successfully.
|
|
|
+ @retval other Some error occurs when executing this entry point.
|
|
|
+**/
|
|
|
+EFI_STATUS
|
|
|
+EFIAPI
|
|
|
+PciCpuIo2Initialize (
|
|
|
+ IN EFI_HANDLE ImageHandle,
|
|
|
+ IN EFI_SYSTEM_TABLE *SystemTable
|
|
|
+ )
|
|
|
+{
|
|
|
+ EFI_STATUS Status;
|
|
|
+
|
|
|
+ ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);
|
|
|
+ Status = gBS->InstallMultipleProtocolInterfaces (
|
|
|
+ &mHandle,
|
|
|
+ &gEfiCpuIo2ProtocolGuid, &mCpuIo2,
|
|
|
+ NULL
|
|
|
+ );
|
|
|
+ ASSERT_EFI_ERROR (Status);
|
|
|
+ return Status;
|
|
|
+}
|