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@@ -37,7 +37,7 @@
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| Y | Y | Y | Y | 3 |
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----------------------------------------
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- Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
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+ Copyright (c) 2020 - 2023, Ampere Computing LLC. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@@ -55,6 +55,12 @@
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#include "RootComplexNVParam.h"
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+typedef enum {
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+ Gen3Preset = 0,
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+ Gen4Preset,
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+ GenPresetMax
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+} NVPARAM_PCIE_PRESET_TYPE;
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+
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STATIC
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BOOLEAN
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IsEmptyRC (
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@@ -144,85 +150,233 @@ SetRootComplexBifurcation (
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}
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}
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-VOID
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+DEV_MAP_MODE
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GetDefaultDevMap (
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- AC01_ROOT_COMPLEX *RootComplex
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+ IN AC01_ROOT_COMPLEX *RootComplex,
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+ IN BOOLEAN IsGetDevMapLow
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)
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{
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- if (RootComplex->Pcie[PcieController0].Active
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- && RootComplex->Pcie[PcieController1].Active
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- && RootComplex->Pcie[PcieController2].Active
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- && RootComplex->Pcie[PcieController3].Active) {
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- RootComplex->DefaultDevMapLow = DevMapMode4;
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- } else if (RootComplex->Pcie[PcieController0].Active
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- && RootComplex->Pcie[PcieController2].Active
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- && RootComplex->Pcie[PcieController3].Active) {
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- RootComplex->DefaultDevMapLow = DevMapMode3;
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- } else if (RootComplex->Pcie[PcieController0].Active
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- && RootComplex->Pcie[PcieController2].Active) {
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- RootComplex->DefaultDevMapLow = DevMapMode2;
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- } else {
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- RootComplex->DefaultDevMapLow = DevMapMode1;
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- }
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+ UINT8 StartIndex;
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+ DEV_MAP_MODE DevMapMode;
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+
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+ DevMapMode = MaxDevMapMode;
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+ StartIndex = IsGetDevMapLow ? PcieController0 : PcieController4;
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+
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+ while (DevMapMode >= DevMapMode1)
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+ {
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+ switch (DevMapMode) {
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+ case DevMapMode4:
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+ if (RootComplex->Pcie[StartIndex].Active
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+ && RootComplex->Pcie[StartIndex + 1].Active
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+ && RootComplex->Pcie[StartIndex + 2].Active
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+ && RootComplex->Pcie[StartIndex + 3].Active) {
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+ return DevMapMode4;
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+ }
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+ break;
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+ case DevMapMode3:
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+ if (RootComplex->Pcie[StartIndex].Active
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+ && RootComplex->Pcie[StartIndex + 2].Active
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+ && RootComplex->Pcie[StartIndex + 3].Active) {
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+ return DevMapMode3;
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+ }
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+ break;
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+ case DevMapMode2:
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+ if (RootComplex->Pcie[StartIndex].Active
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+ && RootComplex->Pcie[StartIndex + 2].Active) {
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+ return DevMapMode2;
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+ }
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+ break;
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+ default:
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+ return DevMapMode1;
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+ }
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- if (RootComplex->Pcie[PcieController4].Active
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- && RootComplex->Pcie[PcieController5].Active
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- && RootComplex->Pcie[PcieController6].Active
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- && RootComplex->Pcie[PcieController7].Active) {
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- RootComplex->DefaultDevMapHigh = DevMapMode4;
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- } else if (RootComplex->Pcie[PcieController4].Active
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- && RootComplex->Pcie[PcieController6].Active
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- && RootComplex->Pcie[PcieController7].Active) {
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- RootComplex->DefaultDevMapHigh = DevMapMode3;
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- } else if (RootComplex->Pcie[PcieController4].Active
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- && RootComplex->Pcie[PcieController6].Active) {
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- RootComplex->DefaultDevMapHigh = DevMapMode2;
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- } else {
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- RootComplex->DefaultDevMapHigh = DevMapMode1;
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+ DevMapMode--;
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}
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+ return DevMapMode1;
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+}
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+
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+VOID
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+GetDevMap (
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+ IN OUT AC01_ROOT_COMPLEX *RootComplex
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+ )
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+{
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+ //
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+ // Get default Devmap low and configure Devmap low accordingly.
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+ //
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+ RootComplex->DefaultDevMapLow = GetDefaultDevMap (RootComplex, TRUE);
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if (RootComplex->DevMapLow == 0) {
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RootComplex->DevMapLow = RootComplex->DefaultDevMapLow;
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}
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+ //
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+ // Get default Devmap high and configure Devmap high accordingly.
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+ //
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+ RootComplex->DefaultDevMapHigh = IsAc01Processor () ? GetDefaultDevMap (RootComplex, FALSE) : DevMapMode1;
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if (RootComplex->Type == RootComplexTypeB && RootComplex->DevMapHigh == 0) {
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RootComplex->DevMapHigh = RootComplex->DefaultDevMapHigh;
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}
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+ //
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+ // Set bifurcation bases on Devmap high and Devmap low.
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+ //
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SetRootComplexBifurcation (RootComplex, PcieController0, RootComplex->DevMapLow);
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if (RootComplex->Type == RootComplexTypeB) {
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SetRootComplexBifurcation (RootComplex, PcieController4, RootComplex->DevMapHigh);
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}
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}
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+UINT8
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+GetMaxController (
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+ IN AC01_ROOT_COMPLEX *RootComplex
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+ )
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+{
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+ if (IsAc01Processor ()) {
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+ return MaxPcieControllerOfRootComplexA;
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+ }
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+
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+ return RootComplex->MaxPcieController;
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+}
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+
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+NVPARAM
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+CalculateNvParamOffset (
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+ IN AC01_ROOT_COMPLEX *RootComplex,
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+ IN UINT8 PaddingOrder,
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+ IN UINT8 StartIndex,
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+ IN UINT64 StartOffset
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+ )
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+{
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+ UINT8 NeededPadding;
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+ INT8 PositionFromStartIndex;
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+ NVPARAM NvParamOffset;
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+
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+
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+ NeededPadding = RootComplex->ID - PaddingOrder;
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+ PositionFromStartIndex = (RootComplex->ID - StartIndex) + NeededPadding;
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+ NvParamOffset = StartOffset + PositionFromStartIndex * NV_PARAM_ENTRYSIZE;
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+
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+ return NvParamOffset;
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+}
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+
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+EFI_STATUS_CODE_TYPE
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+GetNvParamOffsetLane (
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+ IN AC01_ROOT_COMPLEX *RootComplex,
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+ OUT NVPARAM *NvParamOffset
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+ )
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+{
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+ BOOLEAN IsAc01;
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+ BOOLEAN IsRootComplexTypeA;
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+ BOOLEAN IsSocket0;
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+ UINT8 StartIndex;
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+ UINT64 StartOffset;
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+ UINT8 PaddingOrder;
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+
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+ IsSocket0 = RootComplex->Socket == 0 ? TRUE : FALSE;
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+ IsAc01 = IsAc01Processor ();
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+ IsRootComplexTypeA = RootComplex->Type == RootComplexTypeA ? TRUE : FALSE;
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+
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+ if (!IsAc01 && (RootComplex->ID >= MaxPcieControllerOfRootComplexA)) {
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+ // Because from NV_SI_RO_BOARD_S0_RCA4_CFG to NV_SI_RO_BOARD_S0_RCA7_CFG for supporting
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+ // Altra Max are not sequential arrangement with NV_SI_RO_BOARD_S0_RCA0_CFG
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+ // so the start index will be the first Root Complex ID which using these NVParams
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+ // (NV_SI_RO_BOARD_S0_RCA4_CFG to NV_SI_RO_BOARD_S0_RCA7_CFG) to support Altra Max processor.
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+ StartIndex = 4;
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+ StartOffset = IsSocket0 ? NV_SI_RO_BOARD_S0_RCA4_CFG : NV_SI_RO_BOARD_S1_RCA4_CFG;
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+ PaddingOrder = RootComplex->ID;
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+ } else {
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+ StartIndex = 0;
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+ StartOffset = IsSocket0 ? NV_SI_RO_BOARD_S0_RCA0_CFG : NV_SI_RO_BOARD_S1_RCA0_CFG;
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+ PaddingOrder = IsRootComplexTypeA ? RootComplex->ID : MaxRootComplexA;
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+ }
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+
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+ *NvParamOffset = CalculateNvParamOffset (RootComplex, PaddingOrder, StartIndex, StartOffset);
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+ return EFI_SUCCESS;
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+}
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+
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+EFI_STATUS
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+GetNvParamOffsetPreset (
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+ IN AC01_ROOT_COMPLEX *RootComplex,
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+ IN NVPARAM_PCIE_PRESET_TYPE PresetType,
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+ OUT NVPARAM *NvParamOffset
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+ )
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+{
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+ BOOLEAN IsAc01;
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+ BOOLEAN IsRootComplexTypeA;
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+ BOOLEAN IsSocket0;
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+ UINT8 StartIndex;
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+ UINT64 StartOffset;
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+ UINT8 PaddingOrder;
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+
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+ IsSocket0 = RootComplex->Socket == 0 ? TRUE : FALSE;
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+ IsAc01 = IsAc01Processor ();
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+ IsRootComplexTypeA = RootComplex->Type == RootComplexTypeA ? TRUE : FALSE;
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+
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+ switch (PresetType) {
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+ case Gen3Preset:
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+ if (IsAc01) {
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+ StartOffset = IsSocket0 ? NV_SI_RO_BOARD_S0_RCA0_TXRX_G3PRESET :
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+ NV_SI_RO_BOARD_S1_RCA2_TXRX_G3PRESET;
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+ } else {
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+ StartOffset = IsSocket0 ? NV_SI_RO_BOARD_MQ_S0_RCA0_TXRX_G3PRESET :
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+ NV_SI_RO_BOARD_MQ_S1_RCA2_TXRX_G3PRESET;
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+ }
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+ break;
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+
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+ case Gen4Preset:
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+ if (IsAc01) {
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+ StartOffset = IsSocket0 ? NV_SI_RO_BOARD_S0_RCA0_TXRX_G4PRESET :
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+ NV_SI_RO_BOARD_S1_RCA2_TXRX_G4PRESET;
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+ } else {
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+ StartOffset = IsSocket0 ? NV_SI_RO_BOARD_MQ_S0_RCA0_TXRX_G4PRESET :
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+ NV_SI_RO_BOARD_MQ_S1_RCA2_TXRX_G4PRESET;
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+ }
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+ break;
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+
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+ default:
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+ return EFI_INVALID_PARAMETER;
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+ }
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+
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+ //
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+ // For Socket 0, NVParams for all Root Complexes are supported so starting from RCA0.
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+ // For Socket 1, NVParams for RCA0 and RCA1 are not supported so starting from RCA2.
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+ //
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+ StartIndex = IsSocket0 ? 0 : 2;
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+ //
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+ // There're two NVParam entries per RootComplexTypeB
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+ // so padding need to be start from MaxRootComplexA to
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+ // get the first NVParam entry of RootComplexTypeB
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+ //
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+ PaddingOrder = IsRootComplexTypeA ? RootComplex->ID : MaxRootComplexA;
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+
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+ *NvParamOffset = CalculateNvParamOffset (RootComplex, PaddingOrder, StartIndex, StartOffset);
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+
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+ return EFI_SUCCESS;
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+}
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+
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VOID
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GetLaneAllocation (
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- AC01_ROOT_COMPLEX *RootComplex
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+ IN OUT AC01_ROOT_COMPLEX *RootComplex
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)
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{
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EFI_STATUS Status;
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INTN RPIndex;
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NVPARAM NvParamOffset;
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- UINT32 Value, Width;
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+ UINT32 Value;
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+ UINT32 Width;
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+ UINT32 MaxController;
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- // Retrieve lane allocation and capabilities for each controller
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- if (RootComplex->Type == RootComplexTypeA) {
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- NvParamOffset = (RootComplex->Socket == 0) ? NV_SI_RO_BOARD_S0_RCA0_CFG : NV_SI_RO_BOARD_S1_RCA0_CFG;
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- NvParamOffset += RootComplex->ID * NV_PARAM_ENTRYSIZE;
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+ Status = GetNvParamOffsetLane (RootComplex, &NvParamOffset);
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+ if (!EFI_ERROR (Status)) {
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+ Status = NVParamGet (NvParamOffset, NV_PERM_ALL, &Value);
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+ if (EFI_ERROR (Status)) {
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+ Value = 0;
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+ }
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} else {
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- //
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- // There're two NVParam entries per RootComplexTypeB
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- //
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- NvParamOffset = (RootComplex->Socket == 0) ? NV_SI_RO_BOARD_S0_RCB0_LO_CFG : NV_SI_RO_BOARD_S1_RCB0_LO_CFG;
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- NvParamOffset += (RootComplex->ID - MaxRootComplexA) * (NV_PARAM_ENTRYSIZE * 2);
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- }
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-
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- Status = NVParamGet (NvParamOffset, NV_PERM_ALL, &Value);
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- if (EFI_ERROR (Status)) {
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Value = 0;
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}
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- for (RPIndex = 0; RPIndex < MaxPcieControllerOfRootComplexA; RPIndex++) {
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+ MaxController = GetMaxController (RootComplex);
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+ for (RPIndex = PcieController0; RPIndex < MaxController; RPIndex++) {
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Width = (Value >> (RPIndex * BITS_PER_BYTE)) & BYTE_MASK;
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switch (Width) {
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case 1:
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@@ -278,78 +432,6 @@ GetLaneAllocation (
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}
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}
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-NVPARAM
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-GetGen3PresetNvParamOffset (
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- AC01_ROOT_COMPLEX *RootComplex
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- )
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-{
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- NVPARAM NvParamOffset;
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-
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- if (RootComplex->Socket == 0) {
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- if (RootComplex->Type == RootComplexTypeA) {
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- if (RootComplex->ID < MaxRootComplexA) {
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- NvParamOffset = NV_SI_RO_BOARD_S0_RCA0_TXRX_G3PRESET + RootComplex->ID * NV_PARAM_ENTRYSIZE;
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- } else {
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- NvParamOffset = NV_SI_RO_BOARD_S0_RCA4_TXRX_G3PRESET + (RootComplex->ID - MaxRootComplexA) * NV_PARAM_ENTRYSIZE;
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- }
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- } else {
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- //
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- // There're two NVParam entries per RootComplexTypeB
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- //
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- NvParamOffset = NV_SI_RO_BOARD_S0_RCB0A_TXRX_G3PRESET + (RootComplex->ID - MaxRootComplexA) * (NV_PARAM_ENTRYSIZE * 2);
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- }
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- } else if (RootComplex->Type == RootComplexTypeA) {
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- if (RootComplex->ID < MaxRootComplexA) {
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- NvParamOffset = NV_SI_RO_BOARD_S1_RCA2_TXRX_G3PRESET + (RootComplex->ID - 2) * NV_PARAM_ENTRYSIZE;
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- } else {
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- NvParamOffset = NV_SI_RO_BOARD_S1_RCA4_TXRX_G3PRESET + (RootComplex->ID - MaxRootComplexA) * NV_PARAM_ENTRYSIZE;
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- }
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- } else {
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- //
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- // There're two NVParam entries per RootComplexTypeB
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- //
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- NvParamOffset = NV_SI_RO_BOARD_S1_RCB0A_TXRX_G3PRESET + (RootComplex->ID - MaxRootComplexA) * (NV_PARAM_ENTRYSIZE * 2);
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- }
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-
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- return NvParamOffset;
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-}
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-
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-NVPARAM
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-GetGen4PresetNvParamOffset (
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- AC01_ROOT_COMPLEX *RootComplex
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- )
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-{
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- NVPARAM NvParamOffset;
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-
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- if (RootComplex->Socket == 0) {
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- if (RootComplex->Type == RootComplexTypeA) {
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- if (RootComplex->ID < MaxRootComplexA) {
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- NvParamOffset = NV_SI_RO_BOARD_S0_RCA0_TXRX_G4PRESET + RootComplex->ID * NV_PARAM_ENTRYSIZE;
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- } else {
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- NvParamOffset = NV_SI_RO_BOARD_S0_RCA4_TXRX_G4PRESET + (RootComplex->ID - MaxRootComplexA) * NV_PARAM_ENTRYSIZE;
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- }
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- } else {
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- //
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- // There're two NVParam entries per RootComplexTypeB
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- //
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- NvParamOffset = NV_SI_RO_BOARD_S0_RCB0A_TXRX_G4PRESET + (RootComplex->ID - MaxRootComplexA) * (NV_PARAM_ENTRYSIZE * 2);
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- }
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- } else if (RootComplex->Type == RootComplexTypeA) {
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- if (RootComplex->ID < MaxRootComplexA) {
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- NvParamOffset = NV_SI_RO_BOARD_S1_RCA2_TXRX_G4PRESET + (RootComplex->ID - 2) * NV_PARAM_ENTRYSIZE;
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- } else {
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- NvParamOffset = NV_SI_RO_BOARD_S1_RCA4_TXRX_G4PRESET + (RootComplex->ID - MaxRootComplexA) * NV_PARAM_ENTRYSIZE;
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- }
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- } else {
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- //
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- // There're two NVParam entries per RootComplexTypeB
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- //
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- NvParamOffset = NV_SI_RO_BOARD_S1_RCB0A_TXRX_G4PRESET + (RootComplex->ID - MaxRootComplexA) * (NV_PARAM_ENTRYSIZE * 2);
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- }
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-
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- return NvParamOffset;
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-}
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-
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VOID
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GetPresetSetting (
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AC01_ROOT_COMPLEX *RootComplex
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@@ -366,9 +448,11 @@ GetPresetSetting (
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RootComplex->PresetGen4[Index] = PRESET_INVALID;
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}
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- NvParamOffset = GetGen3PresetNvParamOffset (RootComplex);
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-
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- Status = NVParamGet (NvParamOffset, NV_PERM_ALL, &Value);
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+ // Get NVParam offset of Gen3 preset
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+ Status = GetNvParamOffsetPreset (RootComplex, Gen3Preset, &NvParamOffset);
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+ if (!EFI_ERROR (Status)) {
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+ Status = NVParamGet (NvParamOffset, NV_PERM_ALL, &Value);
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+ }
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if (!EFI_ERROR (Status)) {
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for (Index = 0; Index < MaxPcieControllerOfRootComplexA; Index++) {
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RootComplex->PresetGen3[Index] = (Value >> (Index * BITS_PER_BYTE)) & BYTE_MASK;
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@@ -385,9 +469,11 @@ GetPresetSetting (
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}
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}
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- NvParamOffset = GetGen4PresetNvParamOffset (RootComplex);
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-
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- Status = NVParamGet (NvParamOffset, NV_PERM_ALL, &Value);
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+ // Get NVParam offset of Gen4 preset.
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+ Status = GetNvParamOffsetPreset (RootComplex, Gen4Preset, &NvParamOffset);
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+ if (!EFI_ERROR (Status)) {
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+ Status = NVParamGet (NvParamOffset, NV_PERM_ALL, &Value);
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+ }
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if (!EFI_ERROR (Status)) {
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for (Index = 0; Index < MaxPcieControllerOfRootComplexA; Index++) {
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RootComplex->PresetGen4[Index] = (Value >> (Index * BITS_PER_BYTE)) & BYTE_MASK;
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@@ -415,6 +501,7 @@ GetMaxSpeedGen (
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UINT8 ErrataSpeedDevMap4[MaxPcieControllerOfRootComplexA] = { LINK_SPEED_GEN1, LINK_SPEED_GEN1, LINK_SPEED_GEN1, LINK_SPEED_GEN1 }; // Bifurcation 3: x4 x4 x4 x4 (PCIE_ERRATA_SPEED1)
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UINT8 ErrataSpeedRcb[MaxPcieControllerOfRootComplexA] = { LINK_SPEED_GEN1, LINK_SPEED_GEN1, LINK_SPEED_GEN1, LINK_SPEED_GEN1 }; // RootComplexTypeB PCIE_ERRATA_SPEED1
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UINT8 Idx;
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+ UINT8 MaxController;
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UINT8 *MaxGen;
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ASSERT (MaxPcieControllerOfRootComplexA == 4);
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@@ -452,7 +539,8 @@ GetMaxSpeedGen (
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}
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}
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- for (Idx = 0; Idx < MaxPcieControllerOfRootComplexA; Idx++) {
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+ MaxController = GetMaxController (RootComplex);
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+ for (Idx = 0; Idx < MaxController; Idx++) {
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RootComplex->Pcie[Idx].MaxGen = RootComplex->Pcie[Idx].Active ? MaxGen[Idx] : LINK_SPEED_NONE;
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}
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@@ -509,6 +597,6 @@ ParseRootComplexNVParamData (
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GetPresetSetting (RootComplex);
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GetLaneAllocation (RootComplex);
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- GetDefaultDevMap (RootComplex);
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+ GetDevMap (RootComplex);
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GetMaxSpeedGen (RootComplex);
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}
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