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@@ -33,8 +33,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
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PCI_HB0RB0_ECAM_BASE, //ecam
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0x80, //BusBase
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0x87, //BusLimit
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- PCI_HB0RB0_PCIREGION_BASE, //Membase
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- PCI_HB0RB0_CPUMEMREGIONBASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //Memlimit
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PCI_HB0RB0_IO_BASE, //IoBase
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(PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
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PCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBase
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@@ -49,8 +47,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
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PCI_HB0RB1_ECAM_BASE,//ecam
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0x90, //BusBase
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0x97, //BusLimit
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- PCI_HB0RB1_PCIREGION_BASE, //Membase
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- PCI_HB0RB1_CPUMEMREGIONBASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //MemLimit
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(PCI_HB0RB1_IO_BASE), //IoBase
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(PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimit
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PCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBase
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@@ -65,8 +61,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
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PCI_HB0RB2_ECAM_BASE,
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0xF8, //BusBase
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0xFF, //BusLimit
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- PCI_HB0RB2_CPUMEMREGIONBASE ,//MemBase
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- PCI_HB0RB2_CPUMEMREGIONBASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit
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(PCI_HB0RB2_IO_BASE), //IOBase
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(PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimit
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PCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBase
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@@ -82,8 +76,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
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PCI_HB0RB3_ECAM_BASE,
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0xb0, //BusBase
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0xb7, //BusLimit
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- (PCI_HB0RB3_ECAM_BASE), //MemBase
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- (PCI_HB0RB3_CPUMEMREGIONBASE + PCI_HB0RB3_PCIREGION_SIZE - 1), //MemLimit
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(PCI_HB0RB3_IO_BASE), //IoBase
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(PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB3_IO_SIZE - 1), //IoLimit
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PCI_HB0RB3_CPUMEMREGIONBASE,
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@@ -98,8 +90,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
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PCI_HB0RB4_ECAM_BASE, //ecam
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0x88, //BusBase
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0x8f, //BusLimit
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- PCI_HB0RB4_CPUMEMREGIONBASE, //Membase
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- PCI_HB0RB4_CPUMEMREGIONBASE + PCI_HB0RB4_PCIREGION_SIZE - 1, //Memlimit
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PCI_HB0RB4_IO_BASE, //IoBase
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(PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB4_IO_SIZE - 1), //IoLimit
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PCI_HB0RB4_CPUMEMREGIONBASE, //CpuMemRegionBase
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@@ -114,8 +104,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
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PCI_HB0RB5_ECAM_BASE,//ecam
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0x78, //BusBase
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0x7F, //BusLimit
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- PCI_HB0RB5_CPUMEMREGIONBASE, //Membase
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- PCI_HB0RB5_CPUMEMREGIONBASE + PCI_HB0RB5_PCIREGION_SIZE - 1, //MemLimit
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(PCI_HB0RB5_IO_BASE), //IoBase
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(PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB5_IO_SIZE - 1), //IoLimit
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PCI_HB0RB5_CPUMEMREGIONBASE, //CpuMemRegionBase
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@@ -130,8 +118,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
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PCI_HB0RB6_ECAM_BASE,
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0xC0, //BusBase
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0xC7, //BusLimit
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- PCI_HB0RB6_PCIREGION_BASE ,//MemBase
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- PCI_HB0RB6_CPUMEMREGIONBASE + PCI_HB0RB6_PCIREGION_SIZE - 1, //MemLimit
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(PCI_HB0RB6_IO_BASE), //IOBase
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(PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB6_IO_SIZE - 1), //IoLimit
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PCI_HB0RB6_CPUMEMREGIONBASE, //CpuMemRegionBase
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@@ -147,8 +133,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
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PCI_HB0RB7_ECAM_BASE,
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0x90, //BusBase
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0x97, //BusLimit
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- PCI_HB0RB7_CPUMEMREGIONBASE, //MemBase
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- PCI_HB0RB7_CPUMEMREGIONBASE + PCI_HB0RB7_PCIREGION_SIZE - 1, //MemLimit
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(PCI_HB0RB7_IO_BASE), //IoBase
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(PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB7_IO_SIZE - 1), //IoLimit
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PCI_HB0RB7_CPUMEMREGIONBASE,
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@@ -165,8 +149,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
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PCI_HB1RB0_ECAM_BASE,
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0x80, //BusBase
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0x87, //BusLimit
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- (PCI_HB1RB0_ECAM_BASE), //MemBase
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- (PCI_HB1RB0_CPUMEMREGIONBASE + PCI_HB1RB0_PCIREGION_SIZE - 1), //MemLimit
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PCI_HB1RB0_IO_BASE, //IoBase
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(PCI_HB1RB0_CPUIOREGIONBASE + PCI_HB1RB0_IO_SIZE - 1), //IoLimit
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PCI_HB1RB0_CPUMEMREGIONBASE, //CpuMemRegionBase
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@@ -181,8 +163,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
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PCI_HB1RB1_ECAM_BASE,
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0x90, //BusBase
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0x97, //BusLimit
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- (PCI_HB1RB1_ECAM_BASE), //MemBase
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- (PCI_HB1RB1_CPUMEMREGIONBASE + PCI_HB1RB1_PCIREGION_SIZE - 1), //MemLimit
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PCI_HB1RB1_IO_BASE, //IoBase
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(PCI_HB1RB1_CPUIOREGIONBASE + PCI_HB1RB1_IO_SIZE - 1), //IoLimit
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PCI_HB1RB1_CPUMEMREGIONBASE, //CpuMemRegionBase
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@@ -197,8 +177,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
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PCI_HB1RB2_ECAM_BASE,
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0x10, //BusBase
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0x1f, //BusLimit
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- PCI_HB1RB2_CPUMEMREGIONBASE, //MemBase
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- PCI_HB1RB2_CPUMEMREGIONBASE + PCI_HB1RB2_PCIREGION_SIZE - 1, //MemLimit
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PCI_HB1RB2_IO_BASE, //IoBase
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(PCI_HB1RB2_CPUIOREGIONBASE + PCI_HB1RB2_IO_SIZE - 1), //IoLimit
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PCI_HB1RB2_CPUMEMREGIONBASE, //CpuMemRegionBase
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@@ -214,8 +192,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
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PCI_HB1RB3_ECAM_BASE,
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0xb0, //BusBase
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0xb7, //BusLimit
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- (PCI_HB1RB3_ECAM_BASE), //MemBase
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- (PCI_HB1RB3_CPUMEMREGIONBASE + PCI_HB1RB3_PCIREGION_SIZE - 1), //MemLimit
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PCI_HB1RB3_IO_BASE, //IoBase
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(PCI_HB1RB3_CPUIOREGIONBASE + PCI_HB1RB3_IO_SIZE - 1), //IoLimit
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PCI_HB1RB3_CPUMEMREGIONBASE, //CpuMemRegionBase
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@@ -230,8 +206,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
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PCI_HB1RB4_ECAM_BASE,
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0x20, //BusBase
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0x2f, //BusLimit
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- PCI_HB1RB4_CPUMEMREGIONBASE, //MemBase
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- PCI_HB1RB4_CPUMEMREGIONBASE + PCI_HB1RB4_PCIREGION_SIZE - 1, //MemLimit
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PCI_HB1RB4_IO_BASE, //IoBase
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(PCI_HB1RB4_CPUIOREGIONBASE + PCI_HB1RB4_IO_SIZE - 1), //IoLimit
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PCI_HB1RB4_CPUMEMREGIONBASE, //CpuMemRegionBase
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@@ -246,8 +220,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
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PCI_HB1RB5_ECAM_BASE,
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0x30, //BusBase
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0x3f, //BusLimit
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- PCI_HB1RB5_CPUMEMREGIONBASE, //MemBase
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- PCI_HB1RB5_CPUMEMREGIONBASE + PCI_HB1RB5_PCIREGION_SIZE - 1, //MemLimit
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PCI_HB1RB5_IO_BASE, //IoBase
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(PCI_HB1RB5_CPUIOREGIONBASE + PCI_HB1RB5_IO_SIZE - 1), //IoLimit
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PCI_HB1RB5_CPUMEMREGIONBASE, //CpuMemRegionBase
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@@ -262,8 +234,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
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PCI_HB1RB6_ECAM_BASE,
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0xa8, //BusBase
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0xaf, //BusLimit
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- (PCI_HB1RB6_ECAM_BASE), //MemBase
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- PCI_HB1RB6_CPUMEMREGIONBASE + PCI_HB1RB6_PCIREGION_SIZE - 1, //MemLimit
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PCI_HB1RB6_IO_BASE, //IoBase
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(PCI_HB1RB6_CPUIOREGIONBASE + PCI_HB1RB6_IO_SIZE - 1), //IoLimit
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PCI_HB1RB6_CPUMEMREGIONBASE, //CpuMemRegionBase
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@@ -279,8 +249,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
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PCI_HB1RB7_ECAM_BASE,
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0xb8, //BusBase
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0xbf, //BusLimit
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- (PCI_HB1RB7_ECAM_BASE), //MemBase
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- PCI_HB1RB7_CPUMEMREGIONBASE + PCI_HB1RB7_PCIREGION_SIZE - 1, //MemLimit
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PCI_HB1RB7_IO_BASE, //IoBase
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(PCI_HB1RB7_CPUIOREGIONBASE + PCI_HB1RB7_IO_SIZE - 1), //IoLimit
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PCI_HB1RB7_CPUMEMREGIONBASE, //CpuMemRegionBase
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