/**@file
  U500 VC707 Device Tree, compatible with fu540-c000 platform.

  SPDX-License-Identifier: (GPL-2.0 OR MIT)
  Copyright (c) 2018-2019 SiFive, Inc

  SPDX-License-Identifier: BSD-2-Clause-Patent

**/

/dts-v1/;

#include "sifive-fu500-prci.h"

/ {
        #address-cells = <2>;
        #size-cells = <2>;
        compatible = "sifive,fu540-c000", "sifive,fu540";

        aliases {
                serial0 = &uart0;
                ethernet0 = &eth0;
        };

        chosen {
        };

        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
                cpu0: cpu@0 {
                        compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
                        d-cache-block-size = <64>;
                        d-cache-sets = <64>;
                        d-cache-size = <32768>;
                        d-tlb-sets = <1>;
                        d-tlb-size = <32>;
                        device_type = "cpu";
                        i-cache-block-size = <64>;
                        i-cache-sets = <64>;
                        i-cache-size = <32768>;
                        i-tlb-sets = <1>;
                        i-tlb-size = <32>;
                        mmu-type = "riscv,sv39";
                        reg = <0>;
                        riscv,isa = "rv64imafdc";
                        tlb-split;
                        next-level-cache = <&l2cache>;
                        cpu0_intc: interrupt-controller {
                                #interrupt-cells = <1>;
                                compatible = "riscv,cpu-intc";
                                interrupt-controller;
                        };
                };
                cpu1: cpu@1 {
                        compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
                        d-cache-block-size = <64>;
                        d-cache-sets = <64>;
                        d-cache-size = <32768>;
                        d-tlb-sets = <1>;
                        d-tlb-size = <32>;
                        device_type = "cpu";
                        i-cache-block-size = <64>;
                        i-cache-sets = <64>;
                        i-cache-size = <32768>;
                        i-tlb-sets = <1>;
                        i-tlb-size = <32>;
                        mmu-type = "riscv,sv39";
                        reg = <1>;
                        riscv,isa = "rv64imafdc";
                        tlb-split;
                        next-level-cache = <&l2cache>;
                        cpu1_intc: interrupt-controller {
                                #interrupt-cells = <1>;
                                compatible = "riscv,cpu-intc";
                                interrupt-controller;
                        };
                };
                cpu2: cpu@2 {
                        compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
                        d-cache-block-size = <64>;
                        d-cache-sets = <64>;
                        d-cache-size = <32768>;
                        d-tlb-sets = <1>;
                        d-tlb-size = <32>;
                        device_type = "cpu";
                        i-cache-block-size = <64>;
                        i-cache-sets = <64>;
                        i-cache-size = <32768>;
                        i-tlb-sets = <1>;
                        i-tlb-size = <32>;
                        mmu-type = "riscv,sv39";
                        reg = <2>;
                        riscv,isa = "rv64imafdc";
                        tlb-split;
                        next-level-cache = <&l2cache>;
                        cpu2_intc: interrupt-controller {
                                #interrupt-cells = <1>;
                                compatible = "riscv,cpu-intc";
                                interrupt-controller;
                        };
                };
                cpu3: cpu@3 {
                        compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
                        d-cache-block-size = <64>;
                        d-cache-sets = <64>;
                        d-cache-size = <32768>;
                        d-tlb-sets = <1>;
                        d-tlb-size = <32>;
                        device_type = "cpu";
                        i-cache-block-size = <64>;
                        i-cache-sets = <64>;
                        i-cache-size = <32768>;
                        i-tlb-sets = <1>;
                        i-tlb-size = <32>;
                        mmu-type = "riscv,sv39";
                        reg = <3>;
                        riscv,isa = "rv64imafdc";
                        tlb-split;
                        next-level-cache = <&l2cache>;
                        cpu3_intc: interrupt-controller {
                                #interrupt-cells = <1>;
                                compatible = "riscv,cpu-intc";
                                interrupt-controller;
                        };
                };
        };
        soc {
                #address-cells = <2>;
                #size-cells = <2>;
                compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
                ranges;
                plic0: interrupt-controller@c000000 {
                        #interrupt-cells = <1>;
                        compatible = "sifive,plic-1.0.0";
                        reg = <0x0 0xc000000 0x0 0x4000000>;
                        riscv,ndev = <53>;
                        interrupt-controller;
                        interrupts-extended = <
                                &cpu0_intc 0xffffffff &cpu0_intc 9
                                &cpu1_intc 0xffffffff &cpu1_intc 9
                                &cpu2_intc 0xffffffff &cpu2_intc 9
                                &cpu3_intc 0xffffffff &cpu3_intc 9>;
                };
                prci: clock-controller@10000000 {
                        compatible = "sifive,fu540-c000-prci";
                        reg = <0x0 0x10000000 0x0 0x1000>;
                        clocks = <&hfclk>, <&rtcclk>;
                        #clock-cells = <1>;
                };
                uart0: serial@54000000 {
                        compatible = "sifive,fu540-c000-uart", "sifive,uart0";
                        reg = <0x0 0x54000000 0x0 0x1000>;
                        interrupt-parent = <&plic0>;
                        interrupts = <4>;
                        clocks = <&prci PRCI_CLK_TLCLK>;
                        status = "disabled";
                };
                dma: dma@3000000 {
                        compatible = "sifive,fu540-c000-pdma";
                        reg = <0x0 0x3000000 0x0 0x8000>;
                        interrupt-parent = <&plic0>;
                        interrupts = <23 24 25 26 27 28 29 30>;
                        #dma-cells = <1>;
                };
                i2c0: i2c@10030000 {
                        compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
                        reg = <0x0 0x10030000 0x0 0x1000>;
                        interrupt-parent = <&plic0>;
                        interrupts = <50>;
                        clocks = <&prci PRCI_CLK_TLCLK>;
                        reg-shift = <2>;
                        reg-io-width = <1>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        status = "disabled";
                };
                qspi0: spi@10040000 {
                        compatible = "sifive,fu540-c000-spi", "sifive,spi0";
                        reg = <0x0 0x10040000 0x0 0x1000
                               0x0 0x20000000 0x0 0x10000000>;
                        interrupt-parent = <&plic0>;
                        interrupts = <51>;
                        clocks = <&prci PRCI_CLK_TLCLK>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        status = "disabled";
                };
                qspi1: spi@10041000 {
                        compatible = "sifive,fu540-c000-spi", "sifive,spi0";
                        reg = <0x0 0x10041000 0x0 0x1000
                               0x0 0x30000000 0x0 0x10000000>;
                        interrupt-parent = <&plic0>;
                        interrupts = <52>;
                        clocks = <&prci PRCI_CLK_TLCLK>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        status = "disabled";
                };
                qspi2: spi@10050000 {
                        compatible = "sifive,fu540-c000-spi", "sifive,spi0";
                        reg = <0x0 0x10050000 0x0 0x1000>;
                        interrupt-parent = <&plic0>;
                        interrupts = <6>;
                        clocks = <&prci PRCI_CLK_TLCLK>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        status = "disabled";
                };
                eth0: ethernet@10090000 {
                        compatible = "sifive,fu540-c000-gem";
                        interrupt-parent = <&plic0>;
                        interrupts = <53>;
                        reg = <0x0 0x10090000 0x0 0x2000
                               0x0 0x100a0000 0x0 0x1000>;
                        local-mac-address = [00 00 00 00 00 00];
                        clock-names = "pclk", "hclk";
                        clocks = <&prci PRCI_CLK_GEMGXLPLL>,
                                 <&prci PRCI_CLK_GEMGXLPLL>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        status = "disabled";
                };
                pwm0: pwm@10020000 {
                        compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
                        reg = <0x0 0x10020000 0x0 0x1000>;
                        interrupt-parent = <&plic0>;
                        interrupts = <42 43 44 45>;
                        clocks = <&prci PRCI_CLK_TLCLK>;
                        #pwm-cells = <3>;
                        status = "disabled";
                };
                pwm1: pwm@10021000 {
                        compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
                        reg = <0x0 0x10021000 0x0 0x1000>;
                        interrupt-parent = <&plic0>;
                        interrupts = <46 47 48 49>;
                        clocks = <&prci PRCI_CLK_TLCLK>;
                        #pwm-cells = <3>;
                        status = "disabled";
                };
                l2cache: cache-controller@2010000 {
                        compatible = "sifive,fu540-c000-ccache", "cache";
                        cache-block-size = <64>;
                        cache-level = <2>;
                        cache-sets = <1024>;
                        cache-size = <2097152>;
                        cache-unified;
                        interrupt-parent = <&plic0>;
                        interrupts = <1 2 3>;
                        reg = <0x0 0x2010000 0x0 0x1000>;
                };
                gpio: gpio@10060000 {
                        compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
                        interrupt-parent = <&plic0>;
                        interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>,
                                     <14>, <15>, <16>, <17>, <18>, <19>, <20>,
                                     <21>, <22>;
                        reg = <0x0 0x10060000 0x0 0x1000>;
                        gpio-controller;
                        #gpio-cells = <2>;
                        interrupt-controller;
                        #interrupt-cells = <2>;
                        clocks = <&prci PRCI_CLK_TLCLK>;
                        status = "disabled";
                };
        clint: clint@2000000 {
            compatible = "riscv,clint0";
            interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
                                   &cpu1_intc 3 &cpu1_intc 7
                                   &cpu2_intc 3 &cpu2_intc 7
                                   &cpu3_intc 3 &cpu3_intc 7>;
            reg = <0x0 0x2000000 0x0 0xc0000>;
        };
        };
};
