/** @file
  Processor Properties Topology Table (PPTT) for RD-V1 single-chip platform

  This file describes the topological structure of the processor block on the
  RD-V1 single-chip platform in the form as defined by ACPI PPTT table. The
  RD-V1 single-chip platform includes sixteen single-thread CPUS. Each of the
  CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache.
  The platform also includes a system level cache of 16MB.

  Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.

  SPDX-License-Identifier: BSD-2-Clause-Patent

  @par Specification Reference:
    - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology Table
**/

#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
#include "SgiAcpiHeader.h"
#include "SgiPlatform.h"

/** Define helper macro for populating processor core information.

  @param [in] PackageId Package instance number.
  @param [in] ClusterId Cluster instance number.
  @param [in] CpuId     CPU instance number.
**/
#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId)                            \
  {                                                                            \
    /* Parameters for CPU Core */                                              \
    EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT (                               \
      OFFSET_OF (RD_PPTT_CORE, DCache),     /* Length */                       \
      PPTT_PROCESSOR_CORE_FLAGS,            /* Flag */                         \
      OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,             \
        Package.Cluster[ClusterId]),        /* Parent */                       \
      ((PackageId << 4) | ClusterId),       /* ACPI Id */                      \
      2                                     /* Num of private resource */      \
    ),                                                                         \
                                                                               \
    /* Offsets of the private resources */                                     \
    {                                                                          \
      OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,             \
          Package.Cluster[ClusterId].Core[CpuId].DCache),                      \
      OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,             \
          Package.Cluster[ClusterId].Core[CpuId].ICache)                       \
    },                                                                         \
                                                                               \
    /* L1 data cache parameters */                                             \
    EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT (                                   \
      PPTT_CACHE_STRUCTURE_FLAGS,           /* Flag */                         \
      OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,             \
        Package.Cluster[ClusterId].Core[CpuId].L2Cache),                       \
                                            /* Next level of cache */          \
      SIZE_64KB,                            /* Size */                         \
      256,                                  /* Num of sets */                  \
      4,                                    /* Associativity */                \
      PPTT_DATA_CACHE_ATTR,                 /* Attributes */                   \
      64,                                   /* Line size */                    \
      RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1DataCache)               \
                                            /* Cache id */                     \
    ),                                                                         \
                                                                               \
    /* L1 instruction cache parameters */                                      \
    EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT (                                   \
      PPTT_CACHE_STRUCTURE_FLAGS,           /* Flag */                         \
      OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,             \
        Package.Cluster[ClusterId].Core[CpuId].L2Cache),                       \
                                            /* Next level of cache */          \
      SIZE_64KB,                            /* Size */                         \
      256,                                  /* Num of sets */                  \
      4,                                    /* Associativity */                \
      PPTT_INST_CACHE_ATTR,                 /* Attributes */                   \
      64,                                   /* Line size */                    \
      RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1InstructionCache)        \
                                            /* Cache id */                     \
    ),                                                                         \
                                                                               \
    /* L2 cache parameters */                                                  \
    EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT (                                   \
      PPTT_CACHE_STRUCTURE_FLAGS,           /* Flag */                         \
      0,                                    /* Next level of cache */          \
      SIZE_1MB,                             /* Size */                         \
      2048,                                 /* Num of sets */                  \
      8,                                    /* Associativity */                \
      PPTT_UNIFIED_CACHE_ATTR,              /* Attributes */                   \
      64,                                   /* Line size */                    \
      RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L2Cache)                   \
                                            /* Cache id */                     \
    ),                                                                         \
  }

/** Define helper macro for populating processor container information.

  @param [in]  PackageId Package instance number.
  @param [in]  ClusterId Cluster instance number.
**/
#define PPTT_CLUSTER_INIT(PackageId, ClusterId)                                \
  {                                                                            \
    /* Parameters for Cluster */                                               \
    EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT (                               \
      OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core),  /* Length */                 \
      PPTT_PROCESSOR_CLUSTER_FLAGS,         /* Flag */                         \
      OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,             \
        Package),                           /* Parent */                       \
      ((PackageId << 4) | ClusterId),       /* ACPI Id */                      \
      0                                     /* Num of private resource */      \
    ),                                                                         \
                                                                               \
    /* Initialize child core */                                                \
    {                                                                          \
      PPTT_CORE_INIT (PackageId, ClusterId, 0)                                 \
    }                                                                          \
  }

#pragma pack(1)
/*
 * Processor Properties Topology Table
 */
typedef struct {
  EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER  Header;
  RD_PPTT_PACKAGE                                          Package;
} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
#pragma pack ()

STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
  {
    ARM_ACPI_HEADER (
      EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
      EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
      EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
    )
  },

  {
    EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT (
      OFFSET_OF (RD_PPTT_PACKAGE, Cluster[0]),
      PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0),

    {
      PPTT_CLUSTER_INIT (0, 0),
      PPTT_CLUSTER_INIT (0, 1),
      PPTT_CLUSTER_INIT (0, 2),
      PPTT_CLUSTER_INIT (0, 3),
      PPTT_CLUSTER_INIT (0, 4),
      PPTT_CLUSTER_INIT (0, 5),
      PPTT_CLUSTER_INIT (0, 6),
      PPTT_CLUSTER_INIT (0, 7),
      PPTT_CLUSTER_INIT (0, 8),
      PPTT_CLUSTER_INIT (0, 9),
      PPTT_CLUSTER_INIT (0, 10),
      PPTT_CLUSTER_INIT (0, 11),
      PPTT_CLUSTER_INIT (0, 12),
      PPTT_CLUSTER_INIT (0, 13),
      PPTT_CLUSTER_INIT (0, 14),
      PPTT_CLUSTER_INIT (0, 15)
    }
  }
};

/*
 * Reference the table being generated to prevent the optimizer from removing
 * the data structure from the executable
 */
VOID* CONST ReferenceAcpiTable = &Pptt;
