/** @file
*
*  String definitions for the PCIe Config form.
*
*  Copyright (c) 2017 - 2018, Hisilicon Limited. All rights reserved.
*  Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved.
*
*  SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/

/=#

#langdef   en-US "English"

#string STR_BLANK_STRING                #language en-US ""
#string STR_PCIE_CPU_PROMPT_HELP        #language en-US "Press <Enter> to config this CPU."
#string STR_PCIE_CPU_0_NULL_PROMPT      #language en-US ""
#string STR_PCIE_CPU_0_PROMPT           #language en-US "CPU 0 PCIE Configuration"
#string STR_PCIE_CPU_1_PROMPT           #language en-US "CPU 1 PCIE Configuration"
#string STR_SRIOV_SUPPORT_PROMPT        #language en-US "SRIOV"
#string STR_SRIOV_SUPPORT_HELP          #language en-US "This option enables / disables the SRIOV function"

#string STR_PCIE_PORT_PROMPT_HELP       #language en-US "Press <Enter> to config this port."
#string STR_PCIE_PORT_0_NULL_PROMPT     #language en-US ""
#string STR_PCIE_PORT_0_PROMPT          #language en-US "CPU 0 Pcie - Port 0"
#string STR_PCIE_PORT_1_PROMPT          #language en-US "CPU 0 Pcie - Port 1"
#string STR_PCIE_PORT_2_PROMPT          #language en-US "CPU 0 Pcie - Port 2"
#string STR_PCIE_PORT_3_PROMPT          #language en-US "CPU 0 Pcie - Port 3"
#string STR_PCIE_PORT_4_PROMPT          #language en-US "CPU 0 Pcie - Port 4"
#string STR_PCIE_PORT_5_PROMPT          #language en-US "CPU 0 Pcie - Port 5"
#string STR_PCIE_PORT_6_PROMPT          #language en-US "CPU 0 Pcie - Port 6"
#string STR_PCIE_PORT_7_PROMPT          #language en-US "CPU 0 Pcie - Port 7"
#string STR_PCIE_PORT_8_PROMPT          #language en-US "CPU 1 Pcie - Port 0"
#string STR_PCIE_PORT_9_PROMPT          #language en-US "CPU 1 Pcie - Port 1"
#string STR_PCIE_PORT_10_PROMPT         #language en-US "CPU 1 Pcie - Port 2"
#string STR_PCIE_PORT_11_PROMPT         #language en-US "CPU 1 Pcie - Port 3"
#string STR_PCIE_PORT_12_PROMPT         #language en-US "CPU 1 Pcie - Port 4"
#string STR_PCIE_PORT_13_PROMPT         #language en-US "CPU 1 Pcie - Port 5"
#string STR_PCIE_PORT_14_PROMPT         #language en-US "CPU 1 Pcie - Port 6"
#string STR_PCIE_PORT_15_PROMPT         #language en-US "CPU 1 Pcie - Port 7"

#string STR_PCIE_PORT_ENABLE_PROMPT_0   #language en-US "PCI-E Port"
#string STR_PCIE_PORT_ENABLE_HELP       #language en-US "Disable is used to disable the port and hide its CFG space."

#string STR_LINK_STATUS                 #language en-US "PCI-E Port Link Status"
#string STR_LINK_STATUS_NG              #language en-US "Link Training Error"
#string STR_LINK_STATUS_OK              #language en-US "Link Up"
#string STR_MAXLINK_STATUS              #language en-US "PCI-E Port Link Max"
#string STR_WIDTH1_STRING               #language en-US "X1"
#string STR_WIDTH2_STRING               #language en-US "X2"
#string STR_WIDTH4_STRING               #language en-US "X4"
#string STR_WIDTH8_STRING               #language en-US "X8"
#string STR_WIDTH16_STRING              #language en-US "X16"
#string STR_WIDTH32_STRING              #language en-US "X32"

#string STR_PCIESPEED_STATUS            #language en-US "PCI-E Port Link Speed"
#string STR_PCIE_LINK_SPEED1_STRING     #language en-US "Gen 1 (2.5 GT/s)"
#string STR_PCIE_LINK_SPEED2_STRING     #language en-US "Gen 2 (5 GT/s)"
#string STR_PCIE_LINK_SPEED3_STRING     #language en-US "Gen 3 (8 GT/s)"

#string STR_PCIE_PORT_DEEMPHASIS_PROMPT_0  #language en-US "PCI-E Port DeEmphasis"

#string STR_PCIE_PORT_DEEMPHASIS_HELP   #language en-US "De-Emphais control for this PCIe port."

#string STR_35DB                        #language en-US "-3.5 dB"
#string STR_60DB                        #language en-US "-6.0 dB"

#string STR_PCIE_PORT_ASPM_PROMPT_G     #language en-US "PCI-E ASPM Support"

#string STR_PCIE_GLOBAL_ASPM_HELP       #language en-US "This option enables / disables the ASPM support for all downstream devices."
#string STR_PCIE_PORT_ASPM_HELP         #language en-US "This option enables / disables the ASPM (L1) support for the downstream devices."

#string STR_L0S_ONLY                    #language en-US "L0s Only"
#string STR_L0S_L1_BOTH                 #language en-US "L0s & L1 Both"
#string STR_L1_ONLY                     #language en-US "L1 Only"

#string STR_PCIE_PORT_MAX_PAYLOAD_REQUEST_PROMPT    #language en-US "Max Payload Size"
#string STR_PCIE_PORT_MAX_PAYLOAD_REQUEST_HELP      #language en-US "Set Maxpayload size to 512B if possible"
//
// Common Strings
//
#string STR_AUTO                        #language en-US "Auto"
#string STR_X1                          #language en-US "x1"
#string STR_X2                          #language en-US "x2"
#string STR_X4                          #language en-US "x4"
#string STR_X8                          #language en-US "x8"
#string STR_X16                         #language en-US "x16"

#string STR_128B                        #language en-US "128B"
#string STR_256B                        #language en-US "256B"
#string STR_512B                        #language en-US "512B"
#string STR_1024B                       #language en-US "1024B"
#string STR_2048B                       #language en-US "2048B"
#string STR_4096B                       #language en-US "4096B"

#string STR_CLEAR                       #language en-US "Clear"
#string STR_SET                         #language en-US "Set"

#string STR_PCIE_PORT_LINK_SPEED_PROMPT_0       #language en-US "Link Speed"
#string STR_PCIE_PORT_LINK_SPEED_HELP           #language en-US "Link Speed:Gen1(2.5 GT/s)/Gen2(5 GT/s)/Gen3(8 GT/s)/GEN 4 (16 gt/s)"
#string STR_PCIE_GEN1                           #language en-US "Gen 1 (2.5 GT/s)"
#string STR_PCIE_GEN2                           #language en-US "Gen 2 (5 GT/s)"
#string STR_PCIE_GEN3                           #language en-US "Gen 3 (8 GT/s)"
#string STR_PCIE_GEN4                           #language en-US "Gen 4 (16 GT/s)"
