/**

  Copyright (C) 2018, Marvell International Ltd. and its affiliates.

  SPDX-License-Identifier: BSD-2-Clause-Patent

  Glossary - abbreviations used in Marvell SampleAtReset library implementation:
  ICU - Interrupt Consolidation Unit
  AP - Application Processor hardware block (Armada 7k8k incorporates AP806)
  CP - South Bridge hardware blocks (Armada 7k8k incorporates CP110)

**/

#define CP_GIC_SPI_CP0_PCI0            64
#define CP_GIC_SPI_CP0_PCI1            65
#define CP_GIC_SPI_CP0_PCI2            66
#define CP_GIC_SPI_CP0_SDMMC           67
#define CP_GIC_SPI_PP2_CP0_PORT0       69, 72, 75, 78, 81, 127
#define CP_GIC_SPI_PP2_CP0_PORT1       70, 73, 76, 79, 82, 126
#define CP_GIC_SPI_PP2_CP0_PORT2       71, 74, 77, 80, 83, 125
#define CP_GIC_SPI_CP0_EIP_RNG0        105
#define CP_GIC_SPI_CP0_USB_H1          112
#define CP_GIC_SPI_CP0_USB_H0          113
#define CP_GIC_SPI_CP0_SATA_H0         114

#define CP_GIC_SPI_CP1_PCI0            288
#define CP_GIC_SPI_CP1_PCI1            289
#define CP_GIC_SPI_CP1_PCI2            290
#define CP_GIC_SPI_CP1_SDMMC           291
#define CP_GIC_SPI_PP2_CP1_PORT0       293, 296, 299, 302, 305, 351
#define CP_GIC_SPI_PP2_CP1_PORT1       294, 297, 300, 303, 306, 350
#define CP_GIC_SPI_PP2_CP1_PORT2       295, 298, 301, 304, 307, 349
#define CP_GIC_SPI_CP1_EIP_RNG0        329
#define CP_GIC_SPI_CP1_USB_H1          336
#define CP_GIC_SPI_CP1_USB_H0          337
#define CP_GIC_SPI_CP1_SATA_H0         338
