// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2017 Marvell Technology Group Ltd.
 *
 * Device Tree file for the Armada 70x0 SoC
 */

/ {
        aliases {
                gpio1 = &cp0_gpio1;
                gpio2 = &cp0_gpio2;
                spi1 = &cp0_spi0;
                spi2 = &cp0_spi1;
        };
};

/*
 * Instantiate the CP110
 */
#define CP110_NAME                cp0
#define CP110_BASE                f2000000
#define CP110_PCIE_IO_BASE        0xf9000000
#define CP110_PCIE_MEM_BASE        0xf6000000
#define CP110_PCIE0_BASE        f2600000
#define CP110_PCIE1_BASE        f2620000
#define CP110_PCIE2_BASE        f2640000

#include "armada-cp110.dtsi"

#undef CP110_NAME
#undef CP110_BASE
#undef CP110_PCIE_IO_BASE
#undef CP110_PCIE_MEM_BASE
#undef CP110_PCIE0_BASE
#undef CP110_PCIE1_BASE
#undef CP110_PCIE2_BASE

&cp0_gpio1 {
        status = "okay";
};

&cp0_gpio2 {
        status = "okay";
};

&cp0_syscon0 {
        cp0_pinctrl: pinctrl {
                compatible = "marvell,armada-7k-pinctrl";

                nand_pins: nand-pins {
                        marvell,pins =
                        "mpp15", "mpp16", "mpp17", "mpp18",
                        "mpp19", "mpp20", "mpp21", "mpp22",
                        "mpp23", "mpp24", "mpp25", "mpp26",
                        "mpp27";
                        marvell,function = "dev";
                };

                nand_rb: nand-rb {
                        marvell,pins = "mpp13";
                        marvell,function = "nf";
                };
        };
};
