cpu_unittest.cc 6.7 KB

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  1. // Copyright (c) 2012 The Chromium Authors. All rights reserved.
  2. // Use of this source code is governed by a BSD-style license that can be
  3. // found in the LICENSE file.
  4. #include "base/cpu.h"
  5. #include "base/containers/contains.h"
  6. #include "base/logging.h"
  7. #include "base/strings/string_util.h"
  8. #include "build/build_config.h"
  9. #include "testing/gtest/include/gtest/gtest.h"
  10. // Tests whether we can run extended instructions represented by the CPU
  11. // information. This test actually executes some extended instructions (such as
  12. // MMX, SSE, etc.) supported by the CPU and sees we can run them without
  13. // "undefined instruction" exceptions. That is, this test succeeds when this
  14. // test finishes without a crash.
  15. TEST(CPU, RunExtendedInstructions) {
  16. // Retrieve the CPU information.
  17. base::CPU cpu;
  18. #if defined(ARCH_CPU_X86_FAMILY)
  19. ASSERT_TRUE(cpu.has_mmx());
  20. ASSERT_TRUE(cpu.has_sse());
  21. ASSERT_TRUE(cpu.has_sse2());
  22. ASSERT_TRUE(cpu.has_sse3());
  23. // GCC and clang instruction test.
  24. #if defined(COMPILER_GCC)
  25. // Execute an MMX instruction.
  26. __asm__ __volatile__("emms\n" : : : "mm0");
  27. // Execute an SSE instruction.
  28. __asm__ __volatile__("xorps %%xmm0, %%xmm0\n" : : : "xmm0");
  29. // Execute an SSE 2 instruction.
  30. __asm__ __volatile__("psrldq $0, %%xmm0\n" : : : "xmm0");
  31. // Execute an SSE 3 instruction.
  32. __asm__ __volatile__("addsubpd %%xmm0, %%xmm0\n" : : : "xmm0");
  33. if (cpu.has_ssse3()) {
  34. // Execute a Supplimental SSE 3 instruction.
  35. __asm__ __volatile__("psignb %%xmm0, %%xmm0\n" : : : "xmm0");
  36. }
  37. if (cpu.has_sse41()) {
  38. // Execute an SSE 4.1 instruction.
  39. __asm__ __volatile__("pmuldq %%xmm0, %%xmm0\n" : : : "xmm0");
  40. }
  41. if (cpu.has_sse42()) {
  42. // Execute an SSE 4.2 instruction.
  43. __asm__ __volatile__("crc32 %%eax, %%eax\n" : : : "eax");
  44. }
  45. if (cpu.has_popcnt()) {
  46. // Execute a POPCNT instruction.
  47. __asm__ __volatile__("popcnt %%eax, %%eax\n" : : : "eax");
  48. }
  49. if (cpu.has_avx()) {
  50. // Execute an AVX instruction.
  51. __asm__ __volatile__("vzeroupper\n" : : : "xmm0");
  52. }
  53. if (cpu.has_fma3()) {
  54. // Execute a FMA3 instruction.
  55. __asm__ __volatile__("vfmadd132ps %%xmm0, %%xmm0, %%xmm0\n" : : : "xmm0");
  56. }
  57. if (cpu.has_avx2()) {
  58. // Execute an AVX 2 instruction.
  59. __asm__ __volatile__("vpunpcklbw %%ymm0, %%ymm0, %%ymm0\n" : : : "xmm0");
  60. }
  61. // Visual C 32 bit and ClangCL 32/64 bit test.
  62. #elif defined(COMPILER_MSVC) && (defined(ARCH_CPU_32_BITS) || \
  63. (defined(ARCH_CPU_64_BITS) && defined(__clang__)))
  64. // Execute an MMX instruction.
  65. __asm emms;
  66. // Execute an SSE instruction.
  67. __asm xorps xmm0, xmm0;
  68. // Execute an SSE 2 instruction.
  69. __asm psrldq xmm0, 0;
  70. // Execute an SSE 3 instruction.
  71. __asm addsubpd xmm0, xmm0;
  72. if (cpu.has_ssse3()) {
  73. // Execute a Supplimental SSE 3 instruction.
  74. __asm psignb xmm0, xmm0;
  75. }
  76. if (cpu.has_sse41()) {
  77. // Execute an SSE 4.1 instruction.
  78. __asm pmuldq xmm0, xmm0;
  79. }
  80. if (cpu.has_sse42()) {
  81. // Execute an SSE 4.2 instruction.
  82. __asm crc32 eax, eax;
  83. }
  84. if (cpu.has_popcnt()) {
  85. // Execute a POPCNT instruction.
  86. __asm popcnt eax, eax;
  87. }
  88. if (cpu.has_avx()) {
  89. // Execute an AVX instruction.
  90. __asm vzeroupper;
  91. }
  92. if (cpu.has_fma3()) {
  93. // Execute an AVX instruction.
  94. __asm vfmadd132ps xmm0, xmm0, xmm0;
  95. }
  96. if (cpu.has_avx2()) {
  97. // Execute an AVX 2 instruction.
  98. __asm vpunpcklbw ymm0, ymm0, ymm0
  99. }
  100. #endif // defined(COMPILER_GCC)
  101. #endif // defined(ARCH_CPU_X86_FAMILY)
  102. #if defined(ARCH_CPU_ARM64)
  103. // Check that the CPU is correctly reporting support for the Armv8.5-A memory
  104. // tagging extension. The new MTE instructions aren't encoded in NOP space
  105. // like BTI/Pointer Authentication and will crash older cores with a SIGILL if
  106. // used incorrectly. This test demonstrates how it should be done and that
  107. // this approach works.
  108. if (cpu.has_mte()) {
  109. #if !defined(__ARM_FEATURE_MEMORY_TAGGING)
  110. // In this section, we're running on an MTE-compatible core, but we're
  111. // building this file without MTE support. Fail this test to indicate that
  112. // there's a problem with the base/ build configuration.
  113. GTEST_FAIL()
  114. << "MTE support detected (but base/ built without MTE support)";
  115. #else
  116. char ptr[32];
  117. uint64_t val;
  118. // Execute a trivial MTE instruction. Normally, MTE should be used via the
  119. // intrinsics documented at
  120. // https://developer.arm.com/documentation/101028/0012/10--Memory-tagging-intrinsics,
  121. // this test uses the irg (Insert Random Tag) instruction directly to make
  122. // sure that it's not optimized out by the compiler.
  123. __asm__ __volatile__("irg %0, %1" : "=r"(val) : "r"(ptr));
  124. #endif // __ARM_FEATURE_MEMORY_TAGGING
  125. }
  126. #endif // ARCH_CPU_ARM64
  127. }
  128. // For https://crbug.com/249713
  129. TEST(CPU, BrandAndVendorContainsNoNUL) {
  130. base::CPU cpu;
  131. EXPECT_FALSE(base::Contains(cpu.cpu_brand(), '\0'));
  132. EXPECT_FALSE(base::Contains(cpu.vendor_name(), '\0'));
  133. }
  134. #if defined(ARCH_CPU_X86_FAMILY)
  135. // Tests that we compute the correct CPU family and model based on the vendor
  136. // and CPUID signature.
  137. TEST(CPU, X86FamilyAndModel) {
  138. base::internal::X86ModelInfo info;
  139. // Check with an Intel Skylake signature.
  140. info = base::internal::ComputeX86FamilyAndModel("GenuineIntel", 0x000406e3);
  141. EXPECT_EQ(info.family, 6);
  142. EXPECT_EQ(info.model, 78);
  143. EXPECT_EQ(info.ext_family, 0);
  144. EXPECT_EQ(info.ext_model, 4);
  145. // Check with an Intel Airmont signature.
  146. info = base::internal::ComputeX86FamilyAndModel("GenuineIntel", 0x000406c2);
  147. EXPECT_EQ(info.family, 6);
  148. EXPECT_EQ(info.model, 76);
  149. EXPECT_EQ(info.ext_family, 0);
  150. EXPECT_EQ(info.ext_model, 4);
  151. // Check with an Intel Prescott signature.
  152. info = base::internal::ComputeX86FamilyAndModel("GenuineIntel", 0x00000f31);
  153. EXPECT_EQ(info.family, 15);
  154. EXPECT_EQ(info.model, 3);
  155. EXPECT_EQ(info.ext_family, 0);
  156. EXPECT_EQ(info.ext_model, 0);
  157. // Check with an AMD Excavator signature.
  158. info = base::internal::ComputeX86FamilyAndModel("AuthenticAMD", 0x00670f00);
  159. EXPECT_EQ(info.family, 21);
  160. EXPECT_EQ(info.model, 112);
  161. EXPECT_EQ(info.ext_family, 6);
  162. EXPECT_EQ(info.ext_model, 7);
  163. }
  164. #endif // defined(ARCH_CPU_X86_FAMILY)
  165. #if defined(ARCH_CPU_ARM_FAMILY) && \
  166. (BUILDFLAG(IS_LINUX) || BUILDFLAG(IS_ANDROID) || BUILDFLAG(IS_CHROMEOS))
  167. TEST(CPU, ARMImplementerAndPartNumber) {
  168. base::CPU cpu;
  169. const std::string& cpu_brand = cpu.cpu_brand();
  170. // Some devices, including on the CQ, do not report a cpu_brand
  171. // https://crbug.com/1166533 and https://crbug.com/1167123.
  172. EXPECT_EQ(cpu_brand, base::TrimWhitespaceASCII(cpu_brand, base::TRIM_ALL));
  173. EXPECT_GT(cpu.implementer(), 0u);
  174. EXPECT_GT(cpu.part_number(), 0u);
  175. }
  176. #endif // defined(ARCH_CPU_ARM_FAMILY) && (BUILDFLAG(IS_LINUX) ||
  177. // BUILDFLAG(IS_ANDROID) || BUILDFLAG(IS_CHROMEOS))