cpu_context.h 13 KB

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  1. // Copyright 2014 The Crashpad Authors. All rights reserved.
  2. //
  3. // Licensed under the Apache License, Version 2.0 (the "License");
  4. // you may not use this file except in compliance with the License.
  5. // You may obtain a copy of the License at
  6. //
  7. // http://www.apache.org/licenses/LICENSE-2.0
  8. //
  9. // Unless required by applicable law or agreed to in writing, software
  10. // distributed under the License is distributed on an "AS IS" BASIS,
  11. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  12. // See the License for the specific language governing permissions and
  13. // limitations under the License.
  14. #ifndef CRASHPAD_SNAPSHOT_SNAPSHOT_CPU_CONTEXT_H_
  15. #define CRASHPAD_SNAPSHOT_SNAPSHOT_CPU_CONTEXT_H_
  16. #include <stdint.h>
  17. #include "snapshot/cpu_architecture.h"
  18. #include "util/numeric/int128.h"
  19. namespace crashpad {
  20. //! \brief A context structure carrying 32-bit x86 CPU state.
  21. struct CPUContextX86 {
  22. using X87Register = uint8_t[10];
  23. struct Fsave {
  24. uint16_t fcw; // FPU control word
  25. uint16_t reserved_1;
  26. uint16_t fsw; // FPU status word
  27. uint16_t reserved_2;
  28. uint16_t ftw; // full FPU tag word
  29. uint16_t reserved_3;
  30. uint32_t fpu_ip; // FPU instruction pointer offset
  31. uint16_t fpu_cs; // FPU instruction pointer segment selector
  32. uint16_t fop; // FPU opcode
  33. uint32_t fpu_dp; // FPU data pointer offset
  34. uint16_t fpu_ds; // FPU data pointer segment selector
  35. uint16_t reserved_4;
  36. X87Register st[8];
  37. };
  38. union X87OrMMXRegister {
  39. struct {
  40. X87Register st;
  41. uint8_t st_reserved[6];
  42. };
  43. struct {
  44. uint8_t mm_value[8];
  45. uint8_t mm_reserved[8];
  46. };
  47. };
  48. using XMMRegister = uint8_t[16];
  49. struct Fxsave {
  50. uint16_t fcw; // FPU control word
  51. uint16_t fsw; // FPU status word
  52. uint8_t ftw; // abridged FPU tag word
  53. uint8_t reserved_1;
  54. uint16_t fop; // FPU opcode
  55. uint32_t fpu_ip; // FPU instruction pointer offset
  56. uint16_t fpu_cs; // FPU instruction pointer segment selector
  57. uint16_t reserved_2;
  58. uint32_t fpu_dp; // FPU data pointer offset
  59. uint16_t fpu_ds; // FPU data pointer segment selector
  60. uint16_t reserved_3;
  61. uint32_t mxcsr; // multimedia extensions status and control register
  62. uint32_t mxcsr_mask; // valid bits in mxcsr
  63. X87OrMMXRegister st_mm[8];
  64. XMMRegister xmm[8];
  65. uint8_t reserved_4[176];
  66. uint8_t available[48];
  67. };
  68. //! \brief Converts an `fxsave` area to an `fsave` area.
  69. //!
  70. //! `fsave` state is restricted to the x87 FPU, while `fxsave` state includes
  71. //! state related to the x87 FPU as well as state specific to SSE.
  72. //!
  73. //! As the `fxsave` format is a superset of the `fsave` format, this operation
  74. //! fully populates the `fsave` area. `fsave` uses the full 16-bit form for
  75. //! the x87 floating-point tag word, so FxsaveToFsaveTagWord() is used to
  76. //! derive Fsave::ftw from the abridged 8-bit form used by `fxsave`. Reserved
  77. //! fields in \a fsave are set to `0`.
  78. //!
  79. //! \param[in] fxsave The `fxsave` area to convert.
  80. //! \param[out] fsave The `fsave` area to populate.
  81. //!
  82. //! \sa FsaveToFxsave()
  83. static void FxsaveToFsave(const Fxsave& fxsave, Fsave* fsave);
  84. //! \brief Converts an `fsave` area to an `fxsave` area.
  85. //!
  86. //! `fsave` state is restricted to the x87 FPU, while `fxsave` state includes
  87. //! state related to the x87 FPU as well as state specific to SSE.
  88. //!
  89. //! As the `fsave` format is a subset of the `fxsave` format, this operation
  90. //! cannot fully populate the `fxsave` area. Fields in \a fxsave that have no
  91. //! equivalent in \a fsave are set to `0`, including Fxsave::mxcsr,
  92. //! Fxsave::mxcsr_mask, Fxsave::xmm, and Fxsave::available.
  93. //! FsaveToFxsaveTagWord() is used to derive Fxsave::ftw from the full 16-bit
  94. //! form used by `fsave`. Reserved fields in \a fxsave are set to `0`.
  95. //!
  96. //! \param[in] fsave The `fsave` area to convert.
  97. //! \param[out] fxsave The `fxsave` area to populate.
  98. //!
  99. //! \sa FxsaveToFsave()
  100. static void FsaveToFxsave(const Fsave& fsave, Fxsave* fxsave);
  101. //! \brief Converts x87 floating-point tag words from `fxsave` (abridged,
  102. //! 8-bit) to `fsave` (full, 16-bit) form.
  103. //!
  104. //! `fxsave` stores the x87 floating-point tag word in abridged 8-bit form,
  105. //! and `fsave` stores it in full 16-bit form. Some users, notably
  106. //! CPUContextX86::Fsave::ftw, require the full 16-bit form, where most other
  107. //! contemporary code uses `fxsave` and thus the abridged 8-bit form found in
  108. //! CPUContextX86::Fxsave::ftw.
  109. //!
  110. //! This function converts an abridged tag word to the full version by using
  111. //! the abridged tag word and the contents of the registers it describes. See
  112. //! Intel Software Developer’s Manual, Volume 2A: Instruction Set Reference
  113. //! A-M (253666-052), 3.2 “FXSAVE”, specifically, the notes on the abridged
  114. //! FTW and recreating the FSAVE format, and AMD Architecture Programmer’s
  115. //! Manual, Volume 2: System Programming (24593-3.24), “FXSAVE Format for x87
  116. //! Tag Word”.
  117. //!
  118. //! \sa FsaveToFxsaveTagWord()
  119. //!
  120. //! \param[in] fsw The FPU status word, used to map logical \a st_mm registers
  121. //! to their physical counterparts. This can be taken from
  122. //! CPUContextX86::Fxsave::fsw.
  123. //! \param[in] fxsave_tag The abridged FPU tag word. This can be taken from
  124. //! CPUContextX86::Fxsave::ftw.
  125. //! \param[in] st_mm The floating-point registers in logical order. This can
  126. //! be taken from CPUContextX86::Fxsave::st_mm.
  127. //!
  128. //! \return The full FPU tag word.
  129. static uint16_t FxsaveToFsaveTagWord(
  130. uint16_t fsw, uint8_t fxsave_tag, const X87OrMMXRegister st_mm[8]);
  131. //! \brief Converts x87 floating-point tag words from `fsave` (full, 16-bit)
  132. //! to `fxsave` (abridged, 8-bit) form.
  133. //!
  134. //! This function performs the inverse operation of FxsaveToFsaveTagWord().
  135. //!
  136. //! \param[in] fsave_tag The full FPU tag word.
  137. //!
  138. //! \return The abridged FPU tag word.
  139. static uint8_t FsaveToFxsaveTagWord(uint16_t fsave_tag);
  140. // Integer registers.
  141. uint32_t eax;
  142. uint32_t ebx;
  143. uint32_t ecx;
  144. uint32_t edx;
  145. uint32_t edi; // destination index
  146. uint32_t esi; // source index
  147. uint32_t ebp; // base pointer
  148. uint32_t esp; // stack pointer
  149. uint32_t eip; // instruction pointer
  150. uint32_t eflags;
  151. uint16_t cs; // code segment selector
  152. uint16_t ds; // data segment selector
  153. uint16_t es; // extra segment selector
  154. uint16_t fs;
  155. uint16_t gs;
  156. uint16_t ss; // stack segment selector
  157. // Floating-point and vector registers.
  158. Fxsave fxsave;
  159. // Debug registers.
  160. uint32_t dr0;
  161. uint32_t dr1;
  162. uint32_t dr2;
  163. uint32_t dr3;
  164. uint32_t dr4; // obsolete, normally an alias for dr6
  165. uint32_t dr5; // obsolete, normally an alias for dr7
  166. uint32_t dr6;
  167. uint32_t dr7;
  168. };
  169. //! \brief A context structure carrying x86_64 CPU state.
  170. struct CPUContextX86_64 {
  171. using X87Register = CPUContextX86::X87Register;
  172. using X87OrMMXRegister = CPUContextX86::X87OrMMXRegister;
  173. using XMMRegister = CPUContextX86::XMMRegister;
  174. struct Fxsave {
  175. uint16_t fcw; // FPU control word
  176. uint16_t fsw; // FPU status word
  177. uint8_t ftw; // abridged FPU tag word
  178. uint8_t reserved_1;
  179. uint16_t fop; // FPU opcode
  180. union {
  181. // The expression of these union members is determined by the use of
  182. // fxsave/fxrstor or fxsave64/fxrstor64 (fxsaveq/fxrstorq). macOS and
  183. // Windows systems use the traditional fxsave/fxrstor structure.
  184. struct {
  185. // fxsave/fxrstor
  186. uint32_t fpu_ip; // FPU instruction pointer offset
  187. uint16_t fpu_cs; // FPU instruction pointer segment selector
  188. uint16_t reserved_2;
  189. uint32_t fpu_dp; // FPU data pointer offset
  190. uint16_t fpu_ds; // FPU data pointer segment selector
  191. uint16_t reserved_3;
  192. };
  193. struct {
  194. // fxsave64/fxrstor64 (fxsaveq/fxrstorq)
  195. uint64_t fpu_ip_64; // FPU instruction pointer
  196. uint64_t fpu_dp_64; // FPU data pointer
  197. };
  198. };
  199. uint32_t mxcsr; // multimedia extensions status and control register
  200. uint32_t mxcsr_mask; // valid bits in mxcsr
  201. X87OrMMXRegister st_mm[8];
  202. XMMRegister xmm[16];
  203. uint8_t reserved_4[48];
  204. uint8_t available[48];
  205. };
  206. // Integer registers.
  207. uint64_t rax;
  208. uint64_t rbx;
  209. uint64_t rcx;
  210. uint64_t rdx;
  211. uint64_t rdi; // destination index
  212. uint64_t rsi; // source index
  213. uint64_t rbp; // base pointer
  214. uint64_t rsp; // stack pointer
  215. uint64_t r8;
  216. uint64_t r9;
  217. uint64_t r10;
  218. uint64_t r11;
  219. uint64_t r12;
  220. uint64_t r13;
  221. uint64_t r14;
  222. uint64_t r15;
  223. uint64_t rip; // instruction pointer
  224. uint64_t rflags;
  225. uint16_t cs; // code segment selector
  226. uint16_t fs;
  227. uint16_t gs;
  228. // Floating-point and vector registers.
  229. Fxsave fxsave;
  230. // Debug registers.
  231. uint64_t dr0;
  232. uint64_t dr1;
  233. uint64_t dr2;
  234. uint64_t dr3;
  235. uint64_t dr4; // obsolete, normally an alias for dr6
  236. uint64_t dr5; // obsolete, normally an alias for dr7
  237. uint64_t dr6;
  238. uint64_t dr7;
  239. struct {
  240. // If 0 then none of the xsave areas are valid.
  241. uint64_t enabled_features;
  242. // CET_U registers if XSTATE_CET_U bit is set in enabled_features.
  243. struct {
  244. uint64_t cetmsr;
  245. uint64_t ssp;
  246. } cet_u;
  247. } xstate;
  248. };
  249. //! \brief A context structure carrying ARM CPU state.
  250. struct CPUContextARM {
  251. uint32_t regs[11];
  252. uint32_t fp; // r11
  253. uint32_t ip; // r12
  254. uint32_t sp; // r13
  255. uint32_t lr; // r14
  256. uint32_t pc; // r15
  257. uint32_t cpsr;
  258. struct {
  259. struct fp_reg {
  260. uint32_t sign1 : 1;
  261. uint32_t unused : 15;
  262. uint32_t sign2 : 1;
  263. uint32_t exponent : 14;
  264. uint32_t j : 1;
  265. uint32_t mantissa1 : 31;
  266. uint32_t mantisss0 : 32;
  267. } fpregs[8];
  268. uint32_t fpsr : 32;
  269. uint32_t fpcr : 32;
  270. uint8_t type[8];
  271. uint32_t init_flag;
  272. } fpa_regs;
  273. struct {
  274. uint64_t vfp[32];
  275. uint32_t fpscr;
  276. } vfp_regs;
  277. bool have_fpa_regs;
  278. bool have_vfp_regs;
  279. };
  280. //! \brief A context structure carrying ARM64 CPU state.
  281. struct CPUContextARM64 {
  282. uint64_t regs[31];
  283. uint64_t sp;
  284. uint64_t pc;
  285. uint32_t spsr;
  286. uint128_struct fpsimd[32];
  287. uint32_t fpsr;
  288. uint32_t fpcr;
  289. };
  290. //! \brief A context structure carrying MIPS CPU state.
  291. struct CPUContextMIPS {
  292. uint64_t regs[32];
  293. uint32_t mdlo;
  294. uint32_t mdhi;
  295. uint32_t cp0_epc;
  296. uint32_t cp0_badvaddr;
  297. uint32_t cp0_status;
  298. uint32_t cp0_cause;
  299. uint32_t hi[3];
  300. uint32_t lo[3];
  301. uint32_t dsp_control;
  302. union {
  303. double dregs[32];
  304. struct {
  305. float _fp_fregs;
  306. uint32_t _fp_pad;
  307. } fregs[32];
  308. } fpregs;
  309. uint32_t fpcsr;
  310. uint32_t fir;
  311. };
  312. //! \brief A context structure carrying MIPS64 CPU state.
  313. struct CPUContextMIPS64 {
  314. uint64_t regs[32];
  315. uint64_t mdlo;
  316. uint64_t mdhi;
  317. uint64_t cp0_epc;
  318. uint64_t cp0_badvaddr;
  319. uint64_t cp0_status;
  320. uint64_t cp0_cause;
  321. uint64_t hi[3];
  322. uint64_t lo[3];
  323. uint64_t dsp_control;
  324. union {
  325. double dregs[32];
  326. struct {
  327. float _fp_fregs;
  328. uint32_t _fp_pad;
  329. } fregs[32];
  330. } fpregs;
  331. uint64_t fpcsr;
  332. uint64_t fir;
  333. };
  334. //! \brief A context structure carrying RISC CPU state.
  335. struct CPUContextRISCV {
  336. uint32_t regs[32];
  337. uint64_t fpregs[32];
  338. uint32_t fcsr;
  339. };
  340. //! \brief A context structure carrying RISC64 CPU state.
  341. struct CPUContextRISCV64 {
  342. uint64_t regs[32];
  343. uint64_t fpregs[32];
  344. uint32_t fcsr;
  345. };
  346. //! \brief A context structure capable of carrying the context of any supported
  347. //! CPU architecture.
  348. struct CPUContext {
  349. //! \brief Returns the instruction pointer value from the context structure.
  350. //!
  351. //! This is a CPU architecture-independent method that is capable of
  352. //! recovering the instruction pointer from any supported CPU architecture’s
  353. //! context structure.
  354. uint64_t InstructionPointer() const;
  355. //! \brief Returns the stack pointer value from the context structure.
  356. //!
  357. //! This is a CPU architecture-independent method that is capable of
  358. //! recovering the stack pointer from any supported CPU architecture’s
  359. //! context structure.
  360. uint64_t StackPointer() const;
  361. //! \brief Returns the shadow stack pointer value from the context structure.
  362. //!
  363. //! This is a CPU architecture-independent method that is capable of
  364. //! recovering the shadow stack pointer from any supported CPU architecture’s
  365. //! context structure.
  366. uint64_t ShadowStackPointer() const;
  367. //! \brief Returns `true` if this context is for a 64-bit architecture.
  368. bool Is64Bit() const;
  369. //! \brief Returns `true` if this context has an active shadow stack pointer.
  370. bool HasShadowStack() const;
  371. //! \brief The CPU architecture of a context structure. This field controls
  372. //! the expression of the union.
  373. CPUArchitecture architecture;
  374. union {
  375. CPUContextX86* x86;
  376. CPUContextX86_64* x86_64;
  377. CPUContextARM* arm;
  378. CPUContextARM64* arm64;
  379. CPUContextMIPS* mipsel;
  380. CPUContextMIPS64* mips64;
  381. CPUContextRISCV* riscv;
  382. CPUContextRISCV64* riscv64;
  383. };
  384. };
  385. } // namespace crashpad
  386. #endif // CRASHPAD_SNAPSHOT_SNAPSHOT_CPU_CONTEXT_H_