Config.in 12 KB

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  1. menu "Target options"
  2. config BR2_ARCH_IS_64
  3. bool
  4. config BR2_KERNEL_64_USERLAND_32
  5. bool
  6. config BR2_SOFT_FLOAT
  7. bool
  8. config BR2_ARCH_HAS_MMU_MANDATORY
  9. bool
  10. config BR2_ARCH_HAS_MMU_OPTIONAL
  11. bool
  12. choice
  13. prompt "Target Architecture"
  14. default BR2_i386
  15. help
  16. Select the target architecture family to build for.
  17. config BR2_arcle
  18. bool "ARC (little endian)"
  19. select BR2_ARCH_HAS_MMU_MANDATORY
  20. help
  21. Synopsys' DesignWare ARC Processor Cores are a family of
  22. 32-bit CPUs that can be used from deeply embedded to high
  23. performance host applications. Little endian.
  24. config BR2_arceb
  25. bool "ARC (big endian)"
  26. select BR2_ARCH_HAS_MMU_MANDATORY
  27. help
  28. Synopsys' DesignWare ARC Processor Cores are a family of
  29. 32-bit CPUs that can be used from deeply embedded to high
  30. performance host applications. Big endian.
  31. config BR2_arm
  32. bool "ARM (little endian)"
  33. # MMU support is set by the subarchitecture file, arch/Config.in.arm
  34. help
  35. ARM is a 32-bit reduced instruction set computer (RISC)
  36. instruction set architecture (ISA) developed by ARM Holdings.
  37. Little endian.
  38. http://www.arm.com/
  39. http://en.wikipedia.org/wiki/ARM
  40. config BR2_armeb
  41. bool "ARM (big endian)"
  42. # MMU support is set by the subarchitecture file, arch/Config.in.arm
  43. help
  44. ARM is a 32-bit reduced instruction set computer (RISC)
  45. instruction set architecture (ISA) developed by ARM Holdings.
  46. Big endian.
  47. http://www.arm.com/
  48. http://en.wikipedia.org/wiki/ARM
  49. config BR2_aarch64
  50. bool "AArch64 (little endian)"
  51. select BR2_ARCH_IS_64
  52. select BR2_ARCH_HAS_MMU_MANDATORY
  53. help
  54. Aarch64 is a 64-bit architecture developed by ARM Holdings.
  55. http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
  56. http://en.wikipedia.org/wiki/ARM
  57. config BR2_aarch64_be
  58. bool "AArch64 (big endian)"
  59. select BR2_ARCH_IS_64
  60. select BR2_ARCH_HAS_MMU_MANDATORY
  61. help
  62. Aarch64 is a 64-bit architecture developed by ARM Holdings.
  63. http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
  64. http://en.wikipedia.org/wiki/ARM
  65. config BR2_csky
  66. bool "csky"
  67. select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
  68. select BR2_ARCH_HAS_MMU_MANDATORY
  69. select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
  70. help
  71. csky is processor IP from china.
  72. http://www.c-sky.com/
  73. http://www.github.com/c-sky
  74. config BR2_i386
  75. bool "i386"
  76. select BR2_ARCH_HAS_MMU_MANDATORY
  77. help
  78. Intel i386 architecture compatible microprocessor
  79. http://en.wikipedia.org/wiki/I386
  80. config BR2_m68k
  81. bool "m68k"
  82. # MMU support is set by the subarchitecture file, arch/Config.in.m68k
  83. help
  84. Motorola 68000 family microprocessor
  85. http://en.wikipedia.org/wiki/M68k
  86. config BR2_microblazeel
  87. bool "Microblaze AXI (little endian)"
  88. select BR2_ARCH_HAS_MMU_MANDATORY
  89. help
  90. Soft processor core designed for Xilinx FPGAs from Xilinx. AXI
  91. bus based architecture (little endian)
  92. http://www.xilinx.com
  93. http://en.wikipedia.org/wiki/Microblaze
  94. config BR2_microblazebe
  95. bool "Microblaze non-AXI (big endian)"
  96. select BR2_ARCH_HAS_MMU_MANDATORY
  97. help
  98. Soft processor core designed for Xilinx FPGAs from Xilinx. PLB
  99. bus based architecture (non-AXI, big endian)
  100. http://www.xilinx.com
  101. http://en.wikipedia.org/wiki/Microblaze
  102. config BR2_mips
  103. bool "MIPS (big endian)"
  104. select BR2_ARCH_HAS_MMU_MANDATORY
  105. help
  106. MIPS is a RISC microprocessor from MIPS Technologies. Big
  107. endian.
  108. http://www.mips.com/
  109. http://en.wikipedia.org/wiki/MIPS_Technologies
  110. config BR2_mipsel
  111. bool "MIPS (little endian)"
  112. select BR2_ARCH_HAS_MMU_MANDATORY
  113. help
  114. MIPS is a RISC microprocessor from MIPS Technologies. Little
  115. endian.
  116. http://www.mips.com/
  117. http://en.wikipedia.org/wiki/MIPS_Technologies
  118. config BR2_mips64
  119. bool "MIPS64 (big endian)"
  120. select BR2_ARCH_IS_64
  121. select BR2_ARCH_HAS_MMU_MANDATORY
  122. help
  123. MIPS is a RISC microprocessor from MIPS Technologies. Big
  124. endian.
  125. http://www.mips.com/
  126. http://en.wikipedia.org/wiki/MIPS_Technologies
  127. config BR2_mips64el
  128. bool "MIPS64 (little endian)"
  129. select BR2_ARCH_IS_64
  130. select BR2_ARCH_HAS_MMU_MANDATORY
  131. help
  132. MIPS is a RISC microprocessor from MIPS Technologies. Little
  133. endian.
  134. http://www.mips.com/
  135. http://en.wikipedia.org/wiki/MIPS_Technologies
  136. config BR2_nds32
  137. bool "nds32"
  138. select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
  139. select BR2_ARCH_HAS_MMU_MANDATORY
  140. help
  141. nds32 is a 32-bit architecture developed by Andes Technology.
  142. https://en.wikipedia.org/wiki/Andes_Technology
  143. config BR2_nios2
  144. bool "Nios II"
  145. select BR2_ARCH_HAS_MMU_MANDATORY
  146. help
  147. Nios II is a soft core processor from Altera Corporation.
  148. http://www.altera.com/
  149. http://en.wikipedia.org/wiki/Nios_II
  150. config BR2_or1k
  151. bool "OpenRISC"
  152. select BR2_ARCH_HAS_MMU_MANDATORY
  153. help
  154. OpenRISC is a free and open processor for embedded system.
  155. http://openrisc.io
  156. config BR2_powerpc
  157. bool "PowerPC"
  158. select BR2_ARCH_HAS_MMU_MANDATORY
  159. help
  160. PowerPC is a RISC architecture created by Apple-IBM-Motorola
  161. alliance. Big endian.
  162. http://www.power.org/
  163. http://en.wikipedia.org/wiki/Powerpc
  164. config BR2_powerpc64
  165. bool "PowerPC64 (big endian)"
  166. select BR2_ARCH_IS_64
  167. select BR2_ARCH_HAS_MMU_MANDATORY
  168. help
  169. PowerPC is a RISC architecture created by Apple-IBM-Motorola
  170. alliance. Big endian.
  171. http://www.power.org/
  172. http://en.wikipedia.org/wiki/Powerpc
  173. config BR2_powerpc64le
  174. bool "PowerPC64 (little endian)"
  175. select BR2_ARCH_IS_64
  176. select BR2_ARCH_HAS_MMU_MANDATORY
  177. help
  178. PowerPC is a RISC architecture created by Apple-IBM-Motorola
  179. alliance. Little endian.
  180. http://www.power.org/
  181. http://en.wikipedia.org/wiki/Powerpc
  182. config BR2_riscv
  183. bool "RISCV"
  184. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  185. help
  186. RISC-V is an open, free Instruction Set Architecture created
  187. by the UC Berkeley Architecture Research group and supported
  188. and promoted by RISC-V Foundation.
  189. https://riscv.org/
  190. https://en.wikipedia.org/wiki/RISC-V
  191. config BR2_s390x
  192. bool "s390x"
  193. select BR2_ARCH_IS_64
  194. select BR2_ARCH_HAS_MMU_MANDATORY
  195. help
  196. s390x is a big-endian architecture made by IBM.
  197. http://www.ibm.com/
  198. http://en.wikipedia.org/wiki/IBM_System/390
  199. config BR2_sh
  200. bool "SuperH"
  201. select BR2_ARCH_HAS_MMU_OPTIONAL
  202. help
  203. SuperH (or SH) is a 32-bit reduced instruction set computer
  204. (RISC) instruction set architecture (ISA) developed by
  205. Hitachi.
  206. http://www.hitachi.com/
  207. http://en.wikipedia.org/wiki/SuperH
  208. config BR2_sparc
  209. bool "SPARC"
  210. select BR2_ARCH_HAS_MMU_MANDATORY
  211. help
  212. SPARC (from Scalable Processor Architecture) is a RISC
  213. instruction set architecture (ISA) developed by Sun
  214. Microsystems.
  215. http://www.oracle.com/sun
  216. http://en.wikipedia.org/wiki/Sparc
  217. config BR2_sparc64
  218. bool "SPARC64"
  219. select BR2_ARCH_IS_64
  220. select BR2_ARCH_HAS_MMU_MANDATORY
  221. help
  222. SPARC (from Scalable Processor Architecture) is a RISC
  223. instruction set architecture (ISA) developed by Sun
  224. Microsystems.
  225. http://www.oracle.com/sun
  226. http://en.wikipedia.org/wiki/Sparc
  227. config BR2_x86_64
  228. bool "x86_64"
  229. select BR2_ARCH_IS_64
  230. select BR2_ARCH_HAS_MMU_MANDATORY
  231. help
  232. x86-64 is an extension of the x86 instruction set (Intel i386
  233. architecture compatible microprocessor).
  234. http://en.wikipedia.org/wiki/X86_64
  235. config BR2_xtensa
  236. bool "Xtensa"
  237. # MMU support is set by the subarchitecture file, arch/Config.in.xtensa
  238. help
  239. Xtensa is a Tensilica processor IP architecture.
  240. http://en.wikipedia.org/wiki/Xtensa
  241. http://www.tensilica.com/
  242. endchoice
  243. # For some architectures or specific cores, our internal toolchain
  244. # backend is not suitable (like, missing support in upstream gcc, or
  245. # no ChipCo fork exists...)
  246. config BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
  247. bool
  248. config BR2_ARCH_HAS_TOOLCHAIN_BUILDROOT
  249. bool
  250. default y if !BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
  251. # The following symbols are selected by the individual
  252. # Config.in.$ARCH files
  253. config BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8
  254. bool
  255. config BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
  256. bool
  257. select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8
  258. config BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  259. bool
  260. select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
  261. config BR2_ARCH_NEEDS_GCC_AT_LEAST_6
  262. bool
  263. select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  264. config BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  265. bool
  266. select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
  267. config BR2_ARCH_NEEDS_GCC_AT_LEAST_8
  268. bool
  269. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  270. config BR2_ARCH_NEEDS_GCC_AT_LEAST_9
  271. bool
  272. select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
  273. config BR2_ARCH_NEEDS_GCC_AT_LEAST_10
  274. bool
  275. select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
  276. config BR2_ARCH_NEEDS_GCC_AT_LEAST_11
  277. bool
  278. select BR2_ARCH_NEEDS_GCC_AT_LEAST_10
  279. # The following string values are defined by the individual
  280. # Config.in.$ARCH files
  281. config BR2_ARCH
  282. string
  283. config BR2_ENDIAN
  284. string
  285. config BR2_GCC_TARGET_ARCH
  286. string
  287. config BR2_GCC_TARGET_ABI
  288. string
  289. config BR2_GCC_TARGET_NAN
  290. string
  291. config BR2_GCC_TARGET_FP32_MODE
  292. string
  293. config BR2_GCC_TARGET_CPU
  294. string
  295. # The value of this option will be passed as --with-fpu=<value> when
  296. # building gcc (internal backend) or -mfpu=<value> in the toolchain
  297. # wrapper (external toolchain)
  298. config BR2_GCC_TARGET_FPU
  299. string
  300. # The value of this option will be passed as --with-float=<value> when
  301. # building gcc (internal backend) or -mfloat-abi=<value> in the toolchain
  302. # wrapper (external toolchain)
  303. config BR2_GCC_TARGET_FLOAT_ABI
  304. string
  305. # The value of this option will be passed as --with-mode=<value> when
  306. # building gcc (internal backend) or -m<value> in the toolchain
  307. # wrapper (external toolchain)
  308. config BR2_GCC_TARGET_MODE
  309. string
  310. # Must be selected by binary formats that support shared libraries.
  311. config BR2_BINFMT_SUPPORTS_SHARED
  312. bool
  313. # Must match the name of the architecture from readelf point of view,
  314. # i.e the "Machine:" field of readelf output. See get_machine_name()
  315. # in binutils/readelf.c for the list of possible values.
  316. config BR2_READELF_ARCH_NAME
  317. string
  318. # Set up target binary format
  319. choice
  320. prompt "Target Binary Format"
  321. default BR2_BINFMT_ELF if BR2_USE_MMU
  322. default BR2_BINFMT_FLAT
  323. config BR2_BINFMT_ELF
  324. bool "ELF"
  325. depends on BR2_USE_MMU
  326. select BR2_BINFMT_SUPPORTS_SHARED
  327. help
  328. ELF (Executable and Linkable Format) is a format for libraries
  329. and executables used across different architectures and
  330. operating systems.
  331. config BR2_BINFMT_FLAT
  332. bool "FLAT"
  333. depends on !BR2_USE_MMU
  334. help
  335. FLAT binary is a relatively simple and lightweight executable
  336. format based on the original a.out format. It is widely used
  337. in environment where no MMU is available.
  338. endchoice
  339. # Set up flat binary type
  340. choice
  341. prompt "FLAT Binary type"
  342. default BR2_BINFMT_FLAT_ONE
  343. depends on BR2_BINFMT_FLAT
  344. config BR2_BINFMT_FLAT_ONE
  345. bool "One memory region"
  346. help
  347. All segments are linked into one memory region.
  348. config BR2_BINFMT_FLAT_SHARED
  349. bool "Shared binary"
  350. depends on BR2_m68k
  351. # Even though this really generates shared binaries, there is no libdl
  352. # and dlopen() cannot be used. So packages that require shared
  353. # libraries cannot be built. Therefore, we don't select
  354. # BR2_BINFMT_SUPPORTS_SHARED and therefore force BR2_STATIC_LIBS.
  355. # Although this adds -static to the compilation, that's not a problem
  356. # because the -mid-shared-library option overrides it.
  357. help
  358. Allow to load and link indiviual FLAT binaries at run time.
  359. endchoice
  360. if BR2_arcle || BR2_arceb
  361. source "arch/Config.in.arc"
  362. endif
  363. if BR2_arm || BR2_armeb || BR2_aarch64 || BR2_aarch64_be
  364. source "arch/Config.in.arm"
  365. endif
  366. if BR2_csky
  367. source "arch/Config.in.csky"
  368. endif
  369. if BR2_m68k
  370. source "arch/Config.in.m68k"
  371. endif
  372. if BR2_microblazeel || BR2_microblazebe
  373. source "arch/Config.in.microblaze"
  374. endif
  375. if BR2_mips || BR2_mips64 || BR2_mipsel || BR2_mips64el
  376. source "arch/Config.in.mips"
  377. endif
  378. if BR2_nds32
  379. source "arch/Config.in.nds32"
  380. endif
  381. if BR2_nios2
  382. source "arch/Config.in.nios2"
  383. endif
  384. if BR2_or1k
  385. source "arch/Config.in.or1k"
  386. endif
  387. if BR2_powerpc || BR2_powerpc64 || BR2_powerpc64le
  388. source "arch/Config.in.powerpc"
  389. endif
  390. if BR2_riscv
  391. source "arch/Config.in.riscv"
  392. endif
  393. if BR2_s390x
  394. source "arch/Config.in.s390x"
  395. endif
  396. if BR2_sh
  397. source "arch/Config.in.sh"
  398. endif
  399. if BR2_sparc || BR2_sparc64
  400. source "arch/Config.in.sparc"
  401. endif
  402. if BR2_i386 || BR2_x86_64
  403. source "arch/Config.in.x86"
  404. endif
  405. if BR2_xtensa
  406. source "arch/Config.in.xtensa"
  407. endif
  408. endmenu # Target options