arch.mk.riscv 1.1 KB

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  1. #
  2. # Configure the GCC_TARGET_ARCH variable and append the
  3. # appropriate RISC-V ISA extensions.
  4. #
  5. ifeq ($(BR2_riscv),y)
  6. ifeq ($(BR2_RISCV_64),y)
  7. GCC_TARGET_ARCH := rv64i
  8. else
  9. GCC_TARGET_ARCH := rv32i
  10. endif
  11. ifeq ($(BR2_RISCV_ISA_RVM),y)
  12. GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)m
  13. endif
  14. ifeq ($(BR2_RISCV_ISA_RVA),y)
  15. GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)a
  16. endif
  17. ifeq ($(BR2_RISCV_ISA_RVF),y)
  18. GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)f
  19. endif
  20. ifeq ($(BR2_RISCV_ISA_RVD),y)
  21. GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)d
  22. endif
  23. ifeq ($(BR2_RISCV_ISA_RVC),y)
  24. GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c
  25. endif
  26. # Starting from gcc 12.x, csr and fence instructions have been
  27. # separated from the base I instruction set, and special -march
  28. # suffixes are needed to enable their support. In Buildroot, we assume
  29. # all RISC-V cores that support Linux implement those instructions, so
  30. # we unconditionally enable those extensions.
  31. # For starfive JH7110, add _zicsr_zifencei_zba_zbb as default march
  32. ifeq ($(BR2_TOOLCHAIN_GCC_AT_LEAST_12),y)
  33. GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)_zicsr_zifencei
  34. GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)_zba_zbb
  35. endif
  36. endif