0001-or1k-Add-mcmodel-option-to-handle-large-GOTs.patch 7.1 KB

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  1. From 7a20b4574f06472086c786bd1b078ee962cdb02c Mon Sep 17 00:00:00 2001
  2. From: Stafford Horne <shorne@gmail.com>
  3. Date: Tue, 6 Apr 2021 05:47:17 +0900
  4. Subject: [PATCH] or1k: Add mcmodel option to handle large GOTs
  5. When building libgeos we get an error with:
  6. linux-uclibc/9.3.0/crtbeginS.o: in function `__do_global_dtors_aux':
  7. crtstuff.c:(.text+0x118): relocation truncated to fit: R_OR1K_GOT16 against symbol `__cxa_finalize' defined in .text section in
  8. /home/shorne/work/openrisc/3eb9f9d0f6d8274b2d19753c006bd83f7d536e3c/output/host/or1k-buildroot-linux-uclibc/sysroot/lib/libc.so.
  9. This is caused by GOT code having a limit of 64k. In OpenRISC this
  10. looks to be the only relocation code pattern to be limited to 64k.
  11. This patch allows specifying a new option -mcmodel=large which can be
  12. used to generate 2 more instructions to construct 32-bit addresses for
  13. up to 4G GOTs.
  14. gcc/ChangeLog:
  15. PR target/99783
  16. * config/or1k/or1k-opts.h: New file.
  17. * config/or1k/or1k.c (or1k_legitimize_address_1, print_reloc):
  18. Support generating gotha relocations if -mcmodel=large is
  19. specified.
  20. * config/or1k/or1k.h (TARGET_CMODEL_SMALL, TARGET_CMODEL_LARGE):
  21. New macros.
  22. * config/or1k/or1k.opt (mcmodel=): New option.
  23. * doc/invoke.texi (OpenRISC Options): Document mcmodel.
  24. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
  25. ---
  26. gcc/config/or1k/or1k-opts.h | 30 ++++++++++++++++++++++++++++++
  27. gcc/config/or1k/or1k.c | 11 +++++++++--
  28. gcc/config/or1k/or1k.h | 7 +++++++
  29. gcc/config/or1k/or1k.opt | 19 +++++++++++++++++++
  30. gcc/doc/invoke.texi | 12 +++++++++++-
  31. 5 files changed, 76 insertions(+), 3 deletions(-)
  32. create mode 100644 gcc/config/or1k/or1k-opts.h
  33. diff --git a/gcc/config/or1k/or1k-opts.h b/gcc/config/or1k/or1k-opts.h
  34. new file mode 100644
  35. index 00000000000..f791b894fdd
  36. --- /dev/null
  37. +++ b/gcc/config/or1k/or1k-opts.h
  38. @@ -0,0 +1,30 @@
  39. +/* Definitions for option handling for OpenRISC.
  40. + Copyright (C) 2021 Free Software Foundation, Inc.
  41. + Contributed by Stafford Horne.
  42. +
  43. + This file is part of GCC.
  44. +
  45. + GCC is free software; you can redistribute it and/or modify it
  46. + under the terms of the GNU General Public License as published
  47. + by the Free Software Foundation; either version 3, or (at your
  48. + option) any later version.
  49. +
  50. + GCC is distributed in the hope that it will be useful, but WITHOUT
  51. + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  52. + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  53. + License for more details.
  54. +
  55. + You should have received a copy of the GNU General Public License
  56. + along with GCC; see the file COPYING3. If not see
  57. + <http://www.gnu.org/licenses/>. */
  58. +
  59. +#ifndef GCC_OR1K_OPTS_H
  60. +#define GCC_OR1K_OPTS_H
  61. +
  62. +/* The OpenRISC code generation models available. */
  63. +enum or1k_cmodel_type {
  64. + CMODEL_SMALL,
  65. + CMODEL_LARGE
  66. +};
  67. +
  68. +#endif /* GCC_OR1K_OPTS_H */
  69. diff --git a/gcc/config/or1k/or1k.c b/gcc/config/or1k/or1k.c
  70. index e772a7addea..27d3fa17995 100644
  71. --- a/gcc/config/or1k/or1k.c
  72. +++ b/gcc/config/or1k/or1k.c
  73. @@ -750,7 +750,14 @@ or1k_legitimize_address_1 (rtx x, rtx scratch)
  74. {
  75. base = gen_sym_unspec (base, UNSPEC_GOT);
  76. crtl->uses_pic_offset_table = 1;
  77. - t2 = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, base);
  78. + if (TARGET_CMODEL_LARGE)
  79. + {
  80. + emit_insn (gen_rtx_SET (t1, gen_rtx_HIGH (Pmode, base)));
  81. + emit_insn (gen_add3_insn (t1, t1, pic_offset_table_rtx));
  82. + t2 = gen_rtx_LO_SUM (Pmode, t1, base);
  83. + }
  84. + else
  85. + t2 = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, base);
  86. t2 = gen_const_mem (Pmode, t2);
  87. emit_insn (gen_rtx_SET (t1, t2));
  88. base = t1;
  89. @@ -1089,7 +1096,7 @@ print_reloc (FILE *stream, rtx x, HOST_WIDE_INT add, reloc_kind kind)
  90. no special markup. */
  91. static const char * const relocs[RKIND_MAX][RTYPE_MAX] = {
  92. { "lo", "got", "gotofflo", "tpofflo", "gottpofflo", "tlsgdlo" },
  93. - { "ha", NULL, "gotoffha", "tpoffha", "gottpoffha", "tlsgdhi" },
  94. + { "ha", "gotha", "gotoffha", "tpoffha", "gottpoffha", "tlsgdhi" },
  95. };
  96. reloc_type type = RTYPE_DIRECT;
  97. diff --git a/gcc/config/or1k/or1k.h b/gcc/config/or1k/or1k.h
  98. index fe01ab81ead..669907e7e74 100644
  99. --- a/gcc/config/or1k/or1k.h
  100. +++ b/gcc/config/or1k/or1k.h
  101. @@ -21,6 +21,8 @@
  102. #ifndef GCC_OR1K_H
  103. #define GCC_OR1K_H
  104. +#include "config/or1k/or1k-opts.h"
  105. +
  106. /* Names to predefine in the preprocessor for this target machine. */
  107. #define TARGET_CPU_CPP_BUILTINS() \
  108. do \
  109. @@ -37,6 +39,11 @@
  110. } \
  111. while (0)
  112. +#define TARGET_CMODEL_SMALL \
  113. + (or1k_code_model == CMODEL_SMALL)
  114. +#define TARGET_CMODEL_LARGE \
  115. + (or1k_code_model == CMODEL_LARGE)
  116. +
  117. /* Storage layout. */
  118. #define DEFAULT_SIGNED_CHAR 1
  119. diff --git a/gcc/config/or1k/or1k.opt b/gcc/config/or1k/or1k.opt
  120. index 6bd0f3eee6d..cc23e3b8856 100644
  121. --- a/gcc/config/or1k/or1k.opt
  122. +++ b/gcc/config/or1k/or1k.opt
  123. @@ -21,6 +21,9 @@
  124. ; See the GCC internals manual (options.texi) for a description of
  125. ; this file's format.
  126. +HeaderInclude
  127. +config/or1k/or1k-opts.h
  128. +
  129. mhard-div
  130. Target RejectNegative InverseMask(SOFT_DIV)
  131. Enable generation of hardware divide (l.div, l.divu) instructions. This is the
  132. @@ -63,6 +66,22 @@ When -mhard-float is selected, enables generation of unordered floating point
  133. compare and set flag (lf.sfun*) instructions. By default functions from libgcc
  134. are used to perform unordered floating point compare and set flag operations.
  135. +mcmodel=
  136. +Target RejectNegative Joined Enum(or1k_cmodel_type) Var(or1k_code_model) Init(CMODEL_SMALL)
  137. +Specify the code model used for accessing memory addresses. Specifying large
  138. +enables generating binaries with large global offset tables. By default the
  139. +value is small.
  140. +
  141. +Enum
  142. +Name(or1k_cmodel_type) Type(enum or1k_cmodel_type)
  143. +Known code model types (for use with the -mcmodel= option):
  144. +
  145. +EnumValue
  146. +Enum(or1k_cmodel_type) String(small) Value(CMODEL_SMALL)
  147. +
  148. +EnumValue
  149. +Enum(or1k_cmodel_type) String(large) Value(CMODEL_LARGE)
  150. +
  151. mcmov
  152. Target RejectNegative Mask(CMOV)
  153. Enable generation of conditional move (l.cmov) instructions. By default the
  154. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
  155. index 35508efb4ef..a1b7608a3aa 100644
  156. --- a/gcc/doc/invoke.texi
  157. +++ b/gcc/doc/invoke.texi
  158. @@ -1136,7 +1136,8 @@ Objective-C and Objective-C++ Dialects}.
  159. @gccoptlist{-mboard=@var{name} -mnewlib -mhard-mul -mhard-div @gol
  160. -msoft-mul -msoft-div @gol
  161. -msoft-float -mhard-float -mdouble-float -munordered-float @gol
  162. --mcmov -mror -mrori -msext -msfimm -mshftimm}
  163. +-mcmov -mror -mrori -msext -msfimm -mshftimm @gol
  164. +-mcmodel=@var{code-model}}
  165. @emph{PDP-11 Options}
  166. @gccoptlist{-mfpu -msoft-float -mac0 -mno-ac0 -m40 -m45 -m10 @gol
  167. @@ -26443,6 +26444,15 @@ Enable generation of shift with immediate (@code{l.srai}, @code{l.srli},
  168. @code{l.slli}) instructions. By default extra instructions will be generated
  169. to store the immediate to a register first.
  170. +@item -mcmodel=small
  171. +@opindex mcmodel=small
  172. +Generate OpenRISC code for the small model: The GOT is limited to 64k. This is
  173. +the default model.
  174. +
  175. +@item -mcmodel=large
  176. +@opindex mcmodel=large
  177. +Generate OpenRISC code for the large model: The GOT may grow up to 4G in size.
  178. +
  179. @end table
  180. --
  181. 2.35.1