lx9_mmu.dts 9.3 KB

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  1. /*
  2. * Device Tree Generator version: 1.3
  3. *
  4. * (C) Copyright 2007-2008 Xilinx, Inc.
  5. * (C) Copyright 2007-2009 Michal Simek
  6. *
  7. * Michal SIMEK <monstr@monstr.eu>
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. *
  24. * CAUTION: This file is automatically generated by libgen.
  25. * Version: Xilinx EDK 13.2 EDK_O.61xd
  26. *
  27. * XPS project directory: device-tree_bsp_230-orig
  28. */
  29. /dts-v1/;
  30. / {
  31. #address-cells = <1>;
  32. #size-cells = <1>;
  33. compatible = "xlnx,microblaze";
  34. model = "testing";
  35. MCB3_LPDDR: memory@80000000 {
  36. device_type = "memory";
  37. reg = < 0x80000000 0x4000000 >;
  38. } ;
  39. aliases {
  40. ethernet0 = &Ethernet_MAC;
  41. serial0 = &USB_Uart;
  42. } ;
  43. chosen {
  44. bootargs = "console=ttyUL0";
  45. linux,stdout-path = "/axi@0/serial@40600000";
  46. } ;
  47. cpus {
  48. #address-cells = <1>;
  49. #cpus = <0x1>;
  50. #size-cells = <0>;
  51. microblaze_0: cpu@0 {
  52. clock-frequency = <66666667>;
  53. compatible = "xlnx,microblaze-8.20.a";
  54. d-cache-baseaddr = <0x80000000>;
  55. d-cache-highaddr = <0x83ffffff>;
  56. d-cache-line-size = <0x10>;
  57. d-cache-size = <0x2000>;
  58. device_type = "cpu";
  59. i-cache-baseaddr = <0x80000000>;
  60. i-cache-highaddr = <0x83ffffff>;
  61. i-cache-line-size = <0x10>;
  62. i-cache-size = <0x2000>;
  63. model = "microblaze,8.20.a";
  64. reg = <0>;
  65. timebase-frequency = <66666667>;
  66. xlnx,addr-tag-bits = <0xd>;
  67. xlnx,allow-dcache-wr = <0x1>;
  68. xlnx,allow-icache-wr = <0x1>;
  69. xlnx,area-optimized = <0x0>;
  70. xlnx,avoid-primitives = <0x0>;
  71. xlnx,branch-target-cache-size = <0x0>;
  72. xlnx,cache-byte-size = <0x2000>;
  73. xlnx,d-axi = <0x1>;
  74. xlnx,d-lmb = <0x1>;
  75. xlnx,d-plb = <0x0>;
  76. xlnx,data-size = <0x20>;
  77. xlnx,dcache-addr-tag = <0xd>;
  78. xlnx,dcache-always-used = <0x1>;
  79. xlnx,dcache-byte-size = <0x2000>;
  80. xlnx,dcache-data-width = <0x0>;
  81. xlnx,dcache-force-tag-lutram = <0x0>;
  82. xlnx,dcache-interface = <0x0>;
  83. xlnx,dcache-line-len = <0x4>;
  84. xlnx,dcache-use-fsl = <0x0>;
  85. xlnx,dcache-use-writeback = <0x0>;
  86. xlnx,dcache-victims = <0x0>;
  87. xlnx,debug-enabled = <0x1>;
  88. xlnx,div-zero-exception = <0x0>;
  89. xlnx,dynamic-bus-sizing = <0x1>;
  90. xlnx,ecc-use-ce-exception = <0x0>;
  91. xlnx,edge-is-positive = <0x1>;
  92. xlnx,endianness = <0x1>;
  93. xlnx,family = "spartan6";
  94. xlnx,fault-tolerant = <0x0>;
  95. xlnx,fpu-exception = <0x0>;
  96. xlnx,freq = <0x3f940ab>;
  97. xlnx,fsl-data-size = <0x20>;
  98. xlnx,fsl-exception = <0x0>;
  99. xlnx,fsl-links = <0x0>;
  100. xlnx,i-axi = <0x0>;
  101. xlnx,i-lmb = <0x1>;
  102. xlnx,i-plb = <0x0>;
  103. xlnx,icache-always-used = <0x1>;
  104. xlnx,icache-data-width = <0x0>;
  105. xlnx,icache-force-tag-lutram = <0x0>;
  106. xlnx,icache-interface = <0x0>;
  107. xlnx,icache-line-len = <0x4>;
  108. xlnx,icache-streams = <0x0>;
  109. xlnx,icache-use-fsl = <0x0>;
  110. xlnx,icache-victims = <0x0>;
  111. xlnx,ill-opcode-exception = <0x0>;
  112. xlnx,instance = "microblaze_0";
  113. xlnx,interconnect = <0x2>;
  114. xlnx,interconnect-m-axi-dc-aw-register = <0x0>;
  115. xlnx,interconnect-m-axi-dc-read-issuing = <0x2>;
  116. xlnx,interconnect-m-axi-dc-w-register = <0x0>;
  117. xlnx,interconnect-m-axi-dc-write-issuing = <0x20>;
  118. xlnx,interconnect-m-axi-dp-read-issuing = <0x1>;
  119. xlnx,interconnect-m-axi-dp-write-issuing = <0x1>;
  120. xlnx,interconnect-m-axi-ic-read-issuing = <0x2>;
  121. xlnx,interconnect-m-axi-ip-read-issuing = <0x1>;
  122. xlnx,interrupt-is-edge = <0x0>;
  123. xlnx,lockstep-slave = <0x0>;
  124. xlnx,mmu-dtlb-size = <0x1>;
  125. xlnx,mmu-itlb-size = <0x1>;
  126. xlnx,mmu-privileged-instr = <0x0>;
  127. xlnx,mmu-tlb-access = <0x3>;
  128. xlnx,mmu-zones = <0x2>;
  129. xlnx,number-of-pc-brk = <0x1>;
  130. xlnx,number-of-rd-addr-brk = <0x0>;
  131. xlnx,number-of-wr-addr-brk = <0x0>;
  132. xlnx,opcode-0x0-illegal = <0x0>;
  133. xlnx,optimization = <0x0>;
  134. xlnx,pvr = <0x0>;
  135. xlnx,pvr-user1 = <0x0>;
  136. xlnx,pvr-user2 = <0x0>;
  137. xlnx,reset-msr = <0x0>;
  138. xlnx,sco = <0x0>;
  139. xlnx,stream-interconnect = <0x0>;
  140. xlnx,unaligned-exceptions = <0x0>;
  141. xlnx,use-barrel = <0x1>;
  142. xlnx,use-branch-target-cache = <0x0>;
  143. xlnx,use-dcache = <0x1>;
  144. xlnx,use-div = <0x0>;
  145. xlnx,use-ext-brk = <0x1>;
  146. xlnx,use-ext-nm-brk = <0x1>;
  147. xlnx,use-extended-fsl-instr = <0x0>;
  148. xlnx,use-fpu = <0x0>;
  149. xlnx,use-hw-mul = <0x1>;
  150. xlnx,use-icache = <0x1>;
  151. xlnx,use-interrupt = <0x1>;
  152. xlnx,use-mmu = <0x3>;
  153. xlnx,use-msr-instr = <0x1>;
  154. xlnx,use-pcmp-instr = <0x0>;
  155. xlnx,use-stack-protection = <0x0>;
  156. } ;
  157. } ;
  158. axi4lite_0: axi@0 {
  159. #address-cells = <1>;
  160. #size-cells = <1>;
  161. compatible = "xlnx,axi-interconnect-1.03.a", "simple-bus";
  162. ranges ;
  163. Ethernet_MAC: ethernet@40e00000 {
  164. compatible = "xlnx,axi-ethernetlite-1.00.a", "xlnx,xps-ethernetlite-1.00.a";
  165. device_type = "network";
  166. interrupt-parent = <&microblaze_0_intc>;
  167. interrupts = < 2 0 >;
  168. local-mac-address = [ 00 0a 35 aa de 00 ];
  169. // phy-handle = <&phy0>;
  170. reg = < 0x40e00000 0x10000 >;
  171. xlnx,duplex = <0x1>;
  172. xlnx,family = "spartan6";
  173. xlnx,include-global-buffers = <0x0>;
  174. xlnx,include-internal-loopback = <0x0>;
  175. xlnx,include-mdio = <0x1>;
  176. xlnx,include-phy-constraints = <0x1>;
  177. xlnx,interconnect-s-axi-read-acceptance = <0x1>;
  178. xlnx,interconnect-s-axi-write-acceptance = <0x1>;
  179. xlnx,rx-ping-pong = <0x0>;
  180. xlnx,s-axi-aclk-period-ps = <0x3a98>;
  181. xlnx,s-axi-id-width = <0x1>;
  182. xlnx,s-axi-supports-narrow-burst = <0x0>;
  183. xlnx,tx-ping-pong = <0x0>;
  184. /*
  185. mdio {
  186. #address-cells = <1>;
  187. #size-cells = <0>;
  188. phy0: phy@7 {
  189. compatible = "marvell,88e1111";
  190. device_type = "ethernet-phy";
  191. reg = <7>;
  192. } ;
  193. } ;
  194. */
  195. } ;
  196. SPI_FLASH: spi@40a00000 {
  197. compatible = "xlnx,axi-spi-1.01.a", "xlnx,xps-spi-2.00.a";
  198. interrupt-parent = <&microblaze_0_intc>;
  199. interrupts = < 1 2 >;
  200. reg = < 0x40a00000 0x10000 >;
  201. xlnx,family = "spartan6";
  202. xlnx,fifo-exist = <0x1>;
  203. xlnx,num-ss-bits = <0x1>;
  204. xlnx,num-transfer-bits = <0x8>;
  205. xlnx,sck-ratio = <0x4>;
  206. } ;
  207. USB_Uart: serial@40600000 {
  208. clock-frequency = <66666667>;
  209. compatible = "xlnx,axi-uartlite-1.02.a", "xlnx,xps-uartlite-1.00.a";
  210. current-speed = <115200>;
  211. device_type = "serial";
  212. interrupt-parent = <&microblaze_0_intc>;
  213. interrupts = < 3 0 >;
  214. port-number = <0>;
  215. reg = < 0x40600000 0x10000 >;
  216. xlnx,baudrate = <0x1c200>;
  217. xlnx,data-bits = <0x8>;
  218. xlnx,family = "spartan6";
  219. xlnx,odd-parity = <0x1>;
  220. xlnx,s-axi-aclk-freq-hz = <0x3f940ab>;
  221. xlnx,use-parity = <0x0>;
  222. } ;
  223. microblaze_0_intc: interrupt-controller@41200000 {
  224. #interrupt-cells = <0x2>;
  225. compatible = "xlnx,axi-intc-1.01.a", "xlnx,xps-intc-1.00.a";
  226. interrupt-controller ;
  227. reg = < 0x41200000 0x10000 >;
  228. xlnx,kind-of-intr = <0xc>;
  229. xlnx,num-intr-inputs = <0x4>;
  230. } ;
  231. system_timer: timer@41c00000 {
  232. clock-frequency = <66666667>;
  233. compatible = "xlnx,axi-timer-1.02.a", "xlnx,xps-timer-1.00.a";
  234. interrupt-parent = <&microblaze_0_intc>;
  235. interrupts = < 0 2 >;
  236. reg = < 0x41c00000 0x10000 >;
  237. xlnx,count-width = <0x20>;
  238. xlnx,family = "spartan6";
  239. xlnx,gen0-assert = <0x1>;
  240. xlnx,gen1-assert = <0x1>;
  241. xlnx,one-timer-only = <0x0>;
  242. xlnx,trig0-assert = <0x1>;
  243. xlnx,trig1-assert = <0x1>;
  244. } ;
  245. } ;
  246. } ;