Config.in 12 KB

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  1. menu "Target options"
  2. config BR2_ARCH_IS_64
  3. bool
  4. config BR2_KERNEL_64_USERLAND_32
  5. bool
  6. config BR2_SOFT_FLOAT
  7. bool
  8. config BR2_ARCH_HAS_MMU_MANDATORY
  9. bool
  10. config BR2_ARCH_HAS_MMU_OPTIONAL
  11. bool
  12. choice
  13. prompt "Target Architecture"
  14. default BR2_i386
  15. help
  16. Select the target architecture family to build for.
  17. config BR2_arcle
  18. bool "ARC (little endian)"
  19. select BR2_ARCH_HAS_MMU_MANDATORY
  20. help
  21. Synopsys' DesignWare ARC Processor Cores are a family of
  22. 32-bit CPUs that can be used from deeply embedded to high
  23. performance host applications. Little endian.
  24. config BR2_arceb
  25. bool "ARC (big endian)"
  26. select BR2_ARCH_HAS_MMU_MANDATORY
  27. help
  28. Synopsys' DesignWare ARC Processor Cores are a family of
  29. 32-bit CPUs that can be used from deeply embedded to high
  30. performance host applications. Big endian.
  31. config BR2_arm
  32. bool "ARM (little endian)"
  33. # MMU support is set by the subarchitecture file, arch/Config.in.arm
  34. help
  35. ARM is a 32-bit reduced instruction set computer (RISC)
  36. instruction set architecture (ISA) developed by ARM Holdings.
  37. Little endian.
  38. http://www.arm.com/
  39. http://en.wikipedia.org/wiki/ARM
  40. config BR2_armeb
  41. bool "ARM (big endian)"
  42. # MMU support is set by the subarchitecture file, arch/Config.in.arm
  43. help
  44. ARM is a 32-bit reduced instruction set computer (RISC)
  45. instruction set architecture (ISA) developed by ARM Holdings.
  46. Big endian.
  47. http://www.arm.com/
  48. http://en.wikipedia.org/wiki/ARM
  49. config BR2_aarch64
  50. bool "AArch64 (little endian)"
  51. select BR2_ARCH_IS_64
  52. select BR2_ARCH_HAS_MMU_MANDATORY
  53. help
  54. Aarch64 is a 64-bit architecture developed by ARM Holdings.
  55. http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
  56. http://en.wikipedia.org/wiki/ARM
  57. config BR2_aarch64_be
  58. bool "AArch64 (big endian)"
  59. select BR2_ARCH_IS_64
  60. select BR2_ARCH_HAS_MMU_MANDATORY
  61. help
  62. Aarch64 is a 64-bit architecture developed by ARM Holdings.
  63. http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
  64. http://en.wikipedia.org/wiki/ARM
  65. config BR2_csky
  66. bool "csky"
  67. select BR2_ARCH_HAS_MMU_MANDATORY
  68. # Most variants are supported by gcc-9+, except one that is
  69. # handled as a special exception in package/gcc/Config.in.host
  70. select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
  71. help
  72. csky is processor IP from china.
  73. http://www.c-sky.com/
  74. http://www.github.com/c-sky
  75. config BR2_i386
  76. bool "i386"
  77. select BR2_ARCH_HAS_MMU_MANDATORY
  78. help
  79. Intel i386 architecture compatible microprocessor
  80. http://en.wikipedia.org/wiki/I386
  81. config BR2_m68k
  82. bool "m68k"
  83. # MMU support is set by the subarchitecture file, arch/Config.in.m68k
  84. help
  85. Motorola 68000 family microprocessor
  86. http://en.wikipedia.org/wiki/M68k
  87. config BR2_microblazeel
  88. bool "Microblaze AXI (little endian)"
  89. select BR2_ARCH_HAS_MMU_MANDATORY
  90. help
  91. Soft processor core designed for Xilinx FPGAs from Xilinx. AXI
  92. bus based architecture (little endian)
  93. http://www.xilinx.com
  94. http://en.wikipedia.org/wiki/Microblaze
  95. config BR2_microblazebe
  96. bool "Microblaze non-AXI (big endian)"
  97. select BR2_ARCH_HAS_MMU_MANDATORY
  98. help
  99. Soft processor core designed for Xilinx FPGAs from Xilinx. PLB
  100. bus based architecture (non-AXI, big endian)
  101. http://www.xilinx.com
  102. http://en.wikipedia.org/wiki/Microblaze
  103. config BR2_mips
  104. bool "MIPS (big endian)"
  105. select BR2_ARCH_HAS_MMU_MANDATORY
  106. help
  107. MIPS is a RISC microprocessor from MIPS Technologies. Big
  108. endian.
  109. http://www.mips.com/
  110. http://en.wikipedia.org/wiki/MIPS_Technologies
  111. config BR2_mipsel
  112. bool "MIPS (little endian)"
  113. select BR2_ARCH_HAS_MMU_MANDATORY
  114. help
  115. MIPS is a RISC microprocessor from MIPS Technologies. Little
  116. endian.
  117. http://www.mips.com/
  118. http://en.wikipedia.org/wiki/MIPS_Technologies
  119. config BR2_mips64
  120. bool "MIPS64 (big endian)"
  121. select BR2_ARCH_IS_64
  122. select BR2_ARCH_HAS_MMU_MANDATORY
  123. help
  124. MIPS is a RISC microprocessor from MIPS Technologies. Big
  125. endian.
  126. http://www.mips.com/
  127. http://en.wikipedia.org/wiki/MIPS_Technologies
  128. config BR2_mips64el
  129. bool "MIPS64 (little endian)"
  130. select BR2_ARCH_IS_64
  131. select BR2_ARCH_HAS_MMU_MANDATORY
  132. help
  133. MIPS is a RISC microprocessor from MIPS Technologies. Little
  134. endian.
  135. http://www.mips.com/
  136. http://en.wikipedia.org/wiki/MIPS_Technologies
  137. config BR2_nds32
  138. bool "nds32"
  139. select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
  140. select BR2_ARCH_HAS_MMU_MANDATORY
  141. help
  142. nds32 is a 32-bit architecture developed by Andes Technology.
  143. https://en.wikipedia.org/wiki/Andes_Technology
  144. config BR2_nios2
  145. bool "Nios II"
  146. select BR2_ARCH_HAS_MMU_MANDATORY
  147. help
  148. Nios II is a soft core processor from Altera Corporation.
  149. http://www.altera.com/
  150. http://en.wikipedia.org/wiki/Nios_II
  151. config BR2_or1k
  152. bool "OpenRISC"
  153. select BR2_ARCH_HAS_MMU_MANDATORY
  154. help
  155. OpenRISC is a free and open processor for embedded system.
  156. http://openrisc.io
  157. config BR2_powerpc
  158. bool "PowerPC"
  159. select BR2_ARCH_HAS_MMU_MANDATORY
  160. help
  161. PowerPC is a RISC architecture created by Apple-IBM-Motorola
  162. alliance. Big endian.
  163. http://www.power.org/
  164. http://en.wikipedia.org/wiki/Powerpc
  165. config BR2_powerpc64
  166. bool "PowerPC64 (big endian)"
  167. select BR2_ARCH_IS_64
  168. select BR2_ARCH_HAS_MMU_MANDATORY
  169. help
  170. PowerPC is a RISC architecture created by Apple-IBM-Motorola
  171. alliance. Big endian.
  172. http://www.power.org/
  173. http://en.wikipedia.org/wiki/Powerpc
  174. config BR2_powerpc64le
  175. bool "PowerPC64 (little endian)"
  176. select BR2_ARCH_IS_64
  177. select BR2_ARCH_HAS_MMU_MANDATORY
  178. help
  179. PowerPC is a RISC architecture created by Apple-IBM-Motorola
  180. alliance. Little endian.
  181. http://www.power.org/
  182. http://en.wikipedia.org/wiki/Powerpc
  183. config BR2_riscv
  184. bool "RISCV"
  185. select BR2_ARCH_HAS_MMU_MANDATORY
  186. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  187. help
  188. RISC-V is an open, free Instruction Set Architecture created
  189. by the UC Berkeley Architecture Research group and supported
  190. and promoted by RISC-V Foundation.
  191. https://riscv.org/
  192. https://en.wikipedia.org/wiki/RISC-V
  193. config BR2_s390x
  194. bool "s390x"
  195. select BR2_ARCH_IS_64
  196. select BR2_ARCH_HAS_MMU_MANDATORY
  197. help
  198. s390x is a big-endian architecture made by IBM.
  199. http://www.ibm.com/
  200. http://en.wikipedia.org/wiki/IBM_System/390
  201. config BR2_sh
  202. bool "SuperH"
  203. select BR2_ARCH_HAS_MMU_OPTIONAL
  204. help
  205. SuperH (or SH) is a 32-bit reduced instruction set computer
  206. (RISC) instruction set architecture (ISA) developed by
  207. Hitachi.
  208. http://www.hitachi.com/
  209. http://en.wikipedia.org/wiki/SuperH
  210. config BR2_sparc
  211. bool "SPARC"
  212. select BR2_ARCH_HAS_MMU_MANDATORY
  213. help
  214. SPARC (from Scalable Processor Architecture) is a RISC
  215. instruction set architecture (ISA) developed by Sun
  216. Microsystems.
  217. http://www.oracle.com/sun
  218. http://en.wikipedia.org/wiki/Sparc
  219. config BR2_sparc64
  220. bool "SPARC64"
  221. select BR2_ARCH_IS_64
  222. select BR2_ARCH_HAS_MMU_MANDATORY
  223. help
  224. SPARC (from Scalable Processor Architecture) is a RISC
  225. instruction set architecture (ISA) developed by Sun
  226. Microsystems.
  227. http://www.oracle.com/sun
  228. http://en.wikipedia.org/wiki/Sparc
  229. config BR2_x86_64
  230. bool "x86_64"
  231. select BR2_ARCH_IS_64
  232. select BR2_ARCH_HAS_MMU_MANDATORY
  233. help
  234. x86-64 is an extension of the x86 instruction set (Intel i386
  235. architecture compatible microprocessor).
  236. http://en.wikipedia.org/wiki/X86_64
  237. config BR2_xtensa
  238. bool "Xtensa"
  239. # MMU support is set by the subarchitecture file, arch/Config.in.xtensa
  240. help
  241. Xtensa is a Tensilica processor IP architecture.
  242. http://en.wikipedia.org/wiki/Xtensa
  243. http://www.tensilica.com/
  244. endchoice
  245. # For some architectures or specific cores, our internal toolchain
  246. # backend is not suitable (like, missing support in upstream gcc, or
  247. # no ChipCo fork exists...)
  248. config BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
  249. bool
  250. config BR2_ARCH_HAS_TOOLCHAIN_BUILDROOT
  251. bool
  252. default y if !BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
  253. # The following symbols are selected by the individual
  254. # Config.in.$ARCH files
  255. config BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8
  256. bool
  257. config BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
  258. bool
  259. select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8
  260. config BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  261. bool
  262. select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
  263. config BR2_ARCH_NEEDS_GCC_AT_LEAST_6
  264. bool
  265. select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  266. config BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  267. bool
  268. select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
  269. config BR2_ARCH_NEEDS_GCC_AT_LEAST_8
  270. bool
  271. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  272. config BR2_ARCH_NEEDS_GCC_AT_LEAST_9
  273. bool
  274. select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
  275. config BR2_ARCH_NEEDS_GCC_AT_LEAST_10
  276. bool
  277. select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
  278. # The following string values are defined by the individual
  279. # Config.in.$ARCH files
  280. config BR2_ARCH
  281. string
  282. config BR2_ENDIAN
  283. string
  284. config BR2_GCC_TARGET_ARCH
  285. string
  286. config BR2_GCC_TARGET_ABI
  287. string
  288. config BR2_GCC_TARGET_NAN
  289. string
  290. config BR2_GCC_TARGET_FP32_MODE
  291. string
  292. config BR2_GCC_TARGET_CPU
  293. string
  294. # The value of this option will be passed as --with-fpu=<value> when
  295. # building gcc (internal backend) or -mfpu=<value> in the toolchain
  296. # wrapper (external toolchain)
  297. config BR2_GCC_TARGET_FPU
  298. string
  299. # The value of this option will be passed as --with-float=<value> when
  300. # building gcc (internal backend) or -mfloat-abi=<value> in the toolchain
  301. # wrapper (external toolchain)
  302. config BR2_GCC_TARGET_FLOAT_ABI
  303. string
  304. # The value of this option will be passed as --with-mode=<value> when
  305. # building gcc (internal backend) or -m<value> in the toolchain
  306. # wrapper (external toolchain)
  307. config BR2_GCC_TARGET_MODE
  308. string
  309. # Must be selected by binary formats that support shared libraries.
  310. config BR2_BINFMT_SUPPORTS_SHARED
  311. bool
  312. # Must match the name of the architecture from readelf point of view,
  313. # i.e the "Machine:" field of readelf output. See get_machine_name()
  314. # in binutils/readelf.c for the list of possible values.
  315. config BR2_READELF_ARCH_NAME
  316. string
  317. # Set up target binary format
  318. choice
  319. prompt "Target Binary Format"
  320. default BR2_BINFMT_ELF if BR2_USE_MMU
  321. default BR2_BINFMT_FLAT
  322. config BR2_BINFMT_ELF
  323. bool "ELF"
  324. depends on BR2_USE_MMU
  325. select BR2_BINFMT_SUPPORTS_SHARED
  326. help
  327. ELF (Executable and Linkable Format) is a format for libraries
  328. and executables used across different architectures and
  329. operating systems.
  330. config BR2_BINFMT_FLAT
  331. bool "FLAT"
  332. depends on !BR2_USE_MMU
  333. help
  334. FLAT binary is a relatively simple and lightweight executable
  335. format based on the original a.out format. It is widely used
  336. in environment where no MMU is available.
  337. endchoice
  338. # Set up flat binary type
  339. choice
  340. prompt "FLAT Binary type"
  341. default BR2_BINFMT_FLAT_ONE
  342. depends on BR2_BINFMT_FLAT
  343. config BR2_BINFMT_FLAT_ONE
  344. bool "One memory region"
  345. help
  346. All segments are linked into one memory region.
  347. config BR2_BINFMT_FLAT_SHARED
  348. bool "Shared binary"
  349. depends on BR2_m68k
  350. # Even though this really generates shared binaries, there is no libdl
  351. # and dlopen() cannot be used. So packages that require shared
  352. # libraries cannot be built. Therefore, we don't select
  353. # BR2_BINFMT_SUPPORTS_SHARED and therefore force BR2_STATIC_LIBS.
  354. # Although this adds -static to the compilation, that's not a problem
  355. # because the -mid-shared-library option overrides it.
  356. help
  357. Allow to load and link indiviual FLAT binaries at run time.
  358. endchoice
  359. if BR2_arcle || BR2_arceb
  360. source "arch/Config.in.arc"
  361. endif
  362. if BR2_arm || BR2_armeb || BR2_aarch64 || BR2_aarch64_be
  363. source "arch/Config.in.arm"
  364. endif
  365. if BR2_csky
  366. source "arch/Config.in.csky"
  367. endif
  368. if BR2_m68k
  369. source "arch/Config.in.m68k"
  370. endif
  371. if BR2_microblazeel || BR2_microblazebe
  372. source "arch/Config.in.microblaze"
  373. endif
  374. if BR2_mips || BR2_mips64 || BR2_mipsel || BR2_mips64el
  375. source "arch/Config.in.mips"
  376. endif
  377. if BR2_nds32
  378. source "arch/Config.in.nds32"
  379. endif
  380. if BR2_nios2
  381. source "arch/Config.in.nios2"
  382. endif
  383. if BR2_or1k
  384. source "arch/Config.in.or1k"
  385. endif
  386. if BR2_powerpc || BR2_powerpc64 || BR2_powerpc64le
  387. source "arch/Config.in.powerpc"
  388. endif
  389. if BR2_riscv
  390. source "arch/Config.in.riscv"
  391. endif
  392. if BR2_s390x
  393. source "arch/Config.in.s390x"
  394. endif
  395. if BR2_sh
  396. source "arch/Config.in.sh"
  397. endif
  398. if BR2_sparc || BR2_sparc64
  399. source "arch/Config.in.sparc"
  400. endif
  401. if BR2_i386 || BR2_x86_64
  402. source "arch/Config.in.x86"
  403. endif
  404. if BR2_xtensa
  405. source "arch/Config.in.xtensa"
  406. endif
  407. endmenu # Target options