spi_flash.c 13 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /**
  3. ******************************************************************************
  4. * @file spi_flash.c
  5. * @author StarFive Technology
  6. * @version V1.0
  7. * @date 07/24/2020
  8. * @brief
  9. ******************************************************************************
  10. * @copy
  11. *
  12. * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  13. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  14. * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
  15. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  16. * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  17. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  18. *
  19. * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
  20. */
  21. #include <comdef.h>
  22. #include "spi.h"
  23. #include "spi_flash.h"
  24. #include "spi_flash_internal.h"
  25. #include <cadence_qspi.h>
  26. static int qe_enable = 0;
  27. static void spi_flash_addr(u32 addr, u8 *cmd)
  28. {
  29. /* cmd[0] is actual command */
  30. cmd[1] = (addr & 0x00FF0000) >> 16;
  31. cmd[2] = (addr & 0x0000FF00) >> 8;
  32. cmd[3] = (addr & 0x000000FF) >> 0;
  33. }
  34. static int spi_flash_read_write(struct spi_slave *spi,
  35. u8 *cmd, u32 cmd_len,
  36. u8 *data_out, u8 *data_in,
  37. u32 data_len)
  38. {
  39. unsigned long flags = SPI_XFER_BEGIN;
  40. int ret;
  41. if (data_len == 0)
  42. flags |= SPI_XFER_END;
  43. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  44. if (ret)
  45. {
  46. //uart_printf("SF: Failed to send command (%d bytes): %d\n",
  47. //cmd_len, ret);
  48. }
  49. else if (data_len != 0)
  50. {
  51. ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END, SPI_DATAMODE_8);
  52. }
  53. return ret;
  54. }
  55. int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, u32 len)
  56. {
  57. return spi_flash_cmd_read(spi, &cmd, 1, response, len);
  58. }
  59. int spi_flash_cmd_read(struct spi_slave *spi, u8 *cmd,
  60. u32 cmd_len, void *data, u32 data_len)
  61. {
  62. return spi_flash_read_write(spi, cmd, cmd_len, NULL, data, data_len);
  63. }
  64. int spi_flash_cmd_write(struct spi_slave *spi, u8 *cmd, u32 cmd_len,
  65. void *data, u32 data_len)
  66. {
  67. return spi_flash_read_write(spi, cmd, cmd_len, data, NULL, data_len);
  68. }
  69. int spi_flash_cmd_write_enable(struct spi_flash *flash)
  70. {
  71. return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, (void*)NULL, 0);
  72. }
  73. int spi_flash_cmd_write_status_enable(struct spi_flash *flash)
  74. {
  75. return spi_flash_cmd(flash->spi, CMD_STATUS_ENABLE, (void*)NULL, 0);
  76. }
  77. int spi_flash_cmd_write_disable(struct spi_slave *spi)
  78. {
  79. return spi_flash_cmd(spi, CMD_WRITE_DISABLE, (void*)NULL, 0);
  80. }
  81. int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *cmd, u32 cmd_len, u8 *status)
  82. {
  83. struct spi_slave *spi = flash->spi;
  84. int ret;
  85. ret = spi_xfer(spi, 8*cmd_len, cmd, NULL, SPI_XFER_BEGIN, SPI_DATAMODE_8);
  86. if (ret) {
  87. //uart_printf("SF: Failed to send command %x: %d\n", (unsigned int)cmd, ret);
  88. return ret;
  89. }
  90. ret = spi_xfer(spi, 8*1, NULL, status, SPI_XFER_END, SPI_DATAMODE_8);
  91. //uart_printf("status = 0x%x\r\n", status[0]);
  92. if (ret)
  93. return ret;
  94. return 0;
  95. }
  96. int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout,
  97. u8 cmd, u8 poll_bit)
  98. {
  99. int ret;
  100. u8 status;
  101. u32 status_tmp = 0;
  102. u32 timebase_1 = 0;
  103. do {
  104. ret = spi_flash_cmd_read_status(flash, &cmd, 1, &status);
  105. //uart_printf("cmd = 0x%x, status = 0x%x\r\n", cmd, status);
  106. if (ret)
  107. return ret;
  108. if ((status & poll_bit) == 0)
  109. break;
  110. timebase_1++;//libo
  111. } while (timebase_1 < timeout);
  112. if ((status & poll_bit) == 0)
  113. return 0;
  114. /* Timed out */
  115. //uart_printf("SF: time out!\r\n");
  116. return -1;
  117. }
  118. int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
  119. {
  120. return spi_flash_cmd_poll_bit(flash, timeout,
  121. CMD_READ_STATUS, STATUS_WIP);
  122. }
  123. int spi_flash_cmd_poll_enable(struct spi_flash *flash, unsigned long timeout,
  124. u8 cmd, u32 poll_bit)
  125. {
  126. int ret;
  127. u8 status;
  128. u32 status_tmp = 0;
  129. u32 timebase_1 = 0;
  130. do {
  131. ret = spi_flash_cmd_read_status(flash, &cmd, 1, &status);
  132. if (ret)
  133. return ret;
  134. //uart_printf("read status = 0x%x\r\n", status);
  135. if ((status & poll_bit) == 1)
  136. break;
  137. timebase_1++;
  138. } while (timebase_1 < timeout);
  139. /* Timed out */
  140. //uart_printf("SF: time out!\r\n");
  141. return 0;
  142. }
  143. int spi_flash_cmd_status_poll_enable(struct spi_flash *flash, unsigned long timeout,
  144. u8 cmd, u32 poll_bit)
  145. {
  146. int ret;
  147. u8 status;
  148. u32 status_tmp = 0;
  149. u32 timebase_1 = 0;
  150. do {
  151. ret = spi_flash_cmd_read_status(flash, &cmd, 1, &status);
  152. if (ret)
  153. return ret;
  154. //uart_printf("read status = 0x%x\r\n", status);
  155. if ((status & poll_bit) == 0x2)
  156. break;
  157. timebase_1++;
  158. } while (timebase_1 < timeout);
  159. /* Timed out */
  160. //uart_printf("SF: time out!\r\n");
  161. return 0;
  162. }
  163. int spi_flash_cmd_wait_enable(struct spi_flash *flash, unsigned long timeout)
  164. {
  165. return spi_flash_cmd_status_poll_enable(flash, timeout,
  166. CMD_READ_STATUS, FLASH_ENABLE);
  167. }
  168. int spi_flash_write_status(struct spi_flash *flash, u8 *cmd, unsigned int cmd_len,void *data, unsigned int data_len)
  169. {
  170. int ret;
  171. ret = spi_flash_cmd_write_enable(flash);
  172. if (ret) {
  173. // uart_printf("SF: Unable to claim SPI bus\n");
  174. return ret;
  175. }
  176. ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, data, data_len);
  177. if (ret < 0) {
  178. //uart_printf("SF: write failed\n");
  179. return ret;
  180. }
  181. ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
  182. if (ret < 0) {
  183. //uart_printf("SF: wait ready failed\n");
  184. return ret;
  185. }
  186. ret = spi_flash_cmd_write_disable(flash->spi);
  187. if (ret < 0) {
  188. //uart_printf("SF: disable write failed\n");
  189. return ret;
  190. }
  191. return 0;
  192. }
  193. #ifdef ISP_BOARD
  194. int spi_flash_write_status_bit(struct spi_flash *flash, u8 status0, u8 bit0)
  195. {
  196. u8 status[2];
  197. int ret = 0;
  198. status[0] = CMD_WRITE_STATUS;
  199. status[1] = status0|bit0;
  200. spi_flash_write_status(flash, &status[0], 1, &status[1], 1);
  201. if (bit0)
  202. {
  203. ret &= spi_flash_cmd_poll_bit(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT, CMD_READ_STATUS, ~bit0);
  204. }
  205. return ret;
  206. delay(1000);
  207. return ret;
  208. }
  209. int spi_flash_protect(struct spi_flash *flash)
  210. {
  211. /* set PB=0 all can write */
  212. return spi_flash_write_status_bit(flash, 0x00, 0);
  213. }
  214. #else
  215. int spi_flash_write_status_bit(struct spi_flash *flash, u8 status1, u8 status2, u8 bit1, u8 bit2)
  216. {
  217. u8 status[3];
  218. int ret = 0;
  219. status[0] = CMD_WRITE_STATUS;
  220. status[1] = status1|bit1;
  221. status[2] = status2|bit2;
  222. spi_flash_write_status(flash, &status[0], 1, &status[1], 2);
  223. if (bit1)
  224. {
  225. ret &= spi_flash_cmd_poll_bit(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT, CMD_READ_STATUS, ~bit1);
  226. }
  227. if (bit2)
  228. {
  229. ret &= spi_flash_cmd_poll_bit(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT, CMD_READ_STATUS1, ~bit2);
  230. }
  231. return ret;
  232. delay(1000);
  233. return ret;
  234. }
  235. int spi_flash_protect(struct spi_flash *flash)
  236. {
  237. /* set PB=0 all can write */
  238. return spi_flash_write_status_bit(flash, 0x00, 0x00, 0, 0);
  239. }
  240. #endif
  241. int spi_flash_cmd_erase(struct spi_flash *flash, u8 erase_cmd,
  242. u32 offset, u32 len)
  243. {
  244. u32 start, end, erase_size;
  245. int ret;
  246. u8 cmd[4];
  247. //uart_printf("spi_flash_cmd_erase \r\n");
  248. switch(erase_cmd){
  249. case CMD_W25_SE:
  250. erase_size = flash->sector_size;
  251. break;
  252. case CMD_W25_BE_32:
  253. erase_size = flash->sector_size * 8;
  254. break;
  255. case CMD_W25_BE:
  256. erase_size = flash->block_size;
  257. break;
  258. default:
  259. erase_size = flash->sector_size;
  260. break;
  261. }
  262. if (offset % erase_size || len % erase_size) {
  263. //uart_printf("SF: Erase offset/length not multiple of erase size\n");
  264. return -1;
  265. }
  266. // spi_flash_cmd_write_status_enable(flash);
  267. spi_flash_protect(flash);
  268. cmd[0] = erase_cmd;
  269. start = offset;
  270. end = start + len;
  271. while (offset < end)
  272. {
  273. spi_flash_addr(offset, cmd);
  274. offset += erase_size;
  275. //uart_printf("SF: erase %x %x %x %x (%x)\n", cmd[0], cmd[1],
  276. // cmd[2], cmd[3], offset);
  277. ret = spi_flash_cmd_write_enable(flash);
  278. if (ret)
  279. goto out;
  280. //spi_flash_cmd_wait_enable(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
  281. ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), NULL, 0);
  282. if (ret)
  283. goto out;
  284. ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
  285. if (ret)
  286. goto out;
  287. ret = spi_flash_cmd_write_disable(flash->spi);
  288. if (ret)
  289. goto out;
  290. }
  291. //uart_printf("SF: Successfully erased %d bytes @ %x\n", len , start);
  292. out:
  293. return ret;
  294. }
  295. /* mode is 4, 32, 64*/
  296. int spi_flash_erase_mode(struct spi_flash *flash, u32 offset, u32 len, u32 mode)
  297. {
  298. int ret = 0;
  299. switch (mode)
  300. {
  301. case 4:
  302. ret = spi_flash_cmd_erase(flash, CMD_W25_SE, offset, len);
  303. break;
  304. case 32:
  305. ret = spi_flash_cmd_erase(flash, CMD_W25_BE_32, offset, len);
  306. break;
  307. case 64:
  308. ret = spi_flash_cmd_erase(flash, CMD_W25_BE, offset, len);
  309. break;
  310. default:
  311. ret = spi_flash_cmd_erase(flash, CMD_W25_BE, offset, len);
  312. break;
  313. }
  314. return ret;
  315. }
  316. int spi_flash_cmd_write_mode(struct spi_flash *flash, u32 offset,u32 len, void *buf, u32 mode)
  317. {
  318. struct spi_slave *spi = flash->spi;
  319. unsigned long byte_addr, page_size;
  320. u32 write_addr;
  321. u32 chunk_len, actual;
  322. int ret;
  323. u8 cmd[4];
  324. int write_data = 1;
  325. unsigned long flags = SPI_XFER_BEGIN;
  326. page_size = flash->page_size;
  327. switch (mode){
  328. case 1:
  329. cmd[0] = CMD_PAGE_PROGRAM;
  330. qe_enable = 0;
  331. break;
  332. case 4:
  333. cmd[0] = CMD_PAGE_PROGRAM_QUAD;
  334. #ifdef ISP_BOARD
  335. spi_flash_write_status_bit(flash, 0x00, STATUS_QE);
  336. #else
  337. spi_flash_write_status_bit(flash, 0x00, 0x00, 0, STATUS_QE);
  338. #endif
  339. break;
  340. default:
  341. cmd[0] = CMD_PAGE_PROGRAM;
  342. break;
  343. }
  344. for (actual = 0; actual < len; actual += chunk_len)
  345. {
  346. write_addr = offset;
  347. byte_addr = offset % page_size;
  348. chunk_len = min(len - actual, page_size - byte_addr);
  349. spi_flash_addr(write_addr, cmd);
  350. ret = spi_flash_cmd_write_enable(flash);
  351. if (ret < 0) {
  352. //uart_printf("SF: enabling write failed\n");
  353. break;
  354. }
  355. spi_flash_cmd_wait_enable(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
  356. #if 1
  357. if (mode == 1)
  358. {
  359. ret = spi_flash_cmd_write(flash->spi, cmd, 4,
  360. (unsigned char*)buf + actual, chunk_len);
  361. if (ret < 0) {
  362. //uart_printf("SF: write failed\n");
  363. break;
  364. }
  365. }
  366. #endif
  367. if (mode == 4)
  368. {
  369. flags = SPI_XFER_BEGIN;
  370. if (chunk_len == 0)
  371. flags |= SPI_XFER_END;
  372. ret = spi_xfer(spi, 4 * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  373. if (ret < 0)
  374. {
  375. //uart_printf("xfer failed\n");
  376. return ret;
  377. }
  378. else if (chunk_len != 0)
  379. {
  380. //qspi_mode_ctl(SPI4_DATEMODE_4);
  381. ret = spi_xfer(spi, chunk_len * 8, (unsigned char*)buf + actual, NULL, SPI_XFER_END, SPI_DATAMODE_8);
  382. }
  383. }
  384. //qspi_mode_ctl(SPI4_DATEMODE_0);
  385. ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
  386. if (ret < 0)
  387. {
  388. //uart_printf("SF: spi_flash_cmd_wait_ready failed\n");
  389. break;
  390. }
  391. ret = spi_flash_cmd_write_disable(flash->spi);
  392. if (ret < 0)
  393. {
  394. //uart_printf("SF: disable write failed\n");
  395. break;
  396. }
  397. offset += chunk_len;
  398. //uart_printf("SF: program %s %d bytes @ %d\n", ret ? "failure" : "success", len, offset);
  399. }
  400. return ret;
  401. }
  402. int spi_flash_read_common(struct spi_flash *flash, u8 *cmd,
  403. u32 cmd_len, void *data, u32 data_len)
  404. {
  405. struct spi_slave *spi = flash->spi;
  406. int ret;
  407. ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
  408. return ret;
  409. }
  410. int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
  411. u32 len, void *data, u32 mode)
  412. {
  413. u8 cmd[5];
  414. cmd[0] = CMD_READ_ARRAY_FAST;
  415. spi_flash_addr(offset, cmd);
  416. cmd[4] = 0x00;
  417. return spi_flash_read_common(flash, cmd, sizeof(cmd), data, len);
  418. }
  419. int spi_flash_read_mode(struct spi_flash *flash, u32 offset,
  420. u32 len, void *data, u32 mode)
  421. {
  422. struct spi_slave *spi = flash->spi;
  423. u8 cmd[5];
  424. int ret;
  425. int write_data = 0;
  426. u8 status[2] = {2};
  427. int i = 0;
  428. switch (mode)
  429. {
  430. case 1:
  431. cmd[0] = CMD_READ_ARRAY_FAST;
  432. qe_enable = 0;
  433. break;
  434. case 2:
  435. cmd[0] = CMD_READ_ARRAY_DUAL;
  436. break;
  437. case 4:
  438. #ifdef ISP_BOARD
  439. cmd[0] = CMD_READ_ARRAY_LEGACY;
  440. //spi_flash_cmd_write_reg_mode(flash, flash_reg_offset, 1, flash_reg);
  441. //flash_reg[0] = 0;
  442. //spi_flash_cmd_write_reg_mode(flash, flash_reg_offset, 1, flash_reg);
  443. //spi_flash_read_reg_mode(flash, flash_reg_offset, 1, flash_reg);
  444. #else
  445. cmd[0] = CMD_READ_ARRAY_QUAD;
  446. if(qe_enable == 0)
  447. {
  448. spi_flash_write_status_bit(flash, 0x00, 0x00, 0, STATUS_QE);;
  449. qe_enable = 1;
  450. }
  451. #endif
  452. break;
  453. default:
  454. cmd[0] = CMD_READ_ARRAY_FAST;
  455. break;
  456. }
  457. //spi_flash_cmd_poll_bit(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT, CMD_READ_STATUS1, ~STATUS_QE);
  458. spi_flash_addr(offset, cmd);
  459. cmd[4] = 0x00;
  460. ret = spi_xfer(spi, 5*8, cmd, NULL, SPI_XFER_BEGIN, SPI_DATAMODE_8);
  461. if (ret < 0)
  462. {
  463. //uart_printf("xfer failed\n");
  464. return ret;
  465. }
  466. ret = spi_xfer(spi, len*8, NULL, data, SPI_XFER_END, SPI_DATAMODE_8);
  467. if (ret < 0)
  468. {
  469. //uart_printf("xfer failed\n");
  470. return ret;
  471. }
  472. return 0;
  473. }