spi_flash.c 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /**
  3. ******************************************************************************
  4. * @file spi_flash.c
  5. * @author StarFive Technology
  6. * @version V1.0
  7. * @date 06/25/2020
  8. * @brief
  9. ******************************************************************************
  10. * @copy
  11. *
  12. * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  13. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  14. * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
  15. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  16. * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  17. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  18. *
  19. * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
  20. */
  21. #include <comdef.h>
  22. #include "spi.h"
  23. #include "spi_flash.h"
  24. #include "spi_flash_internal.h"
  25. #include <cadence_qspi.h>
  26. static void spi_flash_addr(u32 addr, u8 *cmd)
  27. {
  28. /* cmd[0] is actual command */
  29. cmd[1] = (addr & 0x00FF0000) >> 16;
  30. cmd[2] = (addr & 0x0000FF00) >> 8;
  31. cmd[3] = (addr & 0x000000FF) >> 0;
  32. }
  33. static int spi_flash_read_write(struct spi_slave *spi,
  34. u8 *cmd, u32 cmd_len,
  35. u8 *data_out, u8 *data_in,
  36. u32 data_len)
  37. {
  38. unsigned long flags = SPI_XFER_BEGIN;
  39. int ret;
  40. if (data_len == 0)
  41. flags |= SPI_XFER_END;
  42. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  43. if (ret)
  44. {
  45. //uart_printf("SF: Failed to send command (%d bytes): %d\n",
  46. //cmd_len, ret);
  47. }
  48. else if (data_len != 0)
  49. {
  50. ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END, SPI_DATAMODE_8);
  51. }
  52. return ret;
  53. }
  54. int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, u32 len)
  55. {
  56. return spi_flash_cmd_read(spi, &cmd, 1, response, len);
  57. }
  58. int spi_flash_cmd_read(struct spi_slave *spi, u8 *cmd,
  59. u32 cmd_len, void *data, u32 data_len)
  60. {
  61. return spi_flash_read_write(spi, cmd, cmd_len, NULL, data, data_len);
  62. }
  63. int spi_flash_cmd_write(struct spi_slave *spi, u8 *cmd, u32 cmd_len,
  64. void *data, u32 data_len)
  65. {
  66. return spi_flash_read_write(spi, cmd, cmd_len, data, NULL, data_len);
  67. }
  68. int spi_flash_cmd_write_enable(struct spi_flash *flash)
  69. {
  70. return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, (void*)NULL, 0);
  71. }
  72. int spi_flash_cmd_write_status_enable(struct spi_flash *flash)
  73. {
  74. return spi_flash_cmd(flash->spi, CMD_STATUS_ENABLE, (void*)NULL, 0);
  75. }
  76. int spi_flash_cmd_write_disable(struct spi_slave *spi)
  77. {
  78. return spi_flash_cmd(spi, CMD_WRITE_DISABLE, (void*)NULL, 0);
  79. }
  80. int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *cmd, u32 cmd_len, u8 *status)
  81. {
  82. struct spi_slave *spi = flash->spi;
  83. int ret;
  84. ret = spi_xfer(spi, 8*cmd_len, cmd, NULL, SPI_XFER_BEGIN, SPI_DATAMODE_8);
  85. if (ret) {
  86. //uart_printf("SF: Failed to send command %x: %d\n", (unsigned int)cmd, ret);
  87. return ret;
  88. }
  89. ret = spi_xfer(spi, 8*1, NULL, status, SPI_XFER_END, SPI_DATAMODE_8);
  90. //uart_printf("status = 0x%x\r\n", status[0]);
  91. if (ret)
  92. return ret;
  93. return 0;
  94. }
  95. int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout,
  96. u8 cmd, u8 poll_bit)
  97. {
  98. int ret;
  99. u8 status;
  100. u32 status_tmp = 0;
  101. u32 timebase_1 = 0;
  102. do {
  103. ret = spi_flash_cmd_read_status(flash, &cmd, 1, &status);
  104. //uart_printf("cmd = 0x%x, status = 0x%x\r\n", cmd, status);
  105. if (ret)
  106. return ret;
  107. if ((status & poll_bit) == 0)
  108. break;
  109. timebase_1++;//libo
  110. } while (timebase_1 < timeout);
  111. if ((status & poll_bit) == 0)
  112. return 0;
  113. /* Timed out */
  114. //uart_printf("SF: time out!\r\n");
  115. return -1;
  116. }
  117. int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
  118. {
  119. return spi_flash_cmd_poll_bit(flash, timeout,
  120. CMD_READ_STATUS, STATUS_WIP);
  121. }
  122. int spi_flash_cmd_poll_enable(struct spi_flash *flash, unsigned long timeout,
  123. u8 cmd, u32 poll_bit)
  124. {
  125. int ret;
  126. u8 status;
  127. u32 status_tmp = 0;
  128. u32 timebase_1 = 0;
  129. do {
  130. ret = spi_flash_cmd_read_status(flash, &cmd, 1, &status);
  131. if (ret)
  132. return ret;
  133. //uart_printf("read status = 0x%x\r\n", status);
  134. if ((status & poll_bit) == 1)
  135. break;
  136. timebase_1++;
  137. } while (timebase_1 < timeout);
  138. /* Timed out */
  139. //uart_printf("SF: time out!\r\n");
  140. return 0;
  141. }
  142. int spi_flash_cmd_status_poll_enable(struct spi_flash *flash, unsigned long timeout,
  143. u8 cmd, u32 poll_bit)
  144. {
  145. int ret;
  146. u8 status;
  147. u32 status_tmp = 0;
  148. u32 timebase_1 = 0;
  149. do {
  150. ret = spi_flash_cmd_read_status(flash, &cmd, 1, &status);
  151. if (ret)
  152. return ret;
  153. //uart_printf("read status = 0x%x\r\n", status);
  154. if ((status & poll_bit) == 0x2)
  155. break;
  156. timebase_1++;
  157. } while (timebase_1 < timeout);
  158. /* Timed out */
  159. //uart_printf("SF: time out!\r\n");
  160. return 0;
  161. }
  162. int spi_flash_cmd_wait_enable(struct spi_flash *flash, unsigned long timeout)
  163. {
  164. return spi_flash_cmd_status_poll_enable(flash, timeout,
  165. CMD_READ_STATUS, FLASH_ENABLE);
  166. }
  167. int spi_flash_write_status(struct spi_flash *flash, u8 *cmd, unsigned int cmd_len,void *data, unsigned int data_len)
  168. {
  169. int ret;
  170. ret = spi_flash_cmd_write_enable(flash);
  171. if (ret) {
  172. // uart_printf("SF: Unable to claim SPI bus\n");
  173. return ret;
  174. }
  175. ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, data, data_len);
  176. if (ret < 0) {
  177. //uart_printf("SF: write failed\n");
  178. return ret;
  179. }
  180. ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
  181. if (ret < 0) {
  182. //uart_printf("SF: wait ready failed\n");
  183. return ret;
  184. }
  185. ret = spi_flash_cmd_write_disable(flash->spi);
  186. if (ret < 0) {
  187. //uart_printf("SF: disable write failed\n");
  188. return ret;
  189. }
  190. return 0;
  191. }
  192. #ifdef ISP_BOARD
  193. int spi_flash_write_status_bit(struct spi_flash *flash, u8 status0, u8 bit0)
  194. {
  195. u8 status[2];
  196. int ret = 0;
  197. status[0] = CMD_WRITE_STATUS;
  198. status[1] = status0|bit0;
  199. spi_flash_write_status(flash, &status[0], 1, &status[1], 1);
  200. if (bit0)
  201. {
  202. ret &= spi_flash_cmd_poll_bit(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT, CMD_READ_STATUS, ~bit0);
  203. }
  204. return ret;
  205. delay(1000);
  206. return ret;
  207. }
  208. int spi_flash_protect(struct spi_flash *flash)
  209. {
  210. /* set PB=0 all can write */
  211. return spi_flash_write_status_bit(flash, 0x00, 0);
  212. }
  213. #else
  214. int spi_flash_write_status_bit(struct spi_flash *flash, u8 status1, u8 status2, u8 bit1, u8 bit2)
  215. {
  216. u8 status[3];
  217. int ret = 0;
  218. status[0] = CMD_WRITE_STATUS;
  219. status[1] = status1|bit1;
  220. status[2] = status2|bit2;
  221. spi_flash_write_status(flash, &status[0], 1, &status[1], 2);
  222. if (bit1)
  223. {
  224. ret &= spi_flash_cmd_poll_bit(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT, CMD_READ_STATUS, ~bit1);
  225. }
  226. if (bit2)
  227. {
  228. ret &= spi_flash_cmd_poll_bit(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT, CMD_READ_STATUS1, ~bit2);
  229. }
  230. return ret;
  231. delay(1000);
  232. return ret;
  233. }
  234. int spi_flash_protect(struct spi_flash *flash)
  235. {
  236. /* set PB=0 all can write */
  237. return spi_flash_write_status_bit(flash, 0x00, 0x00, 0, 0);
  238. }
  239. #endif
  240. int spi_flash_cmd_erase(struct spi_flash *flash, u8 erase_cmd,
  241. u32 offset, u32 len)
  242. {
  243. u32 start, end, erase_size;
  244. int ret;
  245. u8 cmd[4];
  246. //uart_printf("spi_flash_cmd_erase \r\n");
  247. switch(erase_cmd){
  248. case CMD_W25_SE:
  249. erase_size = flash->sector_size;
  250. break;
  251. case CMD_W25_BE_32:
  252. erase_size = flash->sector_size * 8;
  253. break;
  254. case CMD_W25_BE:
  255. erase_size = flash->block_size;
  256. break;
  257. default:
  258. erase_size = flash->sector_size;
  259. break;
  260. }
  261. if (offset % erase_size || len % erase_size) {
  262. //uart_printf("SF: Erase offset/length not multiple of erase size\n");
  263. return -1;
  264. }
  265. // spi_flash_cmd_write_status_enable(flash);
  266. spi_flash_protect(flash);
  267. cmd[0] = erase_cmd;
  268. start = offset;
  269. end = start + len;
  270. while (offset < end)
  271. {
  272. spi_flash_addr(offset, cmd);
  273. offset += erase_size;
  274. //uart_printf("SF: erase %x %x %x %x (%x)\n", cmd[0], cmd[1],
  275. // cmd[2], cmd[3], offset);
  276. ret = spi_flash_cmd_write_enable(flash);
  277. if (ret)
  278. goto out;
  279. //spi_flash_cmd_wait_enable(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
  280. ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), NULL, 0);
  281. if (ret)
  282. goto out;
  283. ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
  284. if (ret)
  285. goto out;
  286. ret = spi_flash_cmd_write_disable(flash->spi);
  287. if (ret)
  288. goto out;
  289. }
  290. //uart_printf("SF: Successfully erased %d bytes @ %x\n", len , start);
  291. out:
  292. return ret;
  293. }
  294. /* mode is 4, 32, 64*/
  295. int spi_flash_erase_mode(struct spi_flash *flash, u32 offset, u32 len, u32 mode)
  296. {
  297. int ret = 0;
  298. switch (mode)
  299. {
  300. case 4:
  301. ret = spi_flash_cmd_erase(flash, CMD_W25_SE, offset, len);
  302. break;
  303. case 32:
  304. ret = spi_flash_cmd_erase(flash, CMD_W25_BE_32, offset, len);
  305. break;
  306. case 64:
  307. ret = spi_flash_cmd_erase(flash, CMD_W25_BE, offset, len);
  308. break;
  309. default:
  310. ret = spi_flash_cmd_erase(flash, CMD_W25_BE, offset, len);
  311. break;
  312. }
  313. return ret;
  314. }
  315. int spi_flash_cmd_write_mode(struct spi_flash *flash, u32 offset,u32 len, void *buf, u32 mode)
  316. {
  317. struct spi_slave *spi = flash->spi;
  318. unsigned long byte_addr, page_size;
  319. u32 write_addr;
  320. u32 chunk_len, actual;
  321. int ret;
  322. u8 cmd[4];
  323. int write_data = 1;
  324. unsigned long flags = SPI_XFER_BEGIN;
  325. page_size = flash->page_size;
  326. switch (mode){
  327. case 1:
  328. cmd[0] = CMD_PAGE_PROGRAM;
  329. break;
  330. case 4:
  331. cmd[0] = CMD_PAGE_PROGRAM_QUAD;
  332. #ifdef ISP_BOARD
  333. spi_flash_write_status_bit(flash, 0x00, STATUS_QE);
  334. #else
  335. spi_flash_write_status_bit(flash, 0x00, 0x00, 0, STATUS_QE);
  336. #endif
  337. break;
  338. default:
  339. cmd[0] = CMD_PAGE_PROGRAM;
  340. break;
  341. }
  342. for (actual = 0; actual < len; actual += chunk_len)
  343. {
  344. write_addr = offset;
  345. byte_addr = offset % page_size;
  346. chunk_len = min(len - actual, page_size - byte_addr);
  347. spi_flash_addr(write_addr, cmd);
  348. ret = spi_flash_cmd_write_enable(flash);
  349. if (ret < 0) {
  350. //uart_printf("SF: enabling write failed\n");
  351. break;
  352. }
  353. spi_flash_cmd_wait_enable(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
  354. #if 1
  355. if (mode == 1)
  356. {
  357. ret = spi_flash_cmd_write(flash->spi, cmd, 4,
  358. (unsigned char*)buf + actual, chunk_len);
  359. if (ret < 0) {
  360. //uart_printf("SF: write failed\n");
  361. break;
  362. }
  363. }
  364. #endif
  365. if (mode == 4)
  366. {
  367. flags = SPI_XFER_BEGIN;
  368. if (chunk_len == 0)
  369. flags |= SPI_XFER_END;
  370. ret = spi_xfer(spi, 4 * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  371. if (ret < 0)
  372. {
  373. //uart_printf("xfer failed\n");
  374. return ret;
  375. }
  376. else if (chunk_len != 0)
  377. {
  378. //qspi_mode_ctl(SPI4_DATEMODE_4);
  379. ret = spi_xfer(spi, chunk_len * 8, (unsigned char*)buf + actual, NULL, SPI_XFER_END, SPI_DATAMODE_8);
  380. }
  381. }
  382. //qspi_mode_ctl(SPI4_DATEMODE_0);
  383. ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
  384. if (ret < 0)
  385. {
  386. //uart_printf("SF: spi_flash_cmd_wait_ready failed\n");
  387. break;
  388. }
  389. ret = spi_flash_cmd_write_disable(flash->spi);
  390. if (ret < 0)
  391. {
  392. //uart_printf("SF: disable write failed\n");
  393. break;
  394. }
  395. offset += chunk_len;
  396. //uart_printf("SF: program %s %d bytes @ %d\n", ret ? "failure" : "success", len, offset);
  397. }
  398. return ret;
  399. }
  400. int spi_flash_read_common(struct spi_flash *flash, u8 *cmd,
  401. u32 cmd_len, void *data, u32 data_len)
  402. {
  403. struct spi_slave *spi = flash->spi;
  404. int ret;
  405. ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
  406. return ret;
  407. }
  408. int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
  409. u32 len, void *data, u32 mode)
  410. {
  411. u8 cmd[5];
  412. cmd[0] = CMD_READ_ARRAY_FAST;
  413. spi_flash_addr(offset, cmd);
  414. cmd[4] = 0x00;
  415. return spi_flash_read_common(flash, cmd, sizeof(cmd), data, len);
  416. }
  417. int spi_flash_read_mode(struct spi_flash *flash, u32 offset,
  418. u32 len, void *data, u32 mode)
  419. {
  420. struct spi_slave *spi = flash->spi;
  421. u8 cmd[5];
  422. int ret;
  423. int write_data = 0;
  424. u8 status[2] = {2};
  425. int i = 0;
  426. switch (mode)
  427. {
  428. case 1:
  429. cmd[0] = CMD_READ_ARRAY_FAST;
  430. break;
  431. case 2:
  432. cmd[0] = CMD_READ_ARRAY_DUAL;
  433. break;
  434. case 4:
  435. #ifdef ISP_BOARD
  436. cmd[0] = CMD_READ_ARRAY_LEGACY;
  437. //spi_flash_cmd_write_reg_mode(flash, flash_reg_offset, 1, flash_reg);
  438. //flash_reg[0] = 0;
  439. //spi_flash_cmd_write_reg_mode(flash, flash_reg_offset, 1, flash_reg);
  440. //spi_flash_read_reg_mode(flash, flash_reg_offset, 1, flash_reg);
  441. #else
  442. cmd[0] = CMD_READ_ARRAY_QUAD;
  443. spi_flash_write_status_bit(flash, 0x00, 0x00, 0, STATUS_QE);
  444. #endif
  445. break;
  446. default:
  447. cmd[0] = CMD_READ_ARRAY_FAST;
  448. break;
  449. }
  450. //spi_flash_cmd_poll_bit(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT, CMD_READ_STATUS1, ~STATUS_QE);
  451. spi_flash_addr(offset, cmd);
  452. cmd[4] = 0x00;
  453. ret = spi_xfer(spi, 5*8, cmd, NULL, SPI_XFER_BEGIN, SPI_DATAMODE_8);
  454. if (ret < 0)
  455. {
  456. //uart_printf("xfer failed\n");
  457. return ret;
  458. }
  459. ret = spi_xfer(spi, len*8, NULL, data, SPI_XFER_END, SPI_DATAMODE_8);
  460. if (ret < 0)
  461. {
  462. //uart_printf("xfer failed\n");
  463. return ret;
  464. }
  465. return 0;
  466. }