cadence_qspi.h 2.5 KB

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  1. /*
  2. * Copyright (C) 2012
  3. * Altera Corporation <www.altera.com>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #ifndef __CADENCE_QSPI_H__
  8. #define __CADENCE_QSPI_H__
  9. #define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0)
  10. #define CQSPI_NO_DECODER_MAX_CS 4
  11. #define CQSPI_DECODER_MAX_CS 16
  12. #define CQSPI_READ_CAPTURE_MAX_DELAY 16
  13. struct cadence_spi_platdata {
  14. unsigned int max_hz;
  15. void *regbase;
  16. void *ahbbase;
  17. u32 int_num;
  18. u32 page_size;
  19. u32 block_size;
  20. u32 tshsl_ns;
  21. u32 tsd2d_ns;
  22. u32 tchsh_ns;
  23. u32 tslch_ns;
  24. u32 sram_size;
  25. u32 bit_mode;
  26. };
  27. struct cadence_spi_priv {
  28. void *regbase;
  29. void *ahbbase;
  30. unsigned int cmd_len;
  31. u8 cmd_buf[32];
  32. unsigned int data_len;
  33. int qspi_is_init;
  34. unsigned int qspi_calibrated_hz;
  35. unsigned int qspi_calibrated_cs;
  36. unsigned int previous_hz;
  37. };
  38. /* Functions call declaration */
  39. void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat);
  40. void cadence_qspi_apb_controller_enable(void * reg_base_addr);
  41. void cadence_qspi_apb_controller_disable(void * reg_base_addr);
  42. int cadence_qspi_apb_command_read(void * reg_base_addr,
  43. unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, u8 *rxbuf);
  44. int cadence_qspi_apb_command_write(void * reg_base_addr,
  45. unsigned int cmdlen, const u8 *cmdbuf,
  46. unsigned int txlen, const u8 *txbuf);
  47. int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
  48. unsigned int cmdlen, const u8 *cmdbuf);
  49. int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
  50. unsigned int rxlen, u8 *rxbuf);
  51. int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
  52. unsigned int cmdlen, const u8 *cmdbuf);
  53. int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
  54. unsigned int txlen, const u8 *txbuf);
  55. void cadence_qspi_apb_chipselect(void * reg_base,
  56. unsigned int chip_select, unsigned int decoder_enable);
  57. void cadence_qspi_apb_set_clk_mode(void * reg_base_addr,
  58. unsigned int clk_pol, unsigned int clk_pha);
  59. void cadence_qspi_apb_config_baudrate_div(void * reg_base,
  60. unsigned int ref_clk_hz, unsigned int sclk_hz);
  61. void cadence_qspi_apb_delay(void * reg_base,
  62. unsigned int ref_clk, unsigned int sclk_hz,
  63. unsigned int tshsl_ns, unsigned int tsd2d_ns,
  64. unsigned int tchsh_ns, unsigned int tslch_ns);
  65. void cadence_qspi_apb_enter_xip(void * reg_base, char xip_dummy);
  66. void cadence_qspi_apb_readdata_capture(void * reg_base,
  67. unsigned int bypass, unsigned int delay);
  68. void cadence_qspi_init(unsigned int bus, u32 mode);
  69. #endif /* __CADENCE_QSPI_H__ */