cadence_qspi.c 8.1 KB

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  1. /*
  2. * Copyright (C) 2012
  3. * Altera Corporation <www.altera.com>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <comdef.h>
  8. #include <spi.h>
  9. #include <sys.h>
  10. #include <cadence_qspi.h>
  11. #include <ezGPIO_fullMux_ctrl_macro.h>
  12. #include <clkgen_ctrl_macro.h>
  13. #include <rstgen_ctrl_macro.h>
  14. struct cadence_spi_slave
  15. {
  16. struct spi_slave slave;
  17. u32 base;
  18. int irq;
  19. };
  20. struct spi_operation cadence_spi4x_func;
  21. struct cadence_spi_platdata cadence_plat;
  22. struct cadence_spi_priv spi_priv;
  23. struct cadence_spi_slave vic_spi_slave;
  24. #define CQSPI_STIG_READ 0
  25. #define CQSPI_STIG_WRITE 1
  26. #define CQSPI_INDIRECT_READ 2
  27. #define CQSPI_INDIRECT_WRITE 3
  28. #define CADENCE_QSPI_MAX_HZ QSPI_CLK
  29. #define CONFIG_CQSPI_REF_CLK QSPI_REF_CLK
  30. #define CONFIG_CQSPI_DECODER 0
  31. static int cadence_spi_write_speed(unsigned int hz)
  32. {
  33. struct cadence_spi_platdata *plat = &cadence_plat;
  34. struct cadence_spi_priv *priv = &spi_priv;
  35. cadence_qspi_apb_config_baudrate_div(priv->regbase,
  36. CONFIG_CQSPI_REF_CLK, hz);
  37. /* Reconfigure delay timing if speed is changed. */
  38. cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz,
  39. plat->tshsl_ns, plat->tsd2d_ns,
  40. plat->tchsh_ns, plat->tslch_ns);
  41. return 0;
  42. }
  43. /* Calibration sequence to determine the read data capture delay register */
  44. static int spi_calibration(unsigned int hz, unsigned int cs)
  45. {
  46. struct cadence_spi_priv *priv = &spi_priv;
  47. void * base = priv->regbase;
  48. u8 opcode_rdid = 0x9F;
  49. unsigned int idcode = 0, temp = 0;
  50. int err = 0, i, range_lo = -1, range_hi = -1;
  51. /* start with slowest clock (1 MHz) */
  52. cadence_spi_write_speed(500000);
  53. /* configure the read data capture delay register to 0 */
  54. cadence_qspi_apb_readdata_capture(base, 1, 0);
  55. /* Enable QSPI */
  56. cadence_qspi_apb_controller_enable(base);
  57. /* read the ID which will be our golden value */
  58. err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
  59. 3, (u8 *)&idcode);
  60. if (err) {
  61. //uart_printf("SF: Calibration failed (read)\n");
  62. return err;
  63. }
  64. /* use back the intended clock and find low range */
  65. cadence_spi_write_speed(hz);
  66. for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
  67. /* Disable QSPI */
  68. cadence_qspi_apb_controller_disable(base);
  69. /* reconfigure the read data capture delay register */
  70. cadence_qspi_apb_readdata_capture(base, 1, i);
  71. /* Enable back QSPI */
  72. cadence_qspi_apb_controller_enable(base);
  73. /* issue a RDID to get the ID value */
  74. err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
  75. 3, (u8 *)&temp);
  76. if (err) {
  77. //uart_printf("SF: Calibration failed (read)\n");
  78. return err;
  79. }
  80. /* search for range lo */
  81. if (range_lo == -1 && temp == idcode) {
  82. range_lo = i;
  83. continue;
  84. }
  85. /* search for range hi */
  86. if (range_lo != -1 && temp != idcode) {
  87. range_hi = i - 1;
  88. break;
  89. }
  90. range_hi = i;
  91. }
  92. if (range_lo == -1) {
  93. //uart_printf("SF: Calibration failed (low range)\n");
  94. return err;
  95. }
  96. /* Disable QSPI for subsequent initialization */
  97. cadence_qspi_apb_controller_disable(base);
  98. /* configure the final value for read data capture delay register */
  99. cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
  100. //uart_printf("SF: Read data capture delay calibrated to %i (%i - %i)\n",
  101. //(range_hi + range_lo) / 2, range_lo, range_hi);
  102. /* just to ensure we do once only when speed or chip select change */
  103. priv->qspi_calibrated_hz = hz;
  104. priv->qspi_calibrated_cs = cs;
  105. return 0;
  106. }
  107. struct spi_slave *cadence_spi4x_setup_slave(unsigned int bus, unsigned int cs,
  108. unsigned int max_hz, u32 mode, u32 fifo_width)
  109. {
  110. struct cadence_spi_slave *spi4slave;
  111. struct cadence_spi_platdata *plat = &cadence_plat;
  112. struct cadence_spi_priv *priv = &spi_priv;
  113. u32 base = 0;
  114. int err = 0;
  115. u32 clk_pol;
  116. u32 clk_pha;
  117. spi4slave = &vic_spi_slave;
  118. spi4slave->base = (void *)QSPI_BASE_ADDR;
  119. clk_pol = (mode & SPI_CPOL) ? 1 : 0;
  120. clk_pha = (mode & SPI_CPHA) ? 1 : 0;
  121. plat->regbase = (void *)QSPI_BASE_ADDR;
  122. plat->ahbbase = (void *)QSPI_BASE_AHB_ADDR;
  123. plat->max_hz = CADENCE_QSPI_MAX_HZ;
  124. /****default set, may change******/
  125. plat->tshsl_ns = 200;
  126. plat->tsd2d_ns = 255;
  127. plat->tchsh_ns = 2;
  128. plat->tslch_ns = 20;
  129. plat->sram_size = 256;
  130. plat->block_size = 16;
  131. plat->page_size = 256;
  132. priv->regbase = plat->regbase;
  133. priv->ahbbase = plat->ahbbase;
  134. /* Disable QSPI */
  135. cadence_qspi_apb_controller_disable(priv->regbase);
  136. /* Set SPI mode */
  137. cadence_qspi_apb_set_clk_mode(priv->regbase, clk_pol, clk_pha);
  138. #if 0
  139. if (!priv->qspi_is_init) {
  140. cadence_qspi_apb_controller_init(plat);
  141. priv->qspi_is_init = 1;
  142. }
  143. #endif
  144. cadence_qspi_apb_controller_init(plat);
  145. if (max_hz > plat->max_hz)
  146. max_hz = plat->max_hz;
  147. /*
  148. * Calibration required for different current SCLK speed, requested
  149. * SCLK speed or chip select
  150. */
  151. if (priv->previous_hz != max_hz ||
  152. priv->qspi_calibrated_hz != max_hz ||
  153. priv->qspi_calibrated_cs != cs) {
  154. err = spi_calibration(max_hz, cs);
  155. if (err)
  156. return NULL;
  157. /* prevent calibration run when same as previous request */
  158. priv->previous_hz = max_hz;
  159. }
  160. /* Enable QSPI */
  161. cadence_qspi_apb_controller_enable(priv->regbase);
  162. spi4slave->slave.bus = bus;
  163. spi4slave->slave.cs = cs;
  164. spi4slave->slave.bus_width= fifo_width;
  165. return &spi4slave->slave;
  166. }
  167. static int cadence_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
  168. const void *dout, void *din, unsigned long flags)
  169. {
  170. struct cadence_spi_platdata *plat = &cadence_plat;
  171. struct cadence_spi_priv *priv = &spi_priv;
  172. void * base = priv->regbase;
  173. u8 *cmd_buf = priv->cmd_buf;
  174. unsigned int data_bytes = 0;
  175. int err = 0;
  176. u32 mode = CQSPI_STIG_WRITE;
  177. if (flags & SPI_XFER_BEGIN) {
  178. /* copy command to local buffer */
  179. priv->cmd_len = bitlen / 8;
  180. sys_memcpy(cmd_buf, dout, priv->cmd_len);
  181. }
  182. if (flags == (SPI_XFER_BEGIN | SPI_XFER_END))
  183. {
  184. /* if start and end bit are set, the data bytes is 0. */
  185. data_bytes = 0;
  186. }
  187. else
  188. {
  189. data_bytes = bitlen / 8;
  190. }
  191. //uart_printf("%s: len=%d [bytes]\n", __func__, data_bytes);
  192. /* Set Chip select */
  193. cadence_qspi_apb_chipselect(base, slave->cs,
  194. CONFIG_CQSPI_DECODER);
  195. if ((flags & SPI_XFER_END) || (flags == 0)) {
  196. if (priv->cmd_len == 0) {
  197. //uart_printf("QSPI: Error, command is empty.\n");
  198. return -1;
  199. }
  200. if (din && data_bytes) {
  201. /* read */
  202. /* Use STIG if no address. */
  203. if (!CQSPI_IS_ADDR(priv->cmd_len))
  204. mode = CQSPI_STIG_READ;
  205. else
  206. mode = CQSPI_INDIRECT_READ;
  207. } else if (dout && !(flags & SPI_XFER_BEGIN)) {
  208. /* write */
  209. if (!CQSPI_IS_ADDR(priv->cmd_len))
  210. mode = CQSPI_STIG_WRITE;
  211. else
  212. mode = CQSPI_INDIRECT_WRITE;
  213. }
  214. switch (mode) {
  215. case CQSPI_STIG_READ:
  216. err = cadence_qspi_apb_command_read(
  217. base, priv->cmd_len, cmd_buf,
  218. data_bytes, din);
  219. break;
  220. case CQSPI_STIG_WRITE:
  221. err = cadence_qspi_apb_command_write(base,
  222. priv->cmd_len, cmd_buf,
  223. data_bytes, dout);
  224. break;
  225. case CQSPI_INDIRECT_READ:
  226. err = cadence_qspi_apb_indirect_read_setup(plat,
  227. priv->cmd_len, cmd_buf);
  228. if (!err) {
  229. err = cadence_qspi_apb_indirect_read_execute
  230. (plat, data_bytes, din);
  231. }
  232. break;
  233. case CQSPI_INDIRECT_WRITE:
  234. err = cadence_qspi_apb_indirect_write_setup
  235. (plat, priv->cmd_len, cmd_buf);
  236. if (!err) {
  237. err = cadence_qspi_apb_indirect_write_execute
  238. (plat, data_bytes, dout);
  239. }
  240. break;
  241. default:
  242. err = -1;
  243. break;
  244. }
  245. if (flags & SPI_XFER_END) {
  246. /* clear command buffer */
  247. sys_memset(cmd_buf, 0, sizeof(priv->cmd_buf));
  248. priv->cmd_len = 0;
  249. }
  250. }
  251. return err;
  252. }
  253. void cadence_qspi_init(unsigned int bus, u32 mode)
  254. {
  255. struct spi_operation *func;
  256. struct cadence_spi_platdata *plat = &cadence_plat;
  257. #if 0 //repeat init
  258. /******************* reset ****************/
  259. _ENABLE_CLOCK_clk_qspi_refclk_;
  260. _ENABLE_CLOCK_clk_qspi_apb_;
  261. _ENABLE_CLOCK_clk_qspi_ahb_;
  262. _ASSERT_RESET_rstgen_rstn_qspi_ahb_;
  263. _ASSERT_RESET_rstgen_rstn_qspi_core_;
  264. _ASSERT_RESET_rstgen_rstn_qspi_apb_;
  265. _CLEAR_RESET_rstgen_rstn_qspi_ahb_;
  266. _CLEAR_RESET_rstgen_rstn_qspi_core_;
  267. _CLEAR_RESET_rstgen_rstn_qspi_apb_;
  268. #endif
  269. plat->bit_mode = mode;
  270. func = &cadence_spi4x_func;
  271. func->setup_slave = cadence_spi4x_setup_slave;
  272. func->spi_xfer = cadence_spi_xfer;
  273. spi_register(bus, func);
  274. return;
  275. }