vic_module_reset_clkgen.h 4.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /**
  3. ******************************************************************************
  4. * @file vic_module_reset_clkgen.h
  5. * @author StarFive Technology
  6. * @version V1.0
  7. * @date 06/25/2020
  8. * @brief
  9. ******************************************************************************
  10. * @copy
  11. *
  12. * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  13. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  14. * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
  15. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  16. * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  17. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  18. *
  19. * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
  20. */
  21. #ifndef _SFC_VIC_MODULE_RESET_CLKGEN_H
  22. #define _SFC_VIC_MODULE_RESET_CLKGEN_H
  23. #define vic_uart0_reset_clk_gpio_isp_enable { \
  24. _ENABLE_CLOCK_clk_uart0_apb_; \
  25. _ENABLE_CLOCK_clk_uart0_core_; \
  26. _DIVIDE_CLOCK_clk_uart0_core_(8); \
  27. _CLEAR_RESET_rstgen_rstn_uart0_core_; \
  28. _CLEAR_RESET_rstgen_rstn_uart0_apb_; \
  29. SET_GPIO_uart0_pad_sin(13); \
  30. SET_GPIO_13_doen_HIGH; \
  31. SET_GPIO_12_dout_uart0_pad_sout; \
  32. SET_GPIO_12_doen_LOW; \
  33. }
  34. #define vic_uart0_reset_clk_gpio_misc_enable { \
  35. _ENABLE_CLOCK_clk_uart0_apb_; \
  36. _ENABLE_CLOCK_clk_uart0_core_; \
  37. _CLEAR_RESET_rstgen_rstn_uart0_core_; \
  38. _CLEAR_RESET_rstgen_rstn_uart0_apb_; \
  39. SET_GPIO_uart0_pad_sin(5); \
  40. SET_GPIO_5_doen_HIGH; \
  41. SET_GPIO_6_dout_uart0_pad_sout; \
  42. SET_GPIO_6_doen_LOW; \
  43. }
  44. #define vic_uart1_reset_clk_gpio_isp_enable { \
  45. _ENABLE_CLOCK_clk_uart1_apb_; \
  46. _ENABLE_CLOCK_clk_uart1_core_; \
  47. _CLEAR_RESET_rstgen_rstn_uart1_core_; \
  48. _CLEAR_RESET_rstgen_rstn_uart1_apb_; \
  49. SET_GPIO_12_dout_uart1_pad_sout; \
  50. SET_GPIO_uart1_pad_sin(13); \
  51. SET_GPIO_13_doen_HIGH; \
  52. SET_GPIO_12_doen_LOW; \
  53. }
  54. #define vic_uart1_reset_clk_gpio_misc_enable { \
  55. _ENABLE_CLOCK_clk_uart1_apb_; \
  56. _ENABLE_CLOCK_clk_uart1_core_; \
  57. _CLEAR_RESET_rstgen_rstn_uart1_core_; \
  58. _CLEAR_RESET_rstgen_rstn_uart1_apb_; \
  59. SET_GPIO_6_dout_uart1_pad_sout; \
  60. SET_GPIO_uart1_pad_sin(5); \
  61. SET_GPIO_5_doen_HIGH; \
  62. SET_GPIO_6_doen_LOW; \
  63. }
  64. #define vic_uart2_reset_clk_gpio_isp_enable { \
  65. _ENABLE_CLOCK_clk_uart2_apb_; \
  66. _ENABLE_CLOCK_clk_uart2_core_; \
  67. _CLEAR_RESET_rstgen_rstn_uart2_core_; \
  68. _CLEAR_RESET_rstgen_rstn_uart2_apb_; \
  69. SET_GPIO_uart2_pad_sin(13); \
  70. SET_GPIO_13_doen_HIGH; \
  71. SET_GPIO_12_dout_uart2_pad_sout; \
  72. SET_GPIO_12_doen_LOW; \
  73. }
  74. #define vic_uart2_reset_clk_disable { \
  75. _DISABLE_CLOCK_clk_uart2_apb_; \
  76. _ASSERT_RESET_rstgen_rstn_uart2_apb_; \
  77. _ASSERT_RESET_rstgen_rstn_uart2_core_; \
  78. }
  79. #define vic_uart2_reset_clk_gpio_misc_enable { \
  80. vic_uart2_reset_clk_disable; \
  81. _ENABLE_CLOCK_clk_uart2_apb_; \
  82. _ENABLE_CLOCK_clk_uart2_core_; \
  83. _CLEAR_RESET_rstgen_rstn_uart2_core_; \
  84. _CLEAR_RESET_rstgen_rstn_uart2_apb_; \
  85. SET_GPIO_uart2_pad_sin(13); \
  86. SET_GPIO_13_doen_HIGH; \
  87. SET_GPIO_14_dout_uart2_pad_sout; \
  88. SET_GPIO_14_doen_LOW; \
  89. }
  90. #define vic_uart3_reset_clk_gpio_isp_enable { \
  91. _ENABLE_CLOCK_clk_uart3_apb_; \
  92. _ENABLE_CLOCK_clk_uart3_core_; \
  93. _CLEAR_RESET_rstgen_rstn_uart3_core_; \
  94. _CLEAR_RESET_rstgen_rstn_uart3_apb_; \
  95. SET_GPIO_uart3_pad_sin(13); \
  96. SET_GPIO_13_doen_HIGH; \
  97. SET_GPIO_12_dout_uart3_pad_sout; \
  98. SET_GPIO_12_doen_LOW; \
  99. }
  100. #define vic_uart3_reset_clk_gpio_misc_enable { \
  101. _ENABLE_CLOCK_clk_uart3_apb_; \
  102. _ENABLE_CLOCK_clk_uart3_core_; \
  103. _CLEAR_RESET_rstgen_rstn_uart3_core_; \
  104. _CLEAR_RESET_rstgen_rstn_uart3_apb_; \
  105. SET_GPIO_uart2_pad_sin(13); \
  106. SET_GPIO_13_doen_HIGH; \
  107. SET_GPIO_14_dout_uart2_pad_sout; \
  108. SET_GPIO_14_doen_LOW; \
  109. }
  110. #endif /* _SFC_VIC_MODULE_RESET_CLKGEN_H */