syscon_sysmain_ctrl_macro.h 76 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /**
  3. ******************************************************************************
  4. * @file syscon_sysmain_ctrl_macro.h
  5. * @author StarFive Technology
  6. * @version V1.0
  7. * @date 06/25/2020
  8. * @brief
  9. ******************************************************************************
  10. * @copy
  11. *
  12. * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  13. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  14. * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
  15. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  16. * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  17. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  18. *
  19. * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
  20. */
  21. #ifndef _SYSCON_SYSMAIN_CTRL_MACRO_H_
  22. #define _SYSCON_SYSMAIN_CTRL_MACRO_H_
  23. //#define SYSCON_SYSMAIN_CTRL_BASE_ADDR 0x0
  24. #define syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x0
  25. #define syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x4
  26. #define syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x8
  27. #define syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xC
  28. #define syscon_sysmain_ctrl_register4_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x10
  29. #define syscon_sysmain_ctrl_SCFG_u74_boot_vect0_low_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x14
  30. #define syscon_sysmain_ctrl_SCFG_u74_boot_vect0_hi_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x18
  31. #define syscon_sysmain_ctrl_SCFG_u74_boot_vect1_low_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x1C
  32. #define syscon_sysmain_ctrl_SCFG_u74_boot_vect1_hi_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x20
  33. #define syscon_sysmain_ctrl_SCFG_u74_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x24
  34. #define syscon_sysmain_ctrl_register10_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x28
  35. #define syscon_sysmain_ctrl_register11_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x2C
  36. #define syscon_sysmain_ctrl_register12_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x30
  37. #define syscon_sysmain_ctrl_register13_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x34
  38. #define syscon_sysmain_ctrl_register14_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x38
  39. #define syscon_sysmain_ctrl_register15_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x3C
  40. #define syscon_sysmain_ctrl_register16_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x40
  41. #define syscon_sysmain_ctrl_register17_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x44
  42. #define syscon_sysmain_ctrl_register18_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x48
  43. #define syscon_sysmain_ctrl_register19_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x4C
  44. #define syscon_sysmain_ctrl_register20_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x50
  45. #define syscon_sysmain_ctrl_register21_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x54
  46. #define syscon_sysmain_ctrl_register22_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x58
  47. #define syscon_sysmain_ctrl_register23_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x5C
  48. #define syscon_sysmain_ctrl_qspi_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x60
  49. #define syscon_sysmain_ctrl_intmem_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x64
  50. #define syscon_sysmain_ctrl_register26_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x68
  51. #define syscon_sysmain_ctrl_register27_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x6C
  52. #define syscon_sysmain_ctrl_register28_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x70
  53. #define syscon_sysmain_ctrl_register29_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x74
  54. #define syscon_sysmain_ctrl_SCFG_gmac_timestamp0_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x78
  55. #define syscon_sysmain_ctrl_SCFG_gmac_timestamp1_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x7C
  56. #define syscon_sysmain_ctrl_register32_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x80
  57. #define syscon_sysmain_ctrl_register33_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x84
  58. #define syscon_sysmain_ctrl_register34_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x88
  59. #define syscon_sysmain_ctrl_register35_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x8C
  60. #define syscon_sysmain_ctrl_register36_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x90
  61. #define syscon_sysmain_ctrl_register37_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x94
  62. #define syscon_sysmain_ctrl_register38_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x98
  63. #define syscon_sysmain_ctrl_register39_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x9C
  64. #define syscon_sysmain_ctrl_register40_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xA0
  65. #define syscon_sysmain_ctrl_SCFG_intC1_7to0_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xA4
  66. #define syscon_sysmain_ctrl_SCFG_intC0_src15to8_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xA8
  67. #define syscon_sysmain_ctrl_SCFG_intC0_src23to16_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xAC
  68. #define syscon_sysmain_ctrl_SCFG_intC0_src31to24_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xB0
  69. #define syscon_sysmain_ctrl_register47_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xBC
  70. #define syscon_sysmain_ctrl_register48_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xC0
  71. #define syscon_sysmain_ctrl_register52_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xC4
  72. #define syscon_sysmain_ctrl_register49_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xC8
  73. #define syscon_sysmain_ctrl_register50_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xCC
  74. #define syscon_sysmain_ctrl_register51_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xD0
  75. #define syscon_sysmain_ctrl_register66_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xD8
  76. #define syscon_sysmain_ctrl_register53_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xDC
  77. #define syscon_sysmain_ctrl_register54_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xE0
  78. #define syscon_sysmain_ctrl_register55_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xE4
  79. #define syscon_sysmain_ctrl_register56_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xE8
  80. #define syscon_sysmain_ctrl_register57_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xEC
  81. #define syscon_sysmain_ctrl_register58_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xF0
  82. #define syscon_sysmain_ctrl_register59_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xF4
  83. #define syscon_sysmain_ctrl_register60_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xF8
  84. #define syscon_sysmain_ctrl_register61_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xFC
  85. #define syscon_sysmain_ctrl_register62_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x100
  86. #define syscon_sysmain_ctrl_register63_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x104
  87. #define syscon_sysmain_ctrl_register64_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x108
  88. #define syscon_sysmain_ctrl_register65_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x10C
  89. #define syscon_sysmain_ctrl_register68_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x110
  90. #define syscon_sysmain_ctrl_register67_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x114
  91. #define syscon_sysmain_ctrl_register69_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x118
  92. #define syscon_sysmain_ctrl_register70_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x11C
  93. #define syscon_sysmain_ctrl_register71_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x120
  94. #define syscon_sysmain_ctrl_register72_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x124
  95. #define _SET_SYSCON_REG_SCFG_pll0_reset(v) { \
  96. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR); \
  97. _ezchip_macro_read_value_ &= ~(0x1); \
  98. _ezchip_macro_read_value_ |= (v&0x1); \
  99. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR,_ezchip_macro_read_value_); \
  100. }
  101. #define _GET_SYSCON_REG_SCFG_pll0_reset(_ezchip_macro_read_value_) { \
  102. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR); \
  103. _ezchip_macro_read_value_ &= 0x1;\
  104. }
  105. #define _SET_SYSCON_REG_SCFG_pll0_pwrdn(v) { \
  106. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR); \
  107. _ezchip_macro_read_value_ &= ~(0x1<<1); \
  108. _ezchip_macro_read_value_ |= (v&0x1)<<1; \
  109. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR,_ezchip_macro_read_value_); \
  110. }
  111. #define _GET_SYSCON_REG_SCFG_pll0_pwrdn(_ezchip_macro_read_value_) { \
  112. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR) >> 1; \
  113. _ezchip_macro_read_value_ &= 0x1;\
  114. }
  115. #define _SET_SYSCON_REG_SCFG_pll0_intfb(v) { \
  116. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR); \
  117. _ezchip_macro_read_value_ &= ~(0x1<<2); \
  118. _ezchip_macro_read_value_ |= (v&0x1)<<2; \
  119. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR,_ezchip_macro_read_value_); \
  120. }
  121. #define _GET_SYSCON_REG_SCFG_pll0_intfb(_ezchip_macro_read_value_) { \
  122. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR) >> 2; \
  123. _ezchip_macro_read_value_ &= 0x1;\
  124. }
  125. #define _SET_SYSCON_REG_SCFG_pll0_bypass(v) { \
  126. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR); \
  127. _ezchip_macro_read_value_ &= ~(0x1<<3); \
  128. _ezchip_macro_read_value_ |= (v&0x1)<<3; \
  129. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR,_ezchip_macro_read_value_); \
  130. }
  131. #define _GET_SYSCON_REG_SCFG_pll0_bypass(_ezchip_macro_read_value_) { \
  132. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR) >> 3; \
  133. _ezchip_macro_read_value_ &= 0x1;\
  134. }
  135. #define _SET_SYSCON_REG_SCFG_pll0_clk_refdiv(v) { \
  136. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR); \
  137. _ezchip_macro_read_value_ &= ~(0xF<<4); \
  138. _ezchip_macro_read_value_ |= (v&0xF)<<4; \
  139. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR,_ezchip_macro_read_value_); \
  140. }
  141. #define _GET_SYSCON_REG_SCFG_pll0_clk_refdiv(_ezchip_macro_read_value_) { \
  142. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR) >> 4; \
  143. _ezchip_macro_read_value_ &= 0xf;\
  144. }
  145. #define _SET_SYSCON_REG_SCFG_pll0_clk_fbkdiv(v) { \
  146. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR); \
  147. _ezchip_macro_read_value_ &= ~(0x3F<<8); \
  148. _ezchip_macro_read_value_ |= (v&0x3F)<<8; \
  149. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR,_ezchip_macro_read_value_); \
  150. }
  151. #define _GET_SYSCON_REG_SCFG_pll0_clk_fbkdiv(_ezchip_macro_read_value_) { \
  152. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR) >> 8; \
  153. _ezchip_macro_read_value_ &= 0x3f;\
  154. }
  155. #define _SET_SYSCON_REG_SCFG_pll0_bw_adj(v) { \
  156. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR); \
  157. _ezchip_macro_read_value_ &= ~(0x3F<<16); \
  158. _ezchip_macro_read_value_ |= (v&0x3F)<<16; \
  159. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR,_ezchip_macro_read_value_); \
  160. }
  161. #define _GET_SYSCON_REG_SCFG_pll0_bw_adj(_ezchip_macro_read_value_) { \
  162. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR) >> 16; \
  163. _ezchip_macro_read_value_ &= 0x3f;\
  164. }
  165. #define _SET_SYSCON_REG_SCFG_pll0_clk_outdiv(v) { \
  166. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR); \
  167. _ezchip_macro_read_value_ &= ~(0xF<<24); \
  168. _ezchip_macro_read_value_ |= (v&0xF)<<24; \
  169. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR,_ezchip_macro_read_value_); \
  170. }
  171. #define _GET_SYSCON_REG_SCFG_pll0_clk_outdiv(_ezchip_macro_read_value_) { \
  172. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR) >> 24; \
  173. _ezchip_macro_read_value_ &= 0xf;\
  174. }
  175. #define _SET_SYSCON_REG_SCFG_pll1_reset(v) { \
  176. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR); \
  177. _ezchip_macro_read_value_ &= ~(0x1); \
  178. _ezchip_macro_read_value_ |= (v&0x1); \
  179. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,_ezchip_macro_read_value_); \
  180. }
  181. #define _GET_SYSCON_REG_SCFG_pll1_reset(_ezchip_macro_read_value_) { \
  182. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR); \
  183. _ezchip_macro_read_value_ &= 0x1;\
  184. }
  185. #define _SET_SYSCON_REG_SCFG_pll1_pwrdn(v) { \
  186. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR); \
  187. _ezchip_macro_read_value_ &= ~(0x1<<1); \
  188. _ezchip_macro_read_value_ |= (v&0x1)<<1; \
  189. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,_ezchip_macro_read_value_); \
  190. }
  191. #define _GET_SYSCON_REG_SCFG_pll1_pwrdn(_ezchip_macro_read_value_) { \
  192. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR) >> 1; \
  193. _ezchip_macro_read_value_ &= 0x1;\
  194. }
  195. #define _SET_SYSCON_REG_SCFG_pll1_intfb(v) { \
  196. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR); \
  197. _ezchip_macro_read_value_ &= ~(0x1<<2); \
  198. _ezchip_macro_read_value_ |= (v&0x1)<<2; \
  199. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,_ezchip_macro_read_value_); \
  200. }
  201. #define _GET_SYSCON_REG_SCFG_pll1_intfb(_ezchip_macro_read_value_) { \
  202. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR) >> 2; \
  203. _ezchip_macro_read_value_ &= 0x1;\
  204. }
  205. #define _SET_SYSCON_REG_SCFG_pll1_bypass(v) { \
  206. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR); \
  207. _ezchip_macro_read_value_ &= ~(0x1<<3); \
  208. _ezchip_macro_read_value_ |= (v&0x1)<<3; \
  209. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,_ezchip_macro_read_value_); \
  210. }
  211. #define _GET_SYSCON_REG_SCFG_pll1_bypass(_ezchip_macro_read_value_) { \
  212. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR) >> 3; \
  213. _ezchip_macro_read_value_ &= 0x1;\
  214. }
  215. #define _SET_SYSCON_REG_SCFG_pll1_clk_refdiv(v) { \
  216. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR); \
  217. _ezchip_macro_read_value_ &= ~(0xF<<4); \
  218. _ezchip_macro_read_value_ |= (v&0xF)<<4; \
  219. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,_ezchip_macro_read_value_); \
  220. }
  221. #define _GET_SYSCON_REG_SCFG_pll1_clk_refdiv(_ezchip_macro_read_value_) { \
  222. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR) >> 4; \
  223. _ezchip_macro_read_value_ &= 0xf;\
  224. }
  225. #define _SET_SYSCON_REG_SCFG_pll1_clk_fbkdiv(v) { \
  226. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR); \
  227. _ezchip_macro_read_value_ &= ~(0x3F<<8); \
  228. _ezchip_macro_read_value_ |= (v&0x3F)<<8; \
  229. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,_ezchip_macro_read_value_); \
  230. }
  231. #define _GET_SYSCON_REG_SCFG_pll1_clk_fbkdiv(_ezchip_macro_read_value_) { \
  232. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR) >> 8; \
  233. _ezchip_macro_read_value_ &= 0x3f;\
  234. }
  235. #define _SET_SYSCON_REG_SCFG_pll1_bw_adj(v) { \
  236. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR); \
  237. _ezchip_macro_read_value_ &= ~(0x3F<<16); \
  238. _ezchip_macro_read_value_ |= (v&0x3F)<<16; \
  239. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,_ezchip_macro_read_value_); \
  240. }
  241. #define _GET_SYSCON_REG_SCFG_pll1_bw_adj(_ezchip_macro_read_value_) { \
  242. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR) >> 16; \
  243. _ezchip_macro_read_value_ &= 0x3f;\
  244. }
  245. #define _SET_SYSCON_REG_SCFG_pll1_clk_outdiv(v) { \
  246. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR); \
  247. _ezchip_macro_read_value_ &= ~(0xF<<24); \
  248. _ezchip_macro_read_value_ |= (v&0xF)<<24; \
  249. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,_ezchip_macro_read_value_); \
  250. }
  251. #define _GET_SYSCON_REG_SCFG_pll1_clk_outdiv(_ezchip_macro_read_value_) { \
  252. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR) >> 24; \
  253. _ezchip_macro_read_value_ &= 0xf;\
  254. }
  255. #define _SET_SYSCON_REG_SCFG_pll2_reset(v) { \
  256. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR); \
  257. _ezchip_macro_read_value_ &= ~(0x1); \
  258. _ezchip_macro_read_value_ |= (v&0x1); \
  259. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR,_ezchip_macro_read_value_); \
  260. }
  261. #define _GET_SYSCON_REG_SCFG_pll2_reset(_ezchip_macro_read_value_) { \
  262. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR); \
  263. _ezchip_macro_read_value_ &= 0x1;\
  264. }
  265. #define _SET_SYSCON_REG_SCFG_pll2_pwrdn(v) { \
  266. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR); \
  267. _ezchip_macro_read_value_ &= ~(0x1<<1); \
  268. _ezchip_macro_read_value_ |= (v&0x1)<<1; \
  269. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR,_ezchip_macro_read_value_); \
  270. }
  271. #define _GET_SYSCON_REG_SCFG_pll2_pwrdn(_ezchip_macro_read_value_) { \
  272. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR) >> 1; \
  273. _ezchip_macro_read_value_ &= 0x1;\
  274. }
  275. #define _SET_SYSCON_REG_SCFG_pll2_intfb(v) { \
  276. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR); \
  277. _ezchip_macro_read_value_ &= ~(0x1<<2); \
  278. _ezchip_macro_read_value_ |= (v&0x1)<<2; \
  279. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR,_ezchip_macro_read_value_); \
  280. }
  281. #define _GET_SYSCON_REG_SCFG_pll2_intfb(_ezchip_macro_read_value_) { \
  282. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR) >> 2; \
  283. _ezchip_macro_read_value_ &= 0x1;\
  284. }
  285. #define _SET_SYSCON_REG_SCFG_pll2_bypass(v) { \
  286. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR); \
  287. _ezchip_macro_read_value_ &= ~(0x1<<3); \
  288. _ezchip_macro_read_value_ |= (v&0x1)<<3; \
  289. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR,_ezchip_macro_read_value_); \
  290. }
  291. #define _GET_SYSCON_REG_SCFG_pll2_bypass(_ezchip_macro_read_value_) { \
  292. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR) >> 3; \
  293. _ezchip_macro_read_value_ &= 0x1;\
  294. }
  295. #define _SET_SYSCON_REG_SCFG_pll2_clk_refdiv(v) { \
  296. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR); \
  297. _ezchip_macro_read_value_ &= ~(0xF<<4); \
  298. _ezchip_macro_read_value_ |= (v&0xF)<<4; \
  299. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR,_ezchip_macro_read_value_); \
  300. }
  301. #define _GET_SYSCON_REG_SCFG_pll2_clk_refdiv(_ezchip_macro_read_value_) { \
  302. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR) >> 4; \
  303. _ezchip_macro_read_value_ &= 0xf;\
  304. }
  305. #define _SET_SYSCON_REG_SCFG_pll2_clk_fbkdiv(v) { \
  306. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR); \
  307. _ezchip_macro_read_value_ &= ~(0x3F<<8); \
  308. _ezchip_macro_read_value_ |= (v&0x3F)<<8; \
  309. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR,_ezchip_macro_read_value_); \
  310. }
  311. #define _GET_SYSCON_REG_SCFG_pll2_clk_fbkdiv(_ezchip_macro_read_value_) { \
  312. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR) >> 8; \
  313. _ezchip_macro_read_value_ &= 0x3f;\
  314. }
  315. #define _SET_SYSCON_REG_SCFG_pll2_bw_adj(v) { \
  316. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR); \
  317. _ezchip_macro_read_value_ &= ~(0x3F<<16); \
  318. _ezchip_macro_read_value_ |= (v&0x3F)<<16; \
  319. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR,_ezchip_macro_read_value_); \
  320. }
  321. #define _GET_SYSCON_REG_SCFG_pll2_bw_adj(_ezchip_macro_read_value_) { \
  322. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR) >> 16; \
  323. _ezchip_macro_read_value_ &= 0x3f;\
  324. }
  325. #define _SET_SYSCON_REG_SCFG_pll2_clk_outdiv(v) { \
  326. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR); \
  327. _ezchip_macro_read_value_ &= ~(0xF<<24); \
  328. _ezchip_macro_read_value_ |= (v&0xF)<<24; \
  329. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR,_ezchip_macro_read_value_); \
  330. }
  331. #define _GET_SYSCON_REG_SCFG_pll2_clk_outdiv(_ezchip_macro_read_value_) { \
  332. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR) >> 24; \
  333. _ezchip_macro_read_value_ &= 0xf;\
  334. }
  335. #define _SET_SYSCON_REG_SCFG_plls_stat_pll0_test(v) { \
  336. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR); \
  337. _ezchip_macro_read_value_ &= ~(0x1); \
  338. _ezchip_macro_read_value_ |= (v&0x1); \
  339. MA_OUTW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR,_ezchip_macro_read_value_); \
  340. }
  341. #define _GET_SYSCON_REG_SCFG_plls_stat_pll0_test(_ezchip_macro_read_value_) { \
  342. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR); \
  343. _ezchip_macro_read_value_ &= 0x1;\
  344. }
  345. #define _SET_SYSCON_REG_SCFG_plls_stat_pll1_test(v) { \
  346. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR); \
  347. _ezchip_macro_read_value_ &= ~(0x1<<1); \
  348. _ezchip_macro_read_value_ |= (v&0x1)<<1; \
  349. MA_OUTW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR,_ezchip_macro_read_value_); \
  350. }
  351. #define _GET_SYSCON_REG_SCFG_plls_stat_pll1_test(_ezchip_macro_read_value_) { \
  352. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 1; \
  353. _ezchip_macro_read_value_ &= 0x1;\
  354. }
  355. #define _SET_SYSCON_REG_SCFG_plls_stat_pll2_test(v) { \
  356. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR); \
  357. _ezchip_macro_read_value_ &= ~(0x1<<2); \
  358. _ezchip_macro_read_value_ |= (v&0x1)<<2; \
  359. MA_OUTW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR,_ezchip_macro_read_value_); \
  360. }
  361. #define _GET_SYSCON_REG_SCFG_plls_stat_pll2_test(_ezchip_macro_read_value_) { \
  362. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 2; \
  363. _ezchip_macro_read_value_ &= 0x1;\
  364. }
  365. #define _GET_SYSCON_REG_SCFG_plls_stat_pll0_lock(_ezchip_macro_read_value_) { \
  366. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 4; \
  367. _ezchip_macro_read_value_ &= 0x1;\
  368. }
  369. #define _GET_SYSCON_REG_SCFG_plls_stat_pll0_ref_slip(_ezchip_macro_read_value_) { \
  370. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 5; \
  371. _ezchip_macro_read_value_ &= 0x1;\
  372. }
  373. #define _GET_SYSCON_REG_SCFG_plls_stat_pll0_fdbk_slip(_ezchip_macro_read_value_) { \
  374. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 6; \
  375. _ezchip_macro_read_value_ &= 0x1;\
  376. }
  377. #define _GET_SYSCON_REG_SCFG_plls_stat_pll1_lock(_ezchip_macro_read_value_) { \
  378. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 8; \
  379. _ezchip_macro_read_value_ &= 0x1;\
  380. }
  381. #define _GET_SYSCON_REG_SCFG_plls_stat_pll1_ref_slip(_ezchip_macro_read_value_) { \
  382. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 9; \
  383. _ezchip_macro_read_value_ &= 0x1;\
  384. }
  385. #define _GET_SYSCON_REG_SCFG_plls_stat_pll1_fdbk_slip(_ezchip_macro_read_value_) { \
  386. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 10; \
  387. _ezchip_macro_read_value_ &= 0x1;\
  388. }
  389. #define _GET_SYSCON_REG_SCFG_plls_stat_pll2_lock(_ezchip_macro_read_value_) { \
  390. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 12; \
  391. _ezchip_macro_read_value_ &= 0x1;\
  392. }
  393. #define _GET_SYSCON_REG_SCFG_plls_stat_pll2_ref_slip(_ezchip_macro_read_value_) { \
  394. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 13; \
  395. _ezchip_macro_read_value_ &= 0x1;\
  396. }
  397. #define _GET_SYSCON_REG_SCFG_plls_stat_pll2_fdbk_slip(_ezchip_macro_read_value_) { \
  398. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 14; \
  399. _ezchip_macro_read_value_ &= 0x1;\
  400. }
  401. #define _GET_SYSCON_REG_register4_SCFG_u74_halt_from_tile0(_ezchip_macro_read_value_) { \
  402. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register4_REG_ADDR); \
  403. _ezchip_macro_read_value_ &= 0x1;\
  404. }
  405. #define _GET_SYSCON_REG_register4_SCFG_u74_halt_from_tile1(_ezchip_macro_read_value_) { \
  406. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register4_REG_ADDR) >> 1; \
  407. _ezchip_macro_read_value_ &= 0x1;\
  408. }
  409. #define _GET_SYSCON_REG_register4_SCFG_u74_debug_ndreset(_ezchip_macro_read_value_) { \
  410. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register4_REG_ADDR) >> 2; \
  411. _ezchip_macro_read_value_ &= 0x1;\
  412. }
  413. #define _GET_SYSCON_REG_register4_SCFG_u74_debug_dmactive(_ezchip_macro_read_value_) { \
  414. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register4_REG_ADDR) >> 3; \
  415. _ezchip_macro_read_value_ &= 0x1;\
  416. }
  417. #define _SET_SYSCON_REG_SCFG_u74_boot_vect0_low_b32(v) { \
  418. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_boot_vect0_low_REG_ADDR); \
  419. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  420. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  421. MA_OUTW(syscon_sysmain_ctrl_SCFG_u74_boot_vect0_low_REG_ADDR,_ezchip_macro_read_value_); \
  422. }
  423. #define _GET_SYSCON_REG_SCFG_u74_boot_vect0_low_b32(_ezchip_macro_read_value_) { \
  424. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_boot_vect0_low_REG_ADDR); \
  425. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  426. }
  427. #define _SET_SYSCON_REG_SCFG_u74_boot_vect0_hi_b6(v) { \
  428. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_boot_vect0_hi_REG_ADDR); \
  429. _ezchip_macro_read_value_ &= ~(0x3F); \
  430. _ezchip_macro_read_value_ |= (v&0x3F); \
  431. MA_OUTW(syscon_sysmain_ctrl_SCFG_u74_boot_vect0_hi_REG_ADDR,_ezchip_macro_read_value_); \
  432. }
  433. #define _GET_SYSCON_REG_SCFG_u74_boot_vect0_hi_b6(_ezchip_macro_read_value_) { \
  434. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_boot_vect0_hi_REG_ADDR); \
  435. _ezchip_macro_read_value_ &= 0x3f;\
  436. }
  437. #define _SET_SYSCON_REG_SCFG_u74_boot_vect1_low_b32(v) { \
  438. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_boot_vect1_low_REG_ADDR); \
  439. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  440. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  441. MA_OUTW(syscon_sysmain_ctrl_SCFG_u74_boot_vect1_low_REG_ADDR,_ezchip_macro_read_value_); \
  442. }
  443. #define _GET_SYSCON_REG_SCFG_u74_boot_vect1_low_b32(_ezchip_macro_read_value_) { \
  444. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_boot_vect1_low_REG_ADDR); \
  445. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  446. }
  447. #define _SET_SYSCON_REG_SCFG_u74_boot_vect1_hi_b6(v) { \
  448. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_boot_vect1_hi_REG_ADDR); \
  449. _ezchip_macro_read_value_ &= ~(0x3F); \
  450. _ezchip_macro_read_value_ |= (v&0x3F); \
  451. MA_OUTW(syscon_sysmain_ctrl_SCFG_u74_boot_vect1_hi_REG_ADDR,_ezchip_macro_read_value_); \
  452. }
  453. #define _GET_SYSCON_REG_SCFG_u74_boot_vect1_hi_b6(_ezchip_macro_read_value_) { \
  454. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_boot_vect1_hi_REG_ADDR); \
  455. _ezchip_macro_read_value_ &= 0x3f;\
  456. }
  457. #define _SET_SYSCON_REG_SCFG_u74_PRID(v) { \
  458. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_REG_ADDR); \
  459. _ezchip_macro_read_value_ &= ~(0x7FF); \
  460. _ezchip_macro_read_value_ |= (v&0x7FF); \
  461. MA_OUTW(syscon_sysmain_ctrl_SCFG_u74_REG_ADDR,_ezchip_macro_read_value_); \
  462. }
  463. #define _GET_SYSCON_REG_SCFG_u74_PRID(_ezchip_macro_read_value_) { \
  464. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_REG_ADDR); \
  465. _ezchip_macro_read_value_ &= 0x7ff;\
  466. }
  467. #define _GET_SYSCON_REG_register10_e24_halt(_ezchip_macro_read_value_) { \
  468. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register10_REG_ADDR); \
  469. _ezchip_macro_read_value_ &= 0x1;\
  470. }
  471. #define _GET_SYSCON_REG_register10_e24_dbg_reset(_ezchip_macro_read_value_) { \
  472. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register10_REG_ADDR) >> 1; \
  473. _ezchip_macro_read_value_ &= 0x1;\
  474. }
  475. #define _GET_SYSCON_REG_register10_e24_dbg_active(_ezchip_macro_read_value_) { \
  476. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register10_REG_ADDR) >> 2; \
  477. _ezchip_macro_read_value_ &= 0x1;\
  478. }
  479. #define _SET_SYSCON_REG_register11_SCFG_nbdla_pwrbus_ram_a_pd(v) { \
  480. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register11_REG_ADDR); \
  481. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  482. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  483. MA_OUTW(syscon_sysmain_ctrl_register11_REG_ADDR,_ezchip_macro_read_value_); \
  484. }
  485. #define _GET_SYSCON_REG_register11_SCFG_nbdla_pwrbus_ram_a_pd(_ezchip_macro_read_value_) { \
  486. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register11_REG_ADDR); \
  487. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  488. }
  489. #define _SET_SYSCON_REG_register12_SCFG_nbdla_pwrbus_ram_c_pd(v) { \
  490. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register12_REG_ADDR); \
  491. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  492. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  493. MA_OUTW(syscon_sysmain_ctrl_register12_REG_ADDR,_ezchip_macro_read_value_); \
  494. }
  495. #define _GET_SYSCON_REG_register12_SCFG_nbdla_pwrbus_ram_c_pd(_ezchip_macro_read_value_) { \
  496. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register12_REG_ADDR); \
  497. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  498. }
  499. #define _SET_SYSCON_REG_register13_SCFG_nbdla_pwrbus_ram_o_pd(v) { \
  500. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register13_REG_ADDR); \
  501. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  502. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  503. MA_OUTW(syscon_sysmain_ctrl_register13_REG_ADDR,_ezchip_macro_read_value_); \
  504. }
  505. #define _GET_SYSCON_REG_register13_SCFG_nbdla_pwrbus_ram_o_pd(_ezchip_macro_read_value_) { \
  506. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register13_REG_ADDR); \
  507. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  508. }
  509. #define _SET_SYSCON_REG_register14_SCFG_nbdla_pwrbus_ram_p_pd(v) { \
  510. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register14_REG_ADDR); \
  511. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  512. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  513. MA_OUTW(syscon_sysmain_ctrl_register14_REG_ADDR,_ezchip_macro_read_value_); \
  514. }
  515. #define _GET_SYSCON_REG_register14_SCFG_nbdla_pwrbus_ram_p_pd(_ezchip_macro_read_value_) { \
  516. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register14_REG_ADDR); \
  517. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  518. }
  519. #define _SET_SYSCON_REG_register15_SCFG_nbdla_pwrbus_ram_x_pd(v) { \
  520. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register15_REG_ADDR); \
  521. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  522. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  523. MA_OUTW(syscon_sysmain_ctrl_register15_REG_ADDR,_ezchip_macro_read_value_); \
  524. }
  525. #define _GET_SYSCON_REG_register15_SCFG_nbdla_pwrbus_ram_x_pd(_ezchip_macro_read_value_) { \
  526. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register15_REG_ADDR); \
  527. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  528. }
  529. #define _SET_SYSCON_REG_register16_SCFG_nbdla_globclk_ovr_on(v) { \
  530. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register16_REG_ADDR); \
  531. _ezchip_macro_read_value_ &= ~(0x1); \
  532. _ezchip_macro_read_value_ |= (v&0x1); \
  533. MA_OUTW(syscon_sysmain_ctrl_register16_REG_ADDR,_ezchip_macro_read_value_); \
  534. }
  535. #define _GET_SYSCON_REG_register16_SCFG_nbdla_globclk_ovr_on(_ezchip_macro_read_value_) { \
  536. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register16_REG_ADDR); \
  537. _ezchip_macro_read_value_ &= 0x1;\
  538. }
  539. #define _SET_SYSCON_REG_register16_SCFG_nbdla_disable_clock_gating(v) { \
  540. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register16_REG_ADDR); \
  541. _ezchip_macro_read_value_ &= ~(0x1<<1); \
  542. _ezchip_macro_read_value_ |= (v&0x1)<<1; \
  543. MA_OUTW(syscon_sysmain_ctrl_register16_REG_ADDR,_ezchip_macro_read_value_); \
  544. }
  545. #define _GET_SYSCON_REG_register16_SCFG_nbdla_disable_clock_gating(_ezchip_macro_read_value_) { \
  546. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register16_REG_ADDR) >> 1; \
  547. _ezchip_macro_read_value_ &= 0x1;\
  548. }
  549. #define _SET_SYSCON_REG_register16_SCFG_nbdla_direct_reset(v) { \
  550. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register16_REG_ADDR); \
  551. _ezchip_macro_read_value_ &= ~(0x1<<2); \
  552. _ezchip_macro_read_value_ |= (v&0x1)<<2; \
  553. MA_OUTW(syscon_sysmain_ctrl_register16_REG_ADDR,_ezchip_macro_read_value_); \
  554. }
  555. #define _GET_SYSCON_REG_register16_SCFG_nbdla_direct_reset(_ezchip_macro_read_value_) { \
  556. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register16_REG_ADDR) >> 2; \
  557. _ezchip_macro_read_value_ &= 0x1;\
  558. }
  559. #define _SET_SYSCON_REG_register16_SCFG_nbdla_clkgating_en(v) { \
  560. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register16_REG_ADDR); \
  561. _ezchip_macro_read_value_ &= ~(0x1<<3); \
  562. _ezchip_macro_read_value_ |= (v&0x1)<<3; \
  563. MA_OUTW(syscon_sysmain_ctrl_register16_REG_ADDR,_ezchip_macro_read_value_); \
  564. }
  565. #define _GET_SYSCON_REG_register16_SCFG_nbdla_clkgating_en(_ezchip_macro_read_value_) { \
  566. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register16_REG_ADDR) >> 3; \
  567. _ezchip_macro_read_value_ &= 0x1;\
  568. }
  569. #define _GET_SYSCON_REG_register17_SCFG_jpegc_cur_inst_a(_ezchip_macro_read_value_) { \
  570. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register17_REG_ADDR); \
  571. _ezchip_macro_read_value_ &= 0x3;\
  572. }
  573. #define _GET_SYSCON_REG_register18_SCFG_wave511_vpu_idle(_ezchip_macro_read_value_) { \
  574. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register18_REG_ADDR); \
  575. _ezchip_macro_read_value_ &= 0x1;\
  576. }
  577. #define _GET_SYSCON_REG_register19_SCFG_wave521_vpu_idle(_ezchip_macro_read_value_) { \
  578. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register19_REG_ADDR); \
  579. _ezchip_macro_read_value_ &= 0x1;\
  580. }
  581. #define _SET_SYSCON_REG_register20_u0_syscon_162_SCFG_gc300_csys_req(v) { \
  582. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register20_REG_ADDR); \
  583. _ezchip_macro_read_value_ &= ~(0x1); \
  584. _ezchip_macro_read_value_ |= (v&0x1); \
  585. MA_OUTW(syscon_sysmain_ctrl_register20_REG_ADDR,_ezchip_macro_read_value_); \
  586. }
  587. #define _GET_SYSCON_REG_register20_u0_syscon_162_SCFG_gc300_csys_req(_ezchip_macro_read_value_) { \
  588. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register20_REG_ADDR); \
  589. _ezchip_macro_read_value_ &= 0x1;\
  590. }
  591. #define _GET_SYSCON_REG_register21_u0_syscon_162_SCFG_gc300_cactive(_ezchip_macro_read_value_) { \
  592. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register21_REG_ADDR); \
  593. _ezchip_macro_read_value_ &= 0x1;\
  594. }
  595. #define _GET_SYSCON_REG_register21_u0_syscon_162_SCFG_gc300_csys_ack(_ezchip_macro_read_value_) { \
  596. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register21_REG_ADDR) >> 1; \
  597. _ezchip_macro_read_value_ &= 0x1;\
  598. }
  599. #define _GET_SYSCON_REG_register22_u0_syscon_162_SCFG_gc300_debug_out(_ezchip_macro_read_value_) { \
  600. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register22_REG_ADDR); \
  601. _ezchip_macro_read_value_ &= 0xff;\
  602. }
  603. #define _SET_SYSCON_REG_register23_SCFG_cmsensor_rst0(v) { \
  604. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register23_REG_ADDR); \
  605. _ezchip_macro_read_value_ &= ~(0x1); \
  606. _ezchip_macro_read_value_ |= (v&0x1); \
  607. MA_OUTW(syscon_sysmain_ctrl_register23_REG_ADDR,_ezchip_macro_read_value_); \
  608. }
  609. #define _GET_SYSCON_REG_register23_SCFG_cmsensor_rst0(_ezchip_macro_read_value_) { \
  610. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register23_REG_ADDR); \
  611. _ezchip_macro_read_value_ &= 0x1;\
  612. }
  613. #define _SET_SYSCON_REG_register23_SCFG_cmsensor_rst1(v) { \
  614. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register23_REG_ADDR); \
  615. _ezchip_macro_read_value_ &= ~(0x1<<1); \
  616. _ezchip_macro_read_value_ |= (v&0x1)<<1; \
  617. MA_OUTW(syscon_sysmain_ctrl_register23_REG_ADDR,_ezchip_macro_read_value_); \
  618. }
  619. #define _GET_SYSCON_REG_register23_SCFG_cmsensor_rst1(_ezchip_macro_read_value_) { \
  620. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register23_REG_ADDR) >> 1; \
  621. _ezchip_macro_read_value_ &= 0x1;\
  622. }
  623. #define _SET_SYSCON_REG_qspi_SCFG_sram_config(v) { \
  624. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_qspi_REG_ADDR); \
  625. _ezchip_macro_read_value_ &= ~(0xFF); \
  626. _ezchip_macro_read_value_ |= (v&0xFF); \
  627. MA_OUTW(syscon_sysmain_ctrl_qspi_REG_ADDR,_ezchip_macro_read_value_); \
  628. }
  629. #define _GET_SYSCON_REG_qspi_SCFG_sram_config(_ezchip_macro_read_value_) { \
  630. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_qspi_REG_ADDR); \
  631. _ezchip_macro_read_value_ &= 0xff;\
  632. }
  633. #define _SET_SYSCON_REG_intmem_SCFG_sram_config(v) { \
  634. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_intmem_REG_ADDR); \
  635. _ezchip_macro_read_value_ &= ~(0xFF); \
  636. _ezchip_macro_read_value_ |= (v&0xFF); \
  637. MA_OUTW(syscon_sysmain_ctrl_intmem_REG_ADDR,_ezchip_macro_read_value_); \
  638. }
  639. #define _GET_SYSCON_REG_intmem_SCFG_sram_config(_ezchip_macro_read_value_) { \
  640. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_intmem_REG_ADDR); \
  641. _ezchip_macro_read_value_ &= 0xff;\
  642. }
  643. #define _SET_SYSCON_REG_intmem_SCFG_sram_config_rom(v) { \
  644. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_intmem_REG_ADDR); \
  645. _ezchip_macro_read_value_ &= ~(0xFF<<8); \
  646. _ezchip_macro_read_value_ |= (v&0xFF)<<8; \
  647. MA_OUTW(syscon_sysmain_ctrl_intmem_REG_ADDR,_ezchip_macro_read_value_); \
  648. }
  649. #define _GET_SYSCON_REG_intmem_SCFG_sram_config_rom(_ezchip_macro_read_value_) { \
  650. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_intmem_REG_ADDR) >> 8; \
  651. _ezchip_macro_read_value_ &= 0xff;\
  652. }
  653. #define _SET_SYSCON_REG_register26_SCFG_dma1p2p_sel(v) { \
  654. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register26_REG_ADDR); \
  655. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  656. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  657. MA_OUTW(syscon_sysmain_ctrl_register26_REG_ADDR,_ezchip_macro_read_value_); \
  658. }
  659. #define _GET_SYSCON_REG_register26_SCFG_dma1p2p_sel(_ezchip_macro_read_value_) { \
  660. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register26_REG_ADDR); \
  661. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  662. }
  663. #define _SET_SYSCON_REG_register27_SCFG_dmaezMst_sel(v) { \
  664. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register27_REG_ADDR); \
  665. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  666. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  667. MA_OUTW(syscon_sysmain_ctrl_register27_REG_ADDR,_ezchip_macro_read_value_); \
  668. }
  669. #define _GET_SYSCON_REG_register27_SCFG_dmaezMst_sel(_ezchip_macro_read_value_) { \
  670. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register27_REG_ADDR); \
  671. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  672. }
  673. #define _SET_SYSCON_REG_register28_SCFG_gmac_phy_intf_sel(v) { \
  674. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register28_REG_ADDR); \
  675. _ezchip_macro_read_value_ &= ~(0x7); \
  676. _ezchip_macro_read_value_ |= (v&0x7); \
  677. MA_OUTW(syscon_sysmain_ctrl_register28_REG_ADDR,_ezchip_macro_read_value_); \
  678. }
  679. #define _GET_SYSCON_REG_register28_SCFG_gmac_phy_intf_sel(_ezchip_macro_read_value_) { \
  680. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register28_REG_ADDR); \
  681. _ezchip_macro_read_value_ &= 0x7;\
  682. }
  683. #define _SET_SYSCON_REG_register28_gmac_SCFG_sram_cfg(v) { \
  684. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register28_REG_ADDR); \
  685. _ezchip_macro_read_value_ &= ~(0xFF<<4); \
  686. _ezchip_macro_read_value_ |= (v&0xFF)<<4; \
  687. MA_OUTW(syscon_sysmain_ctrl_register28_REG_ADDR,_ezchip_macro_read_value_); \
  688. }
  689. #define _GET_SYSCON_REG_register28_gmac_SCFG_sram_cfg(_ezchip_macro_read_value_) { \
  690. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register28_REG_ADDR) >> 4; \
  691. _ezchip_macro_read_value_ &= 0xff;\
  692. }
  693. #define _GET_SYSCON_REG_register29_gmac_speed(_ezchip_macro_read_value_) { \
  694. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register29_REG_ADDR); \
  695. _ezchip_macro_read_value_ &= 0x3;\
  696. }
  697. #define _GET_SYSCON_REG_register29_gmac_ptp_pps(_ezchip_macro_read_value_) { \
  698. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register29_REG_ADDR) >> 2; \
  699. _ezchip_macro_read_value_ &= 0x1;\
  700. }
  701. #define _GET_SYSCON_REG_register29_gmac_tx_ckg_ctrl(_ezchip_macro_read_value_) { \
  702. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register29_REG_ADDR) >> 3; \
  703. _ezchip_macro_read_value_ &= 0x1;\
  704. }
  705. #define _GET_SYSCON_REG_SCFG_gmac_timestamp0_ptp(_ezchip_macro_read_value_) { \
  706. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_gmac_timestamp0_REG_ADDR); \
  707. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  708. }
  709. #define _GET_SYSCON_REG_SCFG_gmac_timestamp1_ptp(_ezchip_macro_read_value_) { \
  710. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_gmac_timestamp1_REG_ADDR); \
  711. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  712. }
  713. #define _SET_SYSCON_REG_register32_SCFG_gmac_phy_rstn(v) { \
  714. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register32_REG_ADDR); \
  715. _ezchip_macro_read_value_ &= ~(0x1); \
  716. _ezchip_macro_read_value_ |= (v&0x1); \
  717. MA_OUTW(syscon_sysmain_ctrl_register32_REG_ADDR,_ezchip_macro_read_value_); \
  718. }
  719. #define _GET_SYSCON_REG_register32_SCFG_gmac_phy_rstn(_ezchip_macro_read_value_) { \
  720. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register32_REG_ADDR); \
  721. _ezchip_macro_read_value_ &= 0x1;\
  722. }
  723. #define _SET_SYSCON_REG_register33_SCFG_sdio0_hbig_endian(v) { \
  724. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register33_REG_ADDR); \
  725. _ezchip_macro_read_value_ &= ~(0x1); \
  726. _ezchip_macro_read_value_ |= (v&0x1); \
  727. MA_OUTW(syscon_sysmain_ctrl_register33_REG_ADDR,_ezchip_macro_read_value_); \
  728. }
  729. #define _GET_SYSCON_REG_register33_SCFG_sdio0_hbig_endian(_ezchip_macro_read_value_) { \
  730. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register33_REG_ADDR); \
  731. _ezchip_macro_read_value_ &= 0x1;\
  732. }
  733. #define _SET_SYSCON_REG_register33_SCFG_sdio0_m_hbig_endian(v) { \
  734. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register33_REG_ADDR); \
  735. _ezchip_macro_read_value_ &= ~(0x1<<1); \
  736. _ezchip_macro_read_value_ |= (v&0x1)<<1; \
  737. MA_OUTW(syscon_sysmain_ctrl_register33_REG_ADDR,_ezchip_macro_read_value_); \
  738. }
  739. #define _GET_SYSCON_REG_register33_SCFG_sdio0_m_hbig_endian(_ezchip_macro_read_value_) { \
  740. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register33_REG_ADDR) >> 1; \
  741. _ezchip_macro_read_value_ &= 0x1;\
  742. }
  743. #define _SET_SYSCON_REG_register33_sdio0_SCFG_sram_config(v) { \
  744. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register33_REG_ADDR); \
  745. _ezchip_macro_read_value_ &= ~(0xFF<<2); \
  746. _ezchip_macro_read_value_ |= (v&0xFF)<<2; \
  747. MA_OUTW(syscon_sysmain_ctrl_register33_REG_ADDR,_ezchip_macro_read_value_); \
  748. }
  749. #define _GET_SYSCON_REG_register33_sdio0_SCFG_sram_config(_ezchip_macro_read_value_) { \
  750. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register33_REG_ADDR) >> 2; \
  751. _ezchip_macro_read_value_ &= 0xff;\
  752. }
  753. #define _SET_SYSCON_REG_register34_SCFG_sdio1_hbig_endian(v) { \
  754. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register34_REG_ADDR); \
  755. _ezchip_macro_read_value_ &= ~(0x1); \
  756. _ezchip_macro_read_value_ |= (v&0x1); \
  757. MA_OUTW(syscon_sysmain_ctrl_register34_REG_ADDR,_ezchip_macro_read_value_); \
  758. }
  759. #define _GET_SYSCON_REG_register34_SCFG_sdio1_hbig_endian(_ezchip_macro_read_value_) { \
  760. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register34_REG_ADDR); \
  761. _ezchip_macro_read_value_ &= 0x1;\
  762. }
  763. #define _SET_SYSCON_REG_register34_SCFG_sdio1_m_hbig_endian(v) { \
  764. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register34_REG_ADDR); \
  765. _ezchip_macro_read_value_ &= ~(0x1<<1); \
  766. _ezchip_macro_read_value_ |= (v&0x1)<<1; \
  767. MA_OUTW(syscon_sysmain_ctrl_register34_REG_ADDR,_ezchip_macro_read_value_); \
  768. }
  769. #define _GET_SYSCON_REG_register34_SCFG_sdio1_m_hbig_endian(_ezchip_macro_read_value_) { \
  770. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register34_REG_ADDR) >> 1; \
  771. _ezchip_macro_read_value_ &= 0x1;\
  772. }
  773. #define _SET_SYSCON_REG_register34_sdio1_SCFG_sram_config(v) { \
  774. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register34_REG_ADDR); \
  775. _ezchip_macro_read_value_ &= ~(0xFF<<2); \
  776. _ezchip_macro_read_value_ |= (v&0xFF)<<2; \
  777. MA_OUTW(syscon_sysmain_ctrl_register34_REG_ADDR,_ezchip_macro_read_value_); \
  778. }
  779. #define _GET_SYSCON_REG_register34_sdio1_SCFG_sram_config(_ezchip_macro_read_value_) { \
  780. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register34_REG_ADDR) >> 2; \
  781. _ezchip_macro_read_value_ &= 0xff;\
  782. }
  783. #define _SET_SYSCON_REG_register35_SCFG_spi2ahb_mode(v) { \
  784. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register35_REG_ADDR); \
  785. _ezchip_macro_read_value_ &= ~(0x3); \
  786. _ezchip_macro_read_value_ |= (v&0x3); \
  787. MA_OUTW(syscon_sysmain_ctrl_register35_REG_ADDR,_ezchip_macro_read_value_); \
  788. }
  789. #define _GET_SYSCON_REG_register35_SCFG_spi2ahb_mode(_ezchip_macro_read_value_) { \
  790. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register35_REG_ADDR); \
  791. _ezchip_macro_read_value_ &= 0x3;\
  792. }
  793. #define _GET_SYSCON_REG_register36_spi2ahb_sleep(_ezchip_macro_read_value_) { \
  794. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register36_REG_ADDR); \
  795. _ezchip_macro_read_value_ &= 0x1;\
  796. }
  797. #define _SET_SYSCON_REG_register37_ezmst_SCFG_sram_config(v) { \
  798. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register37_REG_ADDR); \
  799. _ezchip_macro_read_value_ &= ~(0xFF); \
  800. _ezchip_macro_read_value_ |= (v&0xFF); \
  801. MA_OUTW(syscon_sysmain_ctrl_register37_REG_ADDR,_ezchip_macro_read_value_); \
  802. }
  803. #define _GET_SYSCON_REG_register37_ezmst_SCFG_sram_config(_ezchip_macro_read_value_) { \
  804. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register37_REG_ADDR); \
  805. _ezchip_macro_read_value_ &= 0xff;\
  806. }
  807. #define _SET_SYSCON_REG_register38_sec_SCFG_sram_cfg(v) { \
  808. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register38_REG_ADDR); \
  809. _ezchip_macro_read_value_ &= ~(0xFF); \
  810. _ezchip_macro_read_value_ |= (v&0xFF); \
  811. MA_OUTW(syscon_sysmain_ctrl_register38_REG_ADDR,_ezchip_macro_read_value_); \
  812. }
  813. #define _GET_SYSCON_REG_register38_sec_SCFG_sram_cfg(_ezchip_macro_read_value_) { \
  814. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register38_REG_ADDR); \
  815. _ezchip_macro_read_value_ &= 0xff;\
  816. }
  817. #define _SET_SYSCON_REG_register39_uart0_SCFG_sram_config(v) { \
  818. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register39_REG_ADDR); \
  819. _ezchip_macro_read_value_ &= ~(0xFF); \
  820. _ezchip_macro_read_value_ |= (v&0xFF); \
  821. MA_OUTW(syscon_sysmain_ctrl_register39_REG_ADDR,_ezchip_macro_read_value_); \
  822. }
  823. #define _GET_SYSCON_REG_register39_uart0_SCFG_sram_config(_ezchip_macro_read_value_) { \
  824. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register39_REG_ADDR); \
  825. _ezchip_macro_read_value_ &= 0xff;\
  826. }
  827. #define _SET_SYSCON_REG_register39_uart1_SCFG_sram_config(v) { \
  828. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register39_REG_ADDR); \
  829. _ezchip_macro_read_value_ &= ~(0xFF<<8); \
  830. _ezchip_macro_read_value_ |= (v&0xFF)<<8; \
  831. MA_OUTW(syscon_sysmain_ctrl_register39_REG_ADDR,_ezchip_macro_read_value_); \
  832. }
  833. #define _GET_SYSCON_REG_register39_uart1_SCFG_sram_config(_ezchip_macro_read_value_) { \
  834. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register39_REG_ADDR) >> 8; \
  835. _ezchip_macro_read_value_ &= 0xff;\
  836. }
  837. #define _GET_SYSCON_REG_register40_trng_secure_mode(_ezchip_macro_read_value_) { \
  838. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register40_REG_ADDR); \
  839. _ezchip_macro_read_value_ &= 0x1;\
  840. }
  841. #define _GET_SYSCON_REG_register40_trng_nonce_mode(_ezchip_macro_read_value_) { \
  842. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register40_REG_ADDR) >> 1; \
  843. _ezchip_macro_read_value_ &= 0x1;\
  844. }
  845. #define _SET_SYSCON_REG_SCFG_intC1_7to0_int_src1(v) { \
  846. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_intC1_7to0_REG_ADDR); \
  847. _ezchip_macro_read_value_ &= ~(0xFF); \
  848. _ezchip_macro_read_value_ |= (v&0xFF); \
  849. MA_OUTW(syscon_sysmain_ctrl_SCFG_intC1_7to0_REG_ADDR,_ezchip_macro_read_value_); \
  850. }
  851. #define _GET_SYSCON_REG_SCFG_intC1_7to0_int_src1(_ezchip_macro_read_value_) { \
  852. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_intC1_7to0_REG_ADDR); \
  853. _ezchip_macro_read_value_ &= 0xff;\
  854. }
  855. #define _SET_SYSCON_REG_SCFG_intC0_src15to8_int_src1(v) { \
  856. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_intC0_src15to8_REG_ADDR); \
  857. _ezchip_macro_read_value_ &= ~(0xFF); \
  858. _ezchip_macro_read_value_ |= (v&0xFF); \
  859. MA_OUTW(syscon_sysmain_ctrl_SCFG_intC0_src15to8_REG_ADDR,_ezchip_macro_read_value_); \
  860. }
  861. #define _GET_SYSCON_REG_SCFG_intC0_src15to8_int_src1(_ezchip_macro_read_value_) { \
  862. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_intC0_src15to8_REG_ADDR); \
  863. _ezchip_macro_read_value_ &= 0xff;\
  864. }
  865. #define _SET_SYSCON_REG_SCFG_intC0_src23to16_int_src1(v) { \
  866. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_intC0_src23to16_REG_ADDR); \
  867. _ezchip_macro_read_value_ &= ~(0xFF); \
  868. _ezchip_macro_read_value_ |= (v&0xFF); \
  869. MA_OUTW(syscon_sysmain_ctrl_SCFG_intC0_src23to16_REG_ADDR,_ezchip_macro_read_value_); \
  870. }
  871. #define _GET_SYSCON_REG_SCFG_intC0_src23to16_int_src1(_ezchip_macro_read_value_) { \
  872. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_intC0_src23to16_REG_ADDR); \
  873. _ezchip_macro_read_value_ &= 0xff;\
  874. }
  875. #define _SET_SYSCON_REG_SCFG_intC0_src31to24_int_src1(v) { \
  876. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_intC0_src31to24_REG_ADDR); \
  877. _ezchip_macro_read_value_ &= ~(0xFF); \
  878. _ezchip_macro_read_value_ |= (v&0xFF); \
  879. MA_OUTW(syscon_sysmain_ctrl_SCFG_intC0_src31to24_REG_ADDR,_ezchip_macro_read_value_); \
  880. }
  881. #define _GET_SYSCON_REG_SCFG_intC0_src31to24_int_src1(_ezchip_macro_read_value_) { \
  882. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_intC0_src31to24_REG_ADDR); \
  883. _ezchip_macro_read_value_ &= 0xff;\
  884. }
  885. #define _SET_SYSCON_REG_register47_e24_reset_vector(v) { \
  886. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register47_REG_ADDR); \
  887. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  888. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  889. MA_OUTW(syscon_sysmain_ctrl_register47_REG_ADDR,_ezchip_macro_read_value_); \
  890. }
  891. #define _GET_SYSCON_REG_register47_e24_reset_vector(_ezchip_macro_read_value_) { \
  892. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register47_REG_ADDR); \
  893. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  894. }
  895. #define _SET_SYSCON_REG_register48_SCFG_qspi_sclk_dlychain_sel(v) { \
  896. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register48_REG_ADDR); \
  897. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  898. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  899. MA_OUTW(syscon_sysmain_ctrl_register48_REG_ADDR,_ezchip_macro_read_value_); \
  900. }
  901. #define _GET_SYSCON_REG_register48_SCFG_qspi_sclk_dlychain_sel(_ezchip_macro_read_value_) { \
  902. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register48_REG_ADDR); \
  903. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  904. }
  905. #define _SET_SYSCON_REG_register52_SCFG_gmac_rxclk_dlychain_sel(v) { \
  906. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register52_REG_ADDR); \
  907. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  908. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  909. MA_OUTW(syscon_sysmain_ctrl_register52_REG_ADDR,_ezchip_macro_read_value_); \
  910. }
  911. #define _GET_SYSCON_REG_register52_SCFG_gmac_rxclk_dlychain_sel(_ezchip_macro_read_value_) { \
  912. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register52_REG_ADDR); \
  913. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  914. }
  915. #define _SET_SYSCON_REG_register49_SCFG_gmac_gtxclk_dlychain_sel(v) { \
  916. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register49_REG_ADDR); \
  917. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  918. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  919. MA_OUTW(syscon_sysmain_ctrl_register49_REG_ADDR,_ezchip_macro_read_value_); \
  920. }
  921. #define _GET_SYSCON_REG_register49_SCFG_gmac_gtxclk_dlychain_sel(_ezchip_macro_read_value_) { \
  922. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register49_REG_ADDR); \
  923. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  924. }
  925. #define _SET_SYSCON_REG_register50_SCFG_sdio0_cclk_dlychain_sel(v) { \
  926. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register50_REG_ADDR); \
  927. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  928. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  929. MA_OUTW(syscon_sysmain_ctrl_register50_REG_ADDR,_ezchip_macro_read_value_); \
  930. }
  931. #define _GET_SYSCON_REG_register50_SCFG_sdio0_cclk_dlychain_sel(_ezchip_macro_read_value_) { \
  932. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register50_REG_ADDR); \
  933. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  934. }
  935. #define _SET_SYSCON_REG_register51_SCFG_sdio1_cclk_dlychain_sel(v) { \
  936. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register51_REG_ADDR); \
  937. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  938. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  939. MA_OUTW(syscon_sysmain_ctrl_register51_REG_ADDR,_ezchip_macro_read_value_); \
  940. }
  941. #define _GET_SYSCON_REG_register51_SCFG_sdio1_cclk_dlychain_sel(_ezchip_macro_read_value_) { \
  942. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register51_REG_ADDR); \
  943. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  944. }
  945. #define _SET_SYSCON_REG_register66_SCFG_axi_cache_sel(v) { \
  946. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register66_REG_ADDR); \
  947. _ezchip_macro_read_value_ &= ~(0xFF); \
  948. _ezchip_macro_read_value_ |= (v&0xFF); \
  949. MA_OUTW(syscon_sysmain_ctrl_register66_REG_ADDR,_ezchip_macro_read_value_); \
  950. }
  951. #define _GET_SYSCON_REG_register66_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  952. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register66_REG_ADDR); \
  953. _ezchip_macro_read_value_ &= 0xff;\
  954. }
  955. #define _SET_SYSCON_REG_register66_SCFG_default_arcache(v) { \
  956. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register66_REG_ADDR); \
  957. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  958. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  959. MA_OUTW(syscon_sysmain_ctrl_register66_REG_ADDR,_ezchip_macro_read_value_); \
  960. }
  961. #define _GET_SYSCON_REG_register66_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  962. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register66_REG_ADDR) >> 8; \
  963. _ezchip_macro_read_value_ &= 0xf;\
  964. }
  965. #define _SET_SYSCON_REG_register66_SCFG_default_awcache(v) { \
  966. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register66_REG_ADDR); \
  967. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  968. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  969. MA_OUTW(syscon_sysmain_ctrl_register66_REG_ADDR,_ezchip_macro_read_value_); \
  970. }
  971. #define _GET_SYSCON_REG_register66_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  972. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register66_REG_ADDR) >> 12; \
  973. _ezchip_macro_read_value_ &= 0xf;\
  974. }
  975. #define _SET_SYSCON_REG_register53_SCFG_axi_cache_sel(v) { \
  976. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register53_REG_ADDR); \
  977. _ezchip_macro_read_value_ &= ~(0xFF); \
  978. _ezchip_macro_read_value_ |= (v&0xFF); \
  979. MA_OUTW(syscon_sysmain_ctrl_register53_REG_ADDR,_ezchip_macro_read_value_); \
  980. }
  981. #define _GET_SYSCON_REG_register53_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  982. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register53_REG_ADDR); \
  983. _ezchip_macro_read_value_ &= 0xff;\
  984. }
  985. #define _SET_SYSCON_REG_register53_SCFG_default_arcache(v) { \
  986. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register53_REG_ADDR); \
  987. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  988. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  989. MA_OUTW(syscon_sysmain_ctrl_register53_REG_ADDR,_ezchip_macro_read_value_); \
  990. }
  991. #define _GET_SYSCON_REG_register53_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  992. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register53_REG_ADDR) >> 8; \
  993. _ezchip_macro_read_value_ &= 0xf;\
  994. }
  995. #define _SET_SYSCON_REG_register53_SCFG_default_awcache(v) { \
  996. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register53_REG_ADDR); \
  997. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  998. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  999. MA_OUTW(syscon_sysmain_ctrl_register53_REG_ADDR,_ezchip_macro_read_value_); \
  1000. }
  1001. #define _GET_SYSCON_REG_register53_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1002. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register53_REG_ADDR) >> 12; \
  1003. _ezchip_macro_read_value_ &= 0xf;\
  1004. }
  1005. #define _SET_SYSCON_REG_register54_SCFG_axi_cache_sel(v) { \
  1006. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register54_REG_ADDR); \
  1007. _ezchip_macro_read_value_ &= ~(0xFF); \
  1008. _ezchip_macro_read_value_ |= (v&0xFF); \
  1009. MA_OUTW(syscon_sysmain_ctrl_register54_REG_ADDR,_ezchip_macro_read_value_); \
  1010. }
  1011. #define _GET_SYSCON_REG_register54_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1012. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register54_REG_ADDR); \
  1013. _ezchip_macro_read_value_ &= 0xff;\
  1014. }
  1015. #define _SET_SYSCON_REG_register54_SCFG_default_arcache(v) { \
  1016. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register54_REG_ADDR); \
  1017. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1018. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1019. MA_OUTW(syscon_sysmain_ctrl_register54_REG_ADDR,_ezchip_macro_read_value_); \
  1020. }
  1021. #define _GET_SYSCON_REG_register54_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1022. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register54_REG_ADDR) >> 8; \
  1023. _ezchip_macro_read_value_ &= 0xf;\
  1024. }
  1025. #define _SET_SYSCON_REG_register54_SCFG_default_awcache(v) { \
  1026. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register54_REG_ADDR); \
  1027. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1028. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1029. MA_OUTW(syscon_sysmain_ctrl_register54_REG_ADDR,_ezchip_macro_read_value_); \
  1030. }
  1031. #define _GET_SYSCON_REG_register54_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1032. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register54_REG_ADDR) >> 12; \
  1033. _ezchip_macro_read_value_ &= 0xf;\
  1034. }
  1035. #define _SET_SYSCON_REG_register55_SCFG_axi_cache_sel(v) { \
  1036. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register55_REG_ADDR); \
  1037. _ezchip_macro_read_value_ &= ~(0xFF); \
  1038. _ezchip_macro_read_value_ |= (v&0xFF); \
  1039. MA_OUTW(syscon_sysmain_ctrl_register55_REG_ADDR,_ezchip_macro_read_value_); \
  1040. }
  1041. #define _GET_SYSCON_REG_register55_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1042. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register55_REG_ADDR); \
  1043. _ezchip_macro_read_value_ &= 0xff;\
  1044. }
  1045. #define _SET_SYSCON_REG_register55_SCFG_default_arcache(v) { \
  1046. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register55_REG_ADDR); \
  1047. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1048. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1049. MA_OUTW(syscon_sysmain_ctrl_register55_REG_ADDR,_ezchip_macro_read_value_); \
  1050. }
  1051. #define _GET_SYSCON_REG_register55_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1052. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register55_REG_ADDR) >> 8; \
  1053. _ezchip_macro_read_value_ &= 0xf;\
  1054. }
  1055. #define _SET_SYSCON_REG_register55_SCFG_default_awcache(v) { \
  1056. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register55_REG_ADDR); \
  1057. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1058. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1059. MA_OUTW(syscon_sysmain_ctrl_register55_REG_ADDR,_ezchip_macro_read_value_); \
  1060. }
  1061. #define _GET_SYSCON_REG_register55_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1062. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register55_REG_ADDR) >> 12; \
  1063. _ezchip_macro_read_value_ &= 0xf;\
  1064. }
  1065. #define _SET_SYSCON_REG_register56_SCFG_axi_cache_sel(v) { \
  1066. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register56_REG_ADDR); \
  1067. _ezchip_macro_read_value_ &= ~(0xFF); \
  1068. _ezchip_macro_read_value_ |= (v&0xFF); \
  1069. MA_OUTW(syscon_sysmain_ctrl_register56_REG_ADDR,_ezchip_macro_read_value_); \
  1070. }
  1071. #define _GET_SYSCON_REG_register56_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1072. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register56_REG_ADDR); \
  1073. _ezchip_macro_read_value_ &= 0xff;\
  1074. }
  1075. #define _SET_SYSCON_REG_register56_SCFG_default_arcache(v) { \
  1076. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register56_REG_ADDR); \
  1077. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1078. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1079. MA_OUTW(syscon_sysmain_ctrl_register56_REG_ADDR,_ezchip_macro_read_value_); \
  1080. }
  1081. #define _GET_SYSCON_REG_register56_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1082. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register56_REG_ADDR) >> 8; \
  1083. _ezchip_macro_read_value_ &= 0xf;\
  1084. }
  1085. #define _SET_SYSCON_REG_register56_SCFG_default_awcache(v) { \
  1086. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register56_REG_ADDR); \
  1087. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1088. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1089. MA_OUTW(syscon_sysmain_ctrl_register56_REG_ADDR,_ezchip_macro_read_value_); \
  1090. }
  1091. #define _GET_SYSCON_REG_register56_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1092. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register56_REG_ADDR) >> 12; \
  1093. _ezchip_macro_read_value_ &= 0xf;\
  1094. }
  1095. #define _SET_SYSCON_REG_register57_SCFG_axi_cache_sel(v) { \
  1096. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register57_REG_ADDR); \
  1097. _ezchip_macro_read_value_ &= ~(0xFF); \
  1098. _ezchip_macro_read_value_ |= (v&0xFF); \
  1099. MA_OUTW(syscon_sysmain_ctrl_register57_REG_ADDR,_ezchip_macro_read_value_); \
  1100. }
  1101. #define _GET_SYSCON_REG_register57_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1102. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register57_REG_ADDR); \
  1103. _ezchip_macro_read_value_ &= 0xff;\
  1104. }
  1105. #define _SET_SYSCON_REG_register57_SCFG_default_arcache(v) { \
  1106. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register57_REG_ADDR); \
  1107. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1108. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1109. MA_OUTW(syscon_sysmain_ctrl_register57_REG_ADDR,_ezchip_macro_read_value_); \
  1110. }
  1111. #define _GET_SYSCON_REG_register57_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1112. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register57_REG_ADDR) >> 8; \
  1113. _ezchip_macro_read_value_ &= 0xf;\
  1114. }
  1115. #define _SET_SYSCON_REG_register57_SCFG_default_awcache(v) { \
  1116. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register57_REG_ADDR); \
  1117. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1118. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1119. MA_OUTW(syscon_sysmain_ctrl_register57_REG_ADDR,_ezchip_macro_read_value_); \
  1120. }
  1121. #define _GET_SYSCON_REG_register57_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1122. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register57_REG_ADDR) >> 12; \
  1123. _ezchip_macro_read_value_ &= 0xf;\
  1124. }
  1125. #define _SET_SYSCON_REG_register58_SCFG_axi_cache_sel(v) { \
  1126. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register58_REG_ADDR); \
  1127. _ezchip_macro_read_value_ &= ~(0xFF); \
  1128. _ezchip_macro_read_value_ |= (v&0xFF); \
  1129. MA_OUTW(syscon_sysmain_ctrl_register58_REG_ADDR,_ezchip_macro_read_value_); \
  1130. }
  1131. #define _GET_SYSCON_REG_register58_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1132. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register58_REG_ADDR); \
  1133. _ezchip_macro_read_value_ &= 0xff;\
  1134. }
  1135. #define _SET_SYSCON_REG_register58_SCFG_default_arcache(v) { \
  1136. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register58_REG_ADDR); \
  1137. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1138. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1139. MA_OUTW(syscon_sysmain_ctrl_register58_REG_ADDR,_ezchip_macro_read_value_); \
  1140. }
  1141. #define _GET_SYSCON_REG_register58_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1142. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register58_REG_ADDR) >> 8; \
  1143. _ezchip_macro_read_value_ &= 0xf;\
  1144. }
  1145. #define _SET_SYSCON_REG_register58_SCFG_default_awcache(v) { \
  1146. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register58_REG_ADDR); \
  1147. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1148. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1149. MA_OUTW(syscon_sysmain_ctrl_register58_REG_ADDR,_ezchip_macro_read_value_); \
  1150. }
  1151. #define _GET_SYSCON_REG_register58_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1152. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register58_REG_ADDR) >> 12; \
  1153. _ezchip_macro_read_value_ &= 0xf;\
  1154. }
  1155. #define _SET_SYSCON_REG_register59_SCFG_axi_cache_sel(v) { \
  1156. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register59_REG_ADDR); \
  1157. _ezchip_macro_read_value_ &= ~(0xFF); \
  1158. _ezchip_macro_read_value_ |= (v&0xFF); \
  1159. MA_OUTW(syscon_sysmain_ctrl_register59_REG_ADDR,_ezchip_macro_read_value_); \
  1160. }
  1161. #define _GET_SYSCON_REG_register59_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1162. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register59_REG_ADDR); \
  1163. _ezchip_macro_read_value_ &= 0xff;\
  1164. }
  1165. #define _SET_SYSCON_REG_register59_SCFG_default_arcache(v) { \
  1166. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register59_REG_ADDR); \
  1167. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1168. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1169. MA_OUTW(syscon_sysmain_ctrl_register59_REG_ADDR,_ezchip_macro_read_value_); \
  1170. }
  1171. #define _GET_SYSCON_REG_register59_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1172. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register59_REG_ADDR) >> 8; \
  1173. _ezchip_macro_read_value_ &= 0xf;\
  1174. }
  1175. #define _SET_SYSCON_REG_register59_SCFG_default_awcache(v) { \
  1176. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register59_REG_ADDR); \
  1177. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1178. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1179. MA_OUTW(syscon_sysmain_ctrl_register59_REG_ADDR,_ezchip_macro_read_value_); \
  1180. }
  1181. #define _GET_SYSCON_REG_register59_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1182. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register59_REG_ADDR) >> 12; \
  1183. _ezchip_macro_read_value_ &= 0xf;\
  1184. }
  1185. #define _SET_SYSCON_REG_register60_SCFG_axi_cache_sel(v) { \
  1186. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register60_REG_ADDR); \
  1187. _ezchip_macro_read_value_ &= ~(0xFF); \
  1188. _ezchip_macro_read_value_ |= (v&0xFF); \
  1189. MA_OUTW(syscon_sysmain_ctrl_register60_REG_ADDR,_ezchip_macro_read_value_); \
  1190. }
  1191. #define _GET_SYSCON_REG_register60_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1192. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register60_REG_ADDR); \
  1193. _ezchip_macro_read_value_ &= 0xff;\
  1194. }
  1195. #define _SET_SYSCON_REG_register60_SCFG_default_arcache(v) { \
  1196. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register60_REG_ADDR); \
  1197. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1198. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1199. MA_OUTW(syscon_sysmain_ctrl_register60_REG_ADDR,_ezchip_macro_read_value_); \
  1200. }
  1201. #define _GET_SYSCON_REG_register60_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1202. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register60_REG_ADDR) >> 8; \
  1203. _ezchip_macro_read_value_ &= 0xf;\
  1204. }
  1205. #define _SET_SYSCON_REG_register60_SCFG_default_awcache(v) { \
  1206. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register60_REG_ADDR); \
  1207. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1208. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1209. MA_OUTW(syscon_sysmain_ctrl_register60_REG_ADDR,_ezchip_macro_read_value_); \
  1210. }
  1211. #define _GET_SYSCON_REG_register60_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1212. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register60_REG_ADDR) >> 12; \
  1213. _ezchip_macro_read_value_ &= 0xf;\
  1214. }
  1215. #define _SET_SYSCON_REG_register61_SCFG_axi_cache_sel(v) { \
  1216. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register61_REG_ADDR); \
  1217. _ezchip_macro_read_value_ &= ~(0xFF); \
  1218. _ezchip_macro_read_value_ |= (v&0xFF); \
  1219. MA_OUTW(syscon_sysmain_ctrl_register61_REG_ADDR,_ezchip_macro_read_value_); \
  1220. }
  1221. #define _GET_SYSCON_REG_register61_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1222. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register61_REG_ADDR); \
  1223. _ezchip_macro_read_value_ &= 0xff;\
  1224. }
  1225. #define _SET_SYSCON_REG_register61_SCFG_default_arcache(v) { \
  1226. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register61_REG_ADDR); \
  1227. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1228. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1229. MA_OUTW(syscon_sysmain_ctrl_register61_REG_ADDR,_ezchip_macro_read_value_); \
  1230. }
  1231. #define _GET_SYSCON_REG_register61_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1232. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register61_REG_ADDR) >> 8; \
  1233. _ezchip_macro_read_value_ &= 0xf;\
  1234. }
  1235. #define _SET_SYSCON_REG_register61_SCFG_default_awcache(v) { \
  1236. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register61_REG_ADDR); \
  1237. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1238. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1239. MA_OUTW(syscon_sysmain_ctrl_register61_REG_ADDR,_ezchip_macro_read_value_); \
  1240. }
  1241. #define _GET_SYSCON_REG_register61_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1242. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register61_REG_ADDR) >> 12; \
  1243. _ezchip_macro_read_value_ &= 0xf;\
  1244. }
  1245. #define _SET_SYSCON_REG_register62_SCFG_axi_cache_sel(v) { \
  1246. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register62_REG_ADDR); \
  1247. _ezchip_macro_read_value_ &= ~(0xFF); \
  1248. _ezchip_macro_read_value_ |= (v&0xFF); \
  1249. MA_OUTW(syscon_sysmain_ctrl_register62_REG_ADDR,_ezchip_macro_read_value_); \
  1250. }
  1251. #define _GET_SYSCON_REG_register62_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1252. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register62_REG_ADDR); \
  1253. _ezchip_macro_read_value_ &= 0xff;\
  1254. }
  1255. #define _SET_SYSCON_REG_register62_SCFG_default_arcache(v) { \
  1256. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register62_REG_ADDR); \
  1257. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1258. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1259. MA_OUTW(syscon_sysmain_ctrl_register62_REG_ADDR,_ezchip_macro_read_value_); \
  1260. }
  1261. #define _GET_SYSCON_REG_register62_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1262. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register62_REG_ADDR) >> 8; \
  1263. _ezchip_macro_read_value_ &= 0xf;\
  1264. }
  1265. #define _SET_SYSCON_REG_register62_SCFG_default_awcache(v) { \
  1266. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register62_REG_ADDR); \
  1267. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1268. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1269. MA_OUTW(syscon_sysmain_ctrl_register62_REG_ADDR,_ezchip_macro_read_value_); \
  1270. }
  1271. #define _GET_SYSCON_REG_register62_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1272. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register62_REG_ADDR) >> 12; \
  1273. _ezchip_macro_read_value_ &= 0xf;\
  1274. }
  1275. #define _SET_SYSCON_REG_register63_SCFG_axi_cache_sel(v) { \
  1276. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register63_REG_ADDR); \
  1277. _ezchip_macro_read_value_ &= ~(0xFF); \
  1278. _ezchip_macro_read_value_ |= (v&0xFF); \
  1279. MA_OUTW(syscon_sysmain_ctrl_register63_REG_ADDR,_ezchip_macro_read_value_); \
  1280. }
  1281. #define _GET_SYSCON_REG_register63_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1282. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register63_REG_ADDR); \
  1283. _ezchip_macro_read_value_ &= 0xff;\
  1284. }
  1285. #define _SET_SYSCON_REG_register63_SCFG_default_arcache(v) { \
  1286. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register63_REG_ADDR); \
  1287. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1288. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1289. MA_OUTW(syscon_sysmain_ctrl_register63_REG_ADDR,_ezchip_macro_read_value_); \
  1290. }
  1291. #define _GET_SYSCON_REG_register63_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1292. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register63_REG_ADDR) >> 8; \
  1293. _ezchip_macro_read_value_ &= 0xf;\
  1294. }
  1295. #define _SET_SYSCON_REG_register63_SCFG_default_awcache(v) { \
  1296. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register63_REG_ADDR); \
  1297. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1298. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1299. MA_OUTW(syscon_sysmain_ctrl_register63_REG_ADDR,_ezchip_macro_read_value_); \
  1300. }
  1301. #define _GET_SYSCON_REG_register63_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1302. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register63_REG_ADDR) >> 12; \
  1303. _ezchip_macro_read_value_ &= 0xf;\
  1304. }
  1305. #define _SET_SYSCON_REG_register64_SCFG_axi_cache_sel(v) { \
  1306. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register64_REG_ADDR); \
  1307. _ezchip_macro_read_value_ &= ~(0xFF); \
  1308. _ezchip_macro_read_value_ |= (v&0xFF); \
  1309. MA_OUTW(syscon_sysmain_ctrl_register64_REG_ADDR,_ezchip_macro_read_value_); \
  1310. }
  1311. #define _GET_SYSCON_REG_register64_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1312. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register64_REG_ADDR); \
  1313. _ezchip_macro_read_value_ &= 0xff;\
  1314. }
  1315. #define _SET_SYSCON_REG_register64_SCFG_default_arcache(v) { \
  1316. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register64_REG_ADDR); \
  1317. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1318. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1319. MA_OUTW(syscon_sysmain_ctrl_register64_REG_ADDR,_ezchip_macro_read_value_); \
  1320. }
  1321. #define _GET_SYSCON_REG_register64_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1322. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register64_REG_ADDR) >> 8; \
  1323. _ezchip_macro_read_value_ &= 0xf;\
  1324. }
  1325. #define _SET_SYSCON_REG_register64_SCFG_default_awcache(v) { \
  1326. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register64_REG_ADDR); \
  1327. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1328. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1329. MA_OUTW(syscon_sysmain_ctrl_register64_REG_ADDR,_ezchip_macro_read_value_); \
  1330. }
  1331. #define _GET_SYSCON_REG_register64_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1332. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register64_REG_ADDR) >> 12; \
  1333. _ezchip_macro_read_value_ &= 0xf;\
  1334. }
  1335. #define _SET_SYSCON_REG_register65_SCFG_axi_cache_sel(v) { \
  1336. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register65_REG_ADDR); \
  1337. _ezchip_macro_read_value_ &= ~(0xFF); \
  1338. _ezchip_macro_read_value_ |= (v&0xFF); \
  1339. MA_OUTW(syscon_sysmain_ctrl_register65_REG_ADDR,_ezchip_macro_read_value_); \
  1340. }
  1341. #define _GET_SYSCON_REG_register65_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1342. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register65_REG_ADDR); \
  1343. _ezchip_macro_read_value_ &= 0xff;\
  1344. }
  1345. #define _SET_SYSCON_REG_register65_SCFG_default_arcache(v) { \
  1346. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register65_REG_ADDR); \
  1347. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1348. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1349. MA_OUTW(syscon_sysmain_ctrl_register65_REG_ADDR,_ezchip_macro_read_value_); \
  1350. }
  1351. #define _GET_SYSCON_REG_register65_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1352. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register65_REG_ADDR) >> 8; \
  1353. _ezchip_macro_read_value_ &= 0xf;\
  1354. }
  1355. #define _SET_SYSCON_REG_register65_SCFG_default_awcache(v) { \
  1356. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register65_REG_ADDR); \
  1357. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1358. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1359. MA_OUTW(syscon_sysmain_ctrl_register65_REG_ADDR,_ezchip_macro_read_value_); \
  1360. }
  1361. #define _GET_SYSCON_REG_register65_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1362. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register65_REG_ADDR) >> 12; \
  1363. _ezchip_macro_read_value_ &= 0xf;\
  1364. }
  1365. #define _SET_SYSCON_REG_register68_SCFG_disable_u74_memaxi_remap(v) { \
  1366. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register68_REG_ADDR); \
  1367. _ezchip_macro_read_value_ &= ~(0x1); \
  1368. _ezchip_macro_read_value_ |= (v&0x1); \
  1369. MA_OUTW(syscon_sysmain_ctrl_register68_REG_ADDR,_ezchip_macro_read_value_); \
  1370. }
  1371. #define _GET_SYSCON_REG_register68_SCFG_disable_u74_memaxi_remap(_ezchip_macro_read_value_) { \
  1372. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register68_REG_ADDR); \
  1373. _ezchip_macro_read_value_ &= 0x1;\
  1374. }
  1375. #define _SET_SYSCON_REG_register67_SCFG_axi_cache_sel(v) { \
  1376. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register67_REG_ADDR); \
  1377. _ezchip_macro_read_value_ &= ~(0xFF); \
  1378. _ezchip_macro_read_value_ |= (v&0xFF); \
  1379. MA_OUTW(syscon_sysmain_ctrl_register67_REG_ADDR,_ezchip_macro_read_value_); \
  1380. }
  1381. #define _GET_SYSCON_REG_register67_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1382. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register67_REG_ADDR); \
  1383. _ezchip_macro_read_value_ &= 0xff;\
  1384. }
  1385. #define _SET_SYSCON_REG_register67_SCFG_default_arcache(v) { \
  1386. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register67_REG_ADDR); \
  1387. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1388. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1389. MA_OUTW(syscon_sysmain_ctrl_register67_REG_ADDR,_ezchip_macro_read_value_); \
  1390. }
  1391. #define _GET_SYSCON_REG_register67_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1392. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register67_REG_ADDR) >> 8; \
  1393. _ezchip_macro_read_value_ &= 0xf;\
  1394. }
  1395. #define _SET_SYSCON_REG_register67_SCFG_default_awcache(v) { \
  1396. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register67_REG_ADDR); \
  1397. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1398. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1399. MA_OUTW(syscon_sysmain_ctrl_register67_REG_ADDR,_ezchip_macro_read_value_); \
  1400. }
  1401. #define _GET_SYSCON_REG_register67_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1402. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register67_REG_ADDR) >> 12; \
  1403. _ezchip_macro_read_value_ &= 0xf;\
  1404. }
  1405. #define _SET_SYSCON_REG_register69_core1_en(v) { \
  1406. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register69_REG_ADDR); \
  1407. _ezchip_macro_read_value_ &= ~(0x1); \
  1408. _ezchip_macro_read_value_ |= (v&0x1); \
  1409. MA_OUTW(syscon_sysmain_ctrl_register69_REG_ADDR,_ezchip_macro_read_value_); \
  1410. }
  1411. #define _GET_SYSCON_REG_register69_core1_en(_ezchip_macro_read_value_) { \
  1412. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register69_REG_ADDR); \
  1413. _ezchip_macro_read_value_ &= 0x1;\
  1414. }
  1415. #define _SET_SYSCON_REG_register70_SCFG_boot_mode(v) { \
  1416. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register70_REG_ADDR); \
  1417. _ezchip_macro_read_value_ &= ~(0x1); \
  1418. _ezchip_macro_read_value_ |= (v&0x1); \
  1419. MA_OUTW(syscon_sysmain_ctrl_register70_REG_ADDR,_ezchip_macro_read_value_); \
  1420. }
  1421. #define _GET_SYSCON_REG_register70_SCFG_boot_mode(_ezchip_macro_read_value_) { \
  1422. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register70_REG_ADDR); \
  1423. _ezchip_macro_read_value_ &= 0x1;\
  1424. }
  1425. #define _GET_SYSCON_REG_register70_SCFG_u74_IOPAD_bootmode(_ezchip_macro_read_value_) { \
  1426. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register70_REG_ADDR) >> 1; \
  1427. _ezchip_macro_read_value_ &= 0x1;\
  1428. }
  1429. #define _SET_SYSCON_REG_register71_SCFG_u74_reset_vector(v) { \
  1430. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register71_REG_ADDR); \
  1431. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1432. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1433. MA_OUTW(syscon_sysmain_ctrl_register71_REG_ADDR,_ezchip_macro_read_value_); \
  1434. }
  1435. #define _GET_SYSCON_REG_register71_SCFG_u74_reset_vector(_ezchip_macro_read_value_) { \
  1436. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register71_REG_ADDR); \
  1437. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1438. }
  1439. #define _GET_SYSCON_REG_register72_u74_boot_device_sel(_ezchip_macro_read_value_) { \
  1440. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register72_REG_ADDR); \
  1441. _ezchip_macro_read_value_ &= 0x7;\
  1442. }
  1443. #endif //_SYSCON_SYSMAIN_CTRL_MACRO_H_