syscon_iopad_ctrl_macro.h 65 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /**
  3. ******************************************************************************
  4. * @file syscon_iopad_ctrl_macro.h
  5. * @author StarFive Technology
  6. * @version V1.0
  7. * @date 06/25/2020
  8. * @brief
  9. ******************************************************************************
  10. * @copy
  11. *
  12. * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  13. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  14. * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
  15. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  16. * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  17. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  18. *
  19. * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
  20. */
  21. #ifndef _SYSCON_IOPAD_CTRL_MACRO_H_
  22. #define _SYSCON_IOPAD_CTRL_MACRO_H_
  23. //#define SYSCON_IOPAD_CTRL_BASE_ADDR 0x0
  24. #define syscon_iopad_ctrl_register0_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x0
  25. #define syscon_iopad_ctrl_register1_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x4
  26. #define syscon_iopad_ctrl_register2_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x8
  27. #define syscon_iopad_ctrl_register3_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xC
  28. #define syscon_iopad_ctrl_register4_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x10
  29. #define syscon_iopad_ctrl_register5_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x14
  30. #define syscon_iopad_ctrl_register6_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x18
  31. #define syscon_iopad_ctrl_register7_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x1C
  32. #define syscon_iopad_ctrl_register8_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x20
  33. #define syscon_iopad_ctrl_register9_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x24
  34. #define syscon_iopad_ctrl_register10_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x28
  35. #define syscon_iopad_ctrl_register11_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x2C
  36. #define syscon_iopad_ctrl_register12_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x30
  37. #define syscon_iopad_ctrl_register13_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x34
  38. #define syscon_iopad_ctrl_register14_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x38
  39. #define syscon_iopad_ctrl_register15_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x3C
  40. #define syscon_iopad_ctrl_register16_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x40
  41. #define syscon_iopad_ctrl_register17_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x44
  42. #define syscon_iopad_ctrl_register18_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x48
  43. #define syscon_iopad_ctrl_register19_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x4C
  44. #define syscon_iopad_ctrl_register20_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x50
  45. #define syscon_iopad_ctrl_register21_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x54
  46. #define syscon_iopad_ctrl_register22_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x58
  47. #define syscon_iopad_ctrl_register23_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x5C
  48. #define syscon_iopad_ctrl_register24_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x60
  49. #define syscon_iopad_ctrl_register25_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x64
  50. #define syscon_iopad_ctrl_register26_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x68
  51. #define syscon_iopad_ctrl_register27_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x6C
  52. #define syscon_iopad_ctrl_register28_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x70
  53. #define syscon_iopad_ctrl_register29_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x74
  54. #define syscon_iopad_ctrl_register30_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x78
  55. #define syscon_iopad_ctrl_register31_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x7C
  56. #define syscon_iopad_ctrl_register32_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x80
  57. #define syscon_iopad_ctrl_register33_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x84
  58. #define syscon_iopad_ctrl_register34_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x88
  59. #define syscon_iopad_ctrl_register35_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x8C
  60. #define syscon_iopad_ctrl_register36_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x90
  61. #define syscon_iopad_ctrl_register37_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x94
  62. #define syscon_iopad_ctrl_register38_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x98
  63. #define syscon_iopad_ctrl_register39_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x9C
  64. #define syscon_iopad_ctrl_register40_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xA0
  65. #define syscon_iopad_ctrl_register41_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xA4
  66. #define syscon_iopad_ctrl_register42_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xA8
  67. #define syscon_iopad_ctrl_register43_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xAC
  68. #define syscon_iopad_ctrl_register44_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xB0
  69. #define syscon_iopad_ctrl_register45_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xB4
  70. #define syscon_iopad_ctrl_register46_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xB8
  71. #define syscon_iopad_ctrl_register47_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xBC
  72. #define syscon_iopad_ctrl_register48_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xC0
  73. #define syscon_iopad_ctrl_register49_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xC4
  74. #define syscon_iopad_ctrl_register50_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xC8
  75. #define syscon_iopad_ctrl_register51_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xCC
  76. #define syscon_iopad_ctrl_register52_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xD0
  77. #define syscon_iopad_ctrl_register53_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xD4
  78. #define syscon_iopad_ctrl_register54_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xD8
  79. #define syscon_iopad_ctrl_register55_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xDC
  80. #define syscon_iopad_ctrl_register56_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xE0
  81. #define syscon_iopad_ctrl_register57_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xE4
  82. #define syscon_iopad_ctrl_register58_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xE8
  83. #define syscon_iopad_ctrl_register59_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xEC
  84. #define syscon_iopad_ctrl_register60_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xF0
  85. #define syscon_iopad_ctrl_register61_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xF4
  86. #define syscon_iopad_ctrl_register62_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xF8
  87. #define syscon_iopad_ctrl_register63_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xFC
  88. #define syscon_iopad_ctrl_register64_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x100
  89. #define syscon_iopad_ctrl_register65_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x104
  90. #define syscon_iopad_ctrl_register66_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x108
  91. #define syscon_iopad_ctrl_register67_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x10C
  92. #define syscon_iopad_ctrl_register68_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x110
  93. #define syscon_iopad_ctrl_register69_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x114
  94. #define syscon_iopad_ctrl_register70_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x118
  95. #define syscon_iopad_ctrl_register71_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x11C
  96. #define syscon_iopad_ctrl_register72_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x120
  97. #define syscon_iopad_ctrl_register73_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x124
  98. #define syscon_iopad_ctrl_register74_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x128
  99. #define syscon_iopad_ctrl_register75_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x12C
  100. #define syscon_iopad_ctrl_register76_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x130
  101. #define syscon_iopad_ctrl_register77_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x134
  102. #define syscon_iopad_ctrl_register78_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x138
  103. #define syscon_iopad_ctrl_register79_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x13C
  104. #define syscon_iopad_ctrl_register80_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x140
  105. #define syscon_iopad_ctrl_register81_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x144
  106. #define syscon_iopad_ctrl_register82_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x148
  107. #define syscon_iopad_ctrl_register83_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x14C
  108. #define syscon_iopad_ctrl_register84_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x150
  109. #define syscon_iopad_ctrl_register85_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x154
  110. #define syscon_iopad_ctrl_register86_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x158
  111. #define syscon_iopad_ctrl_register87_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x15C
  112. #define syscon_iopad_ctrl_register88_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x160
  113. #define syscon_iopad_ctrl_register89_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x164
  114. #define syscon_iopad_ctrl_register90_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x168
  115. #define syscon_iopad_ctrl_register91_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x16C
  116. #define syscon_iopad_ctrl_register92_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x170
  117. #define syscon_iopad_ctrl_register93_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x174
  118. #define syscon_iopad_ctrl_register94_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x178
  119. #define syscon_iopad_ctrl_register95_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x17C
  120. #define syscon_iopad_ctrl_register96_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x180
  121. #define syscon_iopad_ctrl_register97_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x184
  122. #define syscon_iopad_ctrl_register98_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x188
  123. #define syscon_iopad_ctrl_register99_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x18C
  124. #define syscon_iopad_ctrl_register100_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x190
  125. #define syscon_iopad_ctrl_register101_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x194
  126. #define syscon_iopad_ctrl_register102_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x198
  127. #define syscon_iopad_ctrl_register103_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x19C
  128. #define syscon_iopad_ctrl_register104_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x1A0
  129. #define _SET_SYSCON_REG_register0_SCFG_gpio_pad_ctrl_0(v) { \
  130. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register0_REG_ADDR); \
  131. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  132. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  133. MA_OUTW(syscon_iopad_ctrl_register0_REG_ADDR,_ezchip_macro_read_value_); \
  134. }
  135. #define _GET_SYSCON_REG_register0_SCFG_gpio_pad_ctrl_0(_ezchip_macro_read_value_) { \
  136. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register0_REG_ADDR); \
  137. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  138. }
  139. #define _SET_SYSCON_REG_register1_SCFG_gpio_pad_ctrl_1(v) { \
  140. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register1_REG_ADDR); \
  141. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  142. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  143. MA_OUTW(syscon_iopad_ctrl_register1_REG_ADDR,_ezchip_macro_read_value_); \
  144. }
  145. #define _GET_SYSCON_REG_register1_SCFG_gpio_pad_ctrl_1(_ezchip_macro_read_value_) { \
  146. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register1_REG_ADDR); \
  147. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  148. }
  149. #define _SET_SYSCON_REG_register2_SCFG_gpio_pad_ctrl_2(v) { \
  150. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register2_REG_ADDR); \
  151. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  152. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  153. MA_OUTW(syscon_iopad_ctrl_register2_REG_ADDR,_ezchip_macro_read_value_); \
  154. }
  155. #define _GET_SYSCON_REG_register2_SCFG_gpio_pad_ctrl_2(_ezchip_macro_read_value_) { \
  156. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register2_REG_ADDR); \
  157. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  158. }
  159. #define _SET_SYSCON_REG_register3_SCFG_gpio_pad_ctrl_3(v) { \
  160. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register3_REG_ADDR); \
  161. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  162. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  163. MA_OUTW(syscon_iopad_ctrl_register3_REG_ADDR,_ezchip_macro_read_value_); \
  164. }
  165. #define _GET_SYSCON_REG_register3_SCFG_gpio_pad_ctrl_3(_ezchip_macro_read_value_) { \
  166. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register3_REG_ADDR); \
  167. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  168. }
  169. #define _SET_SYSCON_REG_register4_SCFG_gpio_pad_ctrl_4(v) { \
  170. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register4_REG_ADDR); \
  171. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  172. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  173. MA_OUTW(syscon_iopad_ctrl_register4_REG_ADDR,_ezchip_macro_read_value_); \
  174. }
  175. #define _GET_SYSCON_REG_register4_SCFG_gpio_pad_ctrl_4(_ezchip_macro_read_value_) { \
  176. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register4_REG_ADDR); \
  177. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  178. }
  179. #define _SET_SYSCON_REG_register5_SCFG_gpio_pad_ctrl_5(v) { \
  180. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register5_REG_ADDR); \
  181. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  182. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  183. MA_OUTW(syscon_iopad_ctrl_register5_REG_ADDR,_ezchip_macro_read_value_); \
  184. }
  185. #define _GET_SYSCON_REG_register5_SCFG_gpio_pad_ctrl_5(_ezchip_macro_read_value_) { \
  186. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register5_REG_ADDR); \
  187. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  188. }
  189. #define _SET_SYSCON_REG_register6_SCFG_gpio_pad_ctrl_6(v) { \
  190. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register6_REG_ADDR); \
  191. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  192. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  193. MA_OUTW(syscon_iopad_ctrl_register6_REG_ADDR,_ezchip_macro_read_value_); \
  194. }
  195. #define _GET_SYSCON_REG_register6_SCFG_gpio_pad_ctrl_6(_ezchip_macro_read_value_) { \
  196. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register6_REG_ADDR); \
  197. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  198. }
  199. #define _SET_SYSCON_REG_register7_SCFG_gpio_pad_ctrl_7(v) { \
  200. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register7_REG_ADDR); \
  201. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  202. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  203. MA_OUTW(syscon_iopad_ctrl_register7_REG_ADDR,_ezchip_macro_read_value_); \
  204. }
  205. #define _GET_SYSCON_REG_register7_SCFG_gpio_pad_ctrl_7(_ezchip_macro_read_value_) { \
  206. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register7_REG_ADDR); \
  207. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  208. }
  209. #define _SET_SYSCON_REG_register8_SCFG_gpio_pad_ctrl_8(v) { \
  210. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register8_REG_ADDR); \
  211. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  212. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  213. MA_OUTW(syscon_iopad_ctrl_register8_REG_ADDR,_ezchip_macro_read_value_); \
  214. }
  215. #define _GET_SYSCON_REG_register8_SCFG_gpio_pad_ctrl_8(_ezchip_macro_read_value_) { \
  216. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register8_REG_ADDR); \
  217. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  218. }
  219. #define _SET_SYSCON_REG_register9_SCFG_gpio_pad_ctrl_9(v) { \
  220. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register9_REG_ADDR); \
  221. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  222. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  223. MA_OUTW(syscon_iopad_ctrl_register9_REG_ADDR,_ezchip_macro_read_value_); \
  224. }
  225. #define _GET_SYSCON_REG_register9_SCFG_gpio_pad_ctrl_9(_ezchip_macro_read_value_) { \
  226. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register9_REG_ADDR); \
  227. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  228. }
  229. #define _SET_SYSCON_REG_register10_SCFG_gpio_pad_ctrl_10(v) { \
  230. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register10_REG_ADDR); \
  231. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  232. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  233. MA_OUTW(syscon_iopad_ctrl_register10_REG_ADDR,_ezchip_macro_read_value_); \
  234. }
  235. #define _GET_SYSCON_REG_register10_SCFG_gpio_pad_ctrl_10(_ezchip_macro_read_value_) { \
  236. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register10_REG_ADDR); \
  237. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  238. }
  239. #define _SET_SYSCON_REG_register11_SCFG_gpio_pad_ctrl_11(v) { \
  240. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register11_REG_ADDR); \
  241. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  242. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  243. MA_OUTW(syscon_iopad_ctrl_register11_REG_ADDR,_ezchip_macro_read_value_); \
  244. }
  245. #define _GET_SYSCON_REG_register11_SCFG_gpio_pad_ctrl_11(_ezchip_macro_read_value_) { \
  246. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register11_REG_ADDR); \
  247. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  248. }
  249. #define _SET_SYSCON_REG_register12_SCFG_gpio_pad_ctrl_12(v) { \
  250. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register12_REG_ADDR); \
  251. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  252. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  253. MA_OUTW(syscon_iopad_ctrl_register12_REG_ADDR,_ezchip_macro_read_value_); \
  254. }
  255. #define _GET_SYSCON_REG_register12_SCFG_gpio_pad_ctrl_12(_ezchip_macro_read_value_) { \
  256. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register12_REG_ADDR); \
  257. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  258. }
  259. #define _SET_SYSCON_REG_register13_SCFG_gpio_pad_ctrl_13(v) { \
  260. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register13_REG_ADDR); \
  261. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  262. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  263. MA_OUTW(syscon_iopad_ctrl_register13_REG_ADDR,_ezchip_macro_read_value_); \
  264. }
  265. #define _GET_SYSCON_REG_register13_SCFG_gpio_pad_ctrl_13(_ezchip_macro_read_value_) { \
  266. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register13_REG_ADDR); \
  267. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  268. }
  269. #define _SET_SYSCON_REG_register14_SCFG_gpio_pad_ctrl_14(v) { \
  270. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register14_REG_ADDR); \
  271. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  272. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  273. MA_OUTW(syscon_iopad_ctrl_register14_REG_ADDR,_ezchip_macro_read_value_); \
  274. }
  275. #define _GET_SYSCON_REG_register14_SCFG_gpio_pad_ctrl_14(_ezchip_macro_read_value_) { \
  276. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register14_REG_ADDR); \
  277. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  278. }
  279. #define _SET_SYSCON_REG_register15_SCFG_gpio_pad_ctrl_15(v) { \
  280. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register15_REG_ADDR); \
  281. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  282. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  283. MA_OUTW(syscon_iopad_ctrl_register15_REG_ADDR,_ezchip_macro_read_value_); \
  284. }
  285. #define _GET_SYSCON_REG_register15_SCFG_gpio_pad_ctrl_15(_ezchip_macro_read_value_) { \
  286. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register15_REG_ADDR); \
  287. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  288. }
  289. #define _SET_SYSCON_REG_register16_SCFG_gpio_pad_ctrl_16(v) { \
  290. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register16_REG_ADDR); \
  291. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  292. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  293. MA_OUTW(syscon_iopad_ctrl_register16_REG_ADDR,_ezchip_macro_read_value_); \
  294. }
  295. #define _GET_SYSCON_REG_register16_SCFG_gpio_pad_ctrl_16(_ezchip_macro_read_value_) { \
  296. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register16_REG_ADDR); \
  297. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  298. }
  299. #define _SET_SYSCON_REG_register17_SCFG_gpio_pad_ctrl_17(v) { \
  300. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register17_REG_ADDR); \
  301. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  302. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  303. MA_OUTW(syscon_iopad_ctrl_register17_REG_ADDR,_ezchip_macro_read_value_); \
  304. }
  305. #define _GET_SYSCON_REG_register17_SCFG_gpio_pad_ctrl_17(_ezchip_macro_read_value_) { \
  306. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register17_REG_ADDR); \
  307. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  308. }
  309. #define _SET_SYSCON_REG_register18_SCFG_gpio_pad_ctrl_18(v) { \
  310. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register18_REG_ADDR); \
  311. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  312. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  313. MA_OUTW(syscon_iopad_ctrl_register18_REG_ADDR,_ezchip_macro_read_value_); \
  314. }
  315. #define _GET_SYSCON_REG_register18_SCFG_gpio_pad_ctrl_18(_ezchip_macro_read_value_) { \
  316. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register18_REG_ADDR); \
  317. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  318. }
  319. #define _SET_SYSCON_REG_register19_SCFG_gpio_pad_ctrl_19(v) { \
  320. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register19_REG_ADDR); \
  321. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  322. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  323. MA_OUTW(syscon_iopad_ctrl_register19_REG_ADDR,_ezchip_macro_read_value_); \
  324. }
  325. #define _GET_SYSCON_REG_register19_SCFG_gpio_pad_ctrl_19(_ezchip_macro_read_value_) { \
  326. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register19_REG_ADDR); \
  327. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  328. }
  329. #define _SET_SYSCON_REG_register20_SCFG_gpio_pad_ctrl_20(v) { \
  330. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register20_REG_ADDR); \
  331. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  332. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  333. MA_OUTW(syscon_iopad_ctrl_register20_REG_ADDR,_ezchip_macro_read_value_); \
  334. }
  335. #define _GET_SYSCON_REG_register20_SCFG_gpio_pad_ctrl_20(_ezchip_macro_read_value_) { \
  336. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register20_REG_ADDR); \
  337. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  338. }
  339. #define _SET_SYSCON_REG_register21_SCFG_gpio_pad_ctrl_21(v) { \
  340. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register21_REG_ADDR); \
  341. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  342. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  343. MA_OUTW(syscon_iopad_ctrl_register21_REG_ADDR,_ezchip_macro_read_value_); \
  344. }
  345. #define _GET_SYSCON_REG_register21_SCFG_gpio_pad_ctrl_21(_ezchip_macro_read_value_) { \
  346. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register21_REG_ADDR); \
  347. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  348. }
  349. #define _SET_SYSCON_REG_register22_SCFG_gpio_pad_ctrl_22(v) { \
  350. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register22_REG_ADDR); \
  351. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  352. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  353. MA_OUTW(syscon_iopad_ctrl_register22_REG_ADDR,_ezchip_macro_read_value_); \
  354. }
  355. #define _GET_SYSCON_REG_register22_SCFG_gpio_pad_ctrl_22(_ezchip_macro_read_value_) { \
  356. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register22_REG_ADDR); \
  357. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  358. }
  359. #define _SET_SYSCON_REG_register23_SCFG_gpio_pad_ctrl_23(v) { \
  360. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register23_REG_ADDR); \
  361. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  362. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  363. MA_OUTW(syscon_iopad_ctrl_register23_REG_ADDR,_ezchip_macro_read_value_); \
  364. }
  365. #define _GET_SYSCON_REG_register23_SCFG_gpio_pad_ctrl_23(_ezchip_macro_read_value_) { \
  366. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register23_REG_ADDR); \
  367. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  368. }
  369. #define _SET_SYSCON_REG_register24_SCFG_gpio_pad_ctrl_24(v) { \
  370. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register24_REG_ADDR); \
  371. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  372. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  373. MA_OUTW(syscon_iopad_ctrl_register24_REG_ADDR,_ezchip_macro_read_value_); \
  374. }
  375. #define _GET_SYSCON_REG_register24_SCFG_gpio_pad_ctrl_24(_ezchip_macro_read_value_) { \
  376. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register24_REG_ADDR); \
  377. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  378. }
  379. #define _SET_SYSCON_REG_register25_SCFG_gpio_pad_ctrl_25(v) { \
  380. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register25_REG_ADDR); \
  381. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  382. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  383. MA_OUTW(syscon_iopad_ctrl_register25_REG_ADDR,_ezchip_macro_read_value_); \
  384. }
  385. #define _GET_SYSCON_REG_register25_SCFG_gpio_pad_ctrl_25(_ezchip_macro_read_value_) { \
  386. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register25_REG_ADDR); \
  387. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  388. }
  389. #define _SET_SYSCON_REG_register26_SCFG_gpio_pad_ctrl_26(v) { \
  390. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register26_REG_ADDR); \
  391. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  392. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  393. MA_OUTW(syscon_iopad_ctrl_register26_REG_ADDR,_ezchip_macro_read_value_); \
  394. }
  395. #define _GET_SYSCON_REG_register26_SCFG_gpio_pad_ctrl_26(_ezchip_macro_read_value_) { \
  396. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register26_REG_ADDR); \
  397. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  398. }
  399. #define _SET_SYSCON_REG_register27_SCFG_gpio_pad_ctrl_27(v) { \
  400. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register27_REG_ADDR); \
  401. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  402. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  403. MA_OUTW(syscon_iopad_ctrl_register27_REG_ADDR,_ezchip_macro_read_value_); \
  404. }
  405. #define _GET_SYSCON_REG_register27_SCFG_gpio_pad_ctrl_27(_ezchip_macro_read_value_) { \
  406. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register27_REG_ADDR); \
  407. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  408. }
  409. #define _SET_SYSCON_REG_register28_SCFG_gpio_pad_ctrl_28(v) { \
  410. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register28_REG_ADDR); \
  411. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  412. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  413. MA_OUTW(syscon_iopad_ctrl_register28_REG_ADDR,_ezchip_macro_read_value_); \
  414. }
  415. #define _GET_SYSCON_REG_register28_SCFG_gpio_pad_ctrl_28(_ezchip_macro_read_value_) { \
  416. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register28_REG_ADDR); \
  417. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  418. }
  419. #define _SET_SYSCON_REG_register29_SCFG_gpio_pad_ctrl_29(v) { \
  420. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register29_REG_ADDR); \
  421. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  422. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  423. MA_OUTW(syscon_iopad_ctrl_register29_REG_ADDR,_ezchip_macro_read_value_); \
  424. }
  425. #define _GET_SYSCON_REG_register29_SCFG_gpio_pad_ctrl_29(_ezchip_macro_read_value_) { \
  426. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register29_REG_ADDR); \
  427. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  428. }
  429. #define _SET_SYSCON_REG_register30_SCFG_gpio_pad_ctrl_30(v) { \
  430. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register30_REG_ADDR); \
  431. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  432. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  433. MA_OUTW(syscon_iopad_ctrl_register30_REG_ADDR,_ezchip_macro_read_value_); \
  434. }
  435. #define _GET_SYSCON_REG_register30_SCFG_gpio_pad_ctrl_30(_ezchip_macro_read_value_) { \
  436. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register30_REG_ADDR); \
  437. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  438. }
  439. #define _SET_SYSCON_REG_register31_SCFG_gpio_pad_ctrl_31(v) { \
  440. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register31_REG_ADDR); \
  441. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  442. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  443. MA_OUTW(syscon_iopad_ctrl_register31_REG_ADDR,_ezchip_macro_read_value_); \
  444. }
  445. #define _GET_SYSCON_REG_register31_SCFG_gpio_pad_ctrl_31(_ezchip_macro_read_value_) { \
  446. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register31_REG_ADDR); \
  447. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  448. }
  449. #define _SET_SYSCON_REG_register32_SCFG_funcshare_pad_ctrl_0(v) { \
  450. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register32_REG_ADDR); \
  451. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  452. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  453. MA_OUTW(syscon_iopad_ctrl_register32_REG_ADDR,_ezchip_macro_read_value_); \
  454. }
  455. #define _GET_SYSCON_REG_register32_SCFG_funcshare_pad_ctrl_0(_ezchip_macro_read_value_) { \
  456. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register32_REG_ADDR); \
  457. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  458. }
  459. #define _SET_SYSCON_REG_register33_SCFG_funcshare_pad_ctrl_1(v) { \
  460. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register33_REG_ADDR); \
  461. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  462. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  463. MA_OUTW(syscon_iopad_ctrl_register33_REG_ADDR,_ezchip_macro_read_value_); \
  464. }
  465. #define _GET_SYSCON_REG_register33_SCFG_funcshare_pad_ctrl_1(_ezchip_macro_read_value_) { \
  466. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register33_REG_ADDR); \
  467. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  468. }
  469. #define _SET_SYSCON_REG_register34_SCFG_funcshare_pad_ctrl_2(v) { \
  470. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register34_REG_ADDR); \
  471. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  472. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  473. MA_OUTW(syscon_iopad_ctrl_register34_REG_ADDR,_ezchip_macro_read_value_); \
  474. }
  475. #define _GET_SYSCON_REG_register34_SCFG_funcshare_pad_ctrl_2(_ezchip_macro_read_value_) { \
  476. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register34_REG_ADDR); \
  477. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  478. }
  479. #define _SET_SYSCON_REG_register35_SCFG_funcshare_pad_ctrl_3(v) { \
  480. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register35_REG_ADDR); \
  481. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  482. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  483. MA_OUTW(syscon_iopad_ctrl_register35_REG_ADDR,_ezchip_macro_read_value_); \
  484. }
  485. #define _GET_SYSCON_REG_register35_SCFG_funcshare_pad_ctrl_3(_ezchip_macro_read_value_) { \
  486. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register35_REG_ADDR); \
  487. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  488. }
  489. #define _SET_SYSCON_REG_register36_SCFG_funcshare_pad_ctrl_4(v) { \
  490. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register36_REG_ADDR); \
  491. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  492. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  493. MA_OUTW(syscon_iopad_ctrl_register36_REG_ADDR,_ezchip_macro_read_value_); \
  494. }
  495. #define _GET_SYSCON_REG_register36_SCFG_funcshare_pad_ctrl_4(_ezchip_macro_read_value_) { \
  496. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register36_REG_ADDR); \
  497. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  498. }
  499. #define _SET_SYSCON_REG_register37_SCFG_funcshare_pad_ctrl_5(v) { \
  500. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register37_REG_ADDR); \
  501. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  502. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  503. MA_OUTW(syscon_iopad_ctrl_register37_REG_ADDR,_ezchip_macro_read_value_); \
  504. }
  505. #define _GET_SYSCON_REG_register37_SCFG_funcshare_pad_ctrl_5(_ezchip_macro_read_value_) { \
  506. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register37_REG_ADDR); \
  507. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  508. }
  509. #define _SET_SYSCON_REG_register38_SCFG_funcshare_pad_ctrl_6(v) { \
  510. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register38_REG_ADDR); \
  511. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  512. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  513. MA_OUTW(syscon_iopad_ctrl_register38_REG_ADDR,_ezchip_macro_read_value_); \
  514. }
  515. #define _GET_SYSCON_REG_register38_SCFG_funcshare_pad_ctrl_6(_ezchip_macro_read_value_) { \
  516. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register38_REG_ADDR); \
  517. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  518. }
  519. #define _SET_SYSCON_REG_register39_SCFG_funcshare_pad_ctrl_7(v) { \
  520. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register39_REG_ADDR); \
  521. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  522. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  523. MA_OUTW(syscon_iopad_ctrl_register39_REG_ADDR,_ezchip_macro_read_value_); \
  524. }
  525. #define _GET_SYSCON_REG_register39_SCFG_funcshare_pad_ctrl_7(_ezchip_macro_read_value_) { \
  526. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register39_REG_ADDR); \
  527. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  528. }
  529. #define _SET_SYSCON_REG_register40_SCFG_funcshare_pad_ctrl_8(v) { \
  530. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register40_REG_ADDR); \
  531. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  532. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  533. MA_OUTW(syscon_iopad_ctrl_register40_REG_ADDR,_ezchip_macro_read_value_); \
  534. }
  535. #define _GET_SYSCON_REG_register40_SCFG_funcshare_pad_ctrl_8(_ezchip_macro_read_value_) { \
  536. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register40_REG_ADDR); \
  537. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  538. }
  539. #define _SET_SYSCON_REG_register41_SCFG_funcshare_pad_ctrl_9(v) { \
  540. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register41_REG_ADDR); \
  541. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  542. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  543. MA_OUTW(syscon_iopad_ctrl_register41_REG_ADDR,_ezchip_macro_read_value_); \
  544. }
  545. #define _GET_SYSCON_REG_register41_SCFG_funcshare_pad_ctrl_9(_ezchip_macro_read_value_) { \
  546. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register41_REG_ADDR); \
  547. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  548. }
  549. #define _SET_SYSCON_REG_register42_SCFG_funcshare_pad_ctrl_10(v) { \
  550. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register42_REG_ADDR); \
  551. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  552. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  553. MA_OUTW(syscon_iopad_ctrl_register42_REG_ADDR,_ezchip_macro_read_value_); \
  554. }
  555. #define _GET_SYSCON_REG_register42_SCFG_funcshare_pad_ctrl_10(_ezchip_macro_read_value_) { \
  556. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register42_REG_ADDR); \
  557. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  558. }
  559. #define _SET_SYSCON_REG_register43_SCFG_funcshare_pad_ctrl_11(v) { \
  560. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register43_REG_ADDR); \
  561. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  562. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  563. MA_OUTW(syscon_iopad_ctrl_register43_REG_ADDR,_ezchip_macro_read_value_); \
  564. }
  565. #define _GET_SYSCON_REG_register43_SCFG_funcshare_pad_ctrl_11(_ezchip_macro_read_value_) { \
  566. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register43_REG_ADDR); \
  567. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  568. }
  569. #define _SET_SYSCON_REG_register44_SCFG_funcshare_pad_ctrl_12(v) { \
  570. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register44_REG_ADDR); \
  571. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  572. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  573. MA_OUTW(syscon_iopad_ctrl_register44_REG_ADDR,_ezchip_macro_read_value_); \
  574. }
  575. #define _GET_SYSCON_REG_register44_SCFG_funcshare_pad_ctrl_12(_ezchip_macro_read_value_) { \
  576. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register44_REG_ADDR); \
  577. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  578. }
  579. #define _SET_SYSCON_REG_register45_SCFG_funcshare_pad_ctrl_13(v) { \
  580. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register45_REG_ADDR); \
  581. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  582. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  583. MA_OUTW(syscon_iopad_ctrl_register45_REG_ADDR,_ezchip_macro_read_value_); \
  584. }
  585. #define _GET_SYSCON_REG_register45_SCFG_funcshare_pad_ctrl_13(_ezchip_macro_read_value_) { \
  586. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register45_REG_ADDR); \
  587. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  588. }
  589. #define _SET_SYSCON_REG_register46_SCFG_funcshare_pad_ctrl_14(v) { \
  590. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register46_REG_ADDR); \
  591. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  592. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  593. MA_OUTW(syscon_iopad_ctrl_register46_REG_ADDR,_ezchip_macro_read_value_); \
  594. }
  595. #define _GET_SYSCON_REG_register46_SCFG_funcshare_pad_ctrl_14(_ezchip_macro_read_value_) { \
  596. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register46_REG_ADDR); \
  597. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  598. }
  599. #define _SET_SYSCON_REG_register47_SCFG_funcshare_pad_ctrl_15(v) { \
  600. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register47_REG_ADDR); \
  601. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  602. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  603. MA_OUTW(syscon_iopad_ctrl_register47_REG_ADDR,_ezchip_macro_read_value_); \
  604. }
  605. #define _GET_SYSCON_REG_register47_SCFG_funcshare_pad_ctrl_15(_ezchip_macro_read_value_) { \
  606. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register47_REG_ADDR); \
  607. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  608. }
  609. #define _SET_SYSCON_REG_register48_SCFG_funcshare_pad_ctrl_16(v) { \
  610. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register48_REG_ADDR); \
  611. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  612. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  613. MA_OUTW(syscon_iopad_ctrl_register48_REG_ADDR,_ezchip_macro_read_value_); \
  614. }
  615. #define _GET_SYSCON_REG_register48_SCFG_funcshare_pad_ctrl_16(_ezchip_macro_read_value_) { \
  616. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register48_REG_ADDR); \
  617. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  618. }
  619. #define _SET_SYSCON_REG_register49_SCFG_funcshare_pad_ctrl_17(v) { \
  620. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register49_REG_ADDR); \
  621. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  622. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  623. MA_OUTW(syscon_iopad_ctrl_register49_REG_ADDR,_ezchip_macro_read_value_); \
  624. }
  625. #define _GET_SYSCON_REG_register49_SCFG_funcshare_pad_ctrl_17(_ezchip_macro_read_value_) { \
  626. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register49_REG_ADDR); \
  627. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  628. }
  629. #define _SET_SYSCON_REG_register50_SCFG_funcshare_pad_ctrl_18(v) { \
  630. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register50_REG_ADDR); \
  631. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  632. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  633. MA_OUTW(syscon_iopad_ctrl_register50_REG_ADDR,_ezchip_macro_read_value_); \
  634. }
  635. #define _GET_SYSCON_REG_register50_SCFG_funcshare_pad_ctrl_18(_ezchip_macro_read_value_) { \
  636. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register50_REG_ADDR); \
  637. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  638. }
  639. #define _SET_SYSCON_REG_register51_SCFG_funcshare_pad_ctrl_19(v) { \
  640. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register51_REG_ADDR); \
  641. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  642. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  643. MA_OUTW(syscon_iopad_ctrl_register51_REG_ADDR,_ezchip_macro_read_value_); \
  644. }
  645. #define _GET_SYSCON_REG_register51_SCFG_funcshare_pad_ctrl_19(_ezchip_macro_read_value_) { \
  646. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register51_REG_ADDR); \
  647. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  648. }
  649. #define _SET_SYSCON_REG_register52_SCFG_funcshare_pad_ctrl_20(v) { \
  650. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register52_REG_ADDR); \
  651. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  652. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  653. MA_OUTW(syscon_iopad_ctrl_register52_REG_ADDR,_ezchip_macro_read_value_); \
  654. }
  655. #define _GET_SYSCON_REG_register52_SCFG_funcshare_pad_ctrl_20(_ezchip_macro_read_value_) { \
  656. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register52_REG_ADDR); \
  657. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  658. }
  659. #define _SET_SYSCON_REG_register53_SCFG_funcshare_pad_ctrl_21(v) { \
  660. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register53_REG_ADDR); \
  661. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  662. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  663. MA_OUTW(syscon_iopad_ctrl_register53_REG_ADDR,_ezchip_macro_read_value_); \
  664. }
  665. #define _GET_SYSCON_REG_register53_SCFG_funcshare_pad_ctrl_21(_ezchip_macro_read_value_) { \
  666. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register53_REG_ADDR); \
  667. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  668. }
  669. #define _SET_SYSCON_REG_register54_SCFG_funcshare_pad_ctrl_22(v) { \
  670. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register54_REG_ADDR); \
  671. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  672. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  673. MA_OUTW(syscon_iopad_ctrl_register54_REG_ADDR,_ezchip_macro_read_value_); \
  674. }
  675. #define _GET_SYSCON_REG_register54_SCFG_funcshare_pad_ctrl_22(_ezchip_macro_read_value_) { \
  676. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register54_REG_ADDR); \
  677. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  678. }
  679. #define _SET_SYSCON_REG_register55_SCFG_funcshare_pad_ctrl_23(v) { \
  680. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register55_REG_ADDR); \
  681. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  682. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  683. MA_OUTW(syscon_iopad_ctrl_register55_REG_ADDR,_ezchip_macro_read_value_); \
  684. }
  685. #define _GET_SYSCON_REG_register55_SCFG_funcshare_pad_ctrl_23(_ezchip_macro_read_value_) { \
  686. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register55_REG_ADDR); \
  687. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  688. }
  689. #define _SET_SYSCON_REG_register56_SCFG_funcshare_pad_ctrl_24(v) { \
  690. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register56_REG_ADDR); \
  691. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  692. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  693. MA_OUTW(syscon_iopad_ctrl_register56_REG_ADDR,_ezchip_macro_read_value_); \
  694. }
  695. #define _GET_SYSCON_REG_register56_SCFG_funcshare_pad_ctrl_24(_ezchip_macro_read_value_) { \
  696. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register56_REG_ADDR); \
  697. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  698. }
  699. #define _SET_SYSCON_REG_register57_SCFG_funcshare_pad_ctrl_25(v) { \
  700. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register57_REG_ADDR); \
  701. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  702. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  703. MA_OUTW(syscon_iopad_ctrl_register57_REG_ADDR,_ezchip_macro_read_value_); \
  704. }
  705. #define _GET_SYSCON_REG_register57_SCFG_funcshare_pad_ctrl_25(_ezchip_macro_read_value_) { \
  706. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register57_REG_ADDR); \
  707. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  708. }
  709. #define _SET_SYSCON_REG_register58_SCFG_funcshare_pad_ctrl_26(v) { \
  710. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register58_REG_ADDR); \
  711. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  712. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  713. MA_OUTW(syscon_iopad_ctrl_register58_REG_ADDR,_ezchip_macro_read_value_); \
  714. }
  715. #define _GET_SYSCON_REG_register58_SCFG_funcshare_pad_ctrl_26(_ezchip_macro_read_value_) { \
  716. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register58_REG_ADDR); \
  717. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  718. }
  719. #define _SET_SYSCON_REG_register59_SCFG_funcshare_pad_ctrl_27(v) { \
  720. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register59_REG_ADDR); \
  721. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  722. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  723. MA_OUTW(syscon_iopad_ctrl_register59_REG_ADDR,_ezchip_macro_read_value_); \
  724. }
  725. #define _GET_SYSCON_REG_register59_SCFG_funcshare_pad_ctrl_27(_ezchip_macro_read_value_) { \
  726. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register59_REG_ADDR); \
  727. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  728. }
  729. #define _SET_SYSCON_REG_register60_SCFG_funcshare_pad_ctrl_28(v) { \
  730. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register60_REG_ADDR); \
  731. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  732. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  733. MA_OUTW(syscon_iopad_ctrl_register60_REG_ADDR,_ezchip_macro_read_value_); \
  734. }
  735. #define _GET_SYSCON_REG_register60_SCFG_funcshare_pad_ctrl_28(_ezchip_macro_read_value_) { \
  736. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register60_REG_ADDR); \
  737. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  738. }
  739. #define _SET_SYSCON_REG_register61_SCFG_funcshare_pad_ctrl_29(v) { \
  740. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register61_REG_ADDR); \
  741. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  742. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  743. MA_OUTW(syscon_iopad_ctrl_register61_REG_ADDR,_ezchip_macro_read_value_); \
  744. }
  745. #define _GET_SYSCON_REG_register61_SCFG_funcshare_pad_ctrl_29(_ezchip_macro_read_value_) { \
  746. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register61_REG_ADDR); \
  747. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  748. }
  749. #define _SET_SYSCON_REG_register62_SCFG_funcshare_pad_ctrl_30(v) { \
  750. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register62_REG_ADDR); \
  751. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  752. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  753. MA_OUTW(syscon_iopad_ctrl_register62_REG_ADDR,_ezchip_macro_read_value_); \
  754. }
  755. #define _GET_SYSCON_REG_register62_SCFG_funcshare_pad_ctrl_30(_ezchip_macro_read_value_) { \
  756. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register62_REG_ADDR); \
  757. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  758. }
  759. #define _SET_SYSCON_REG_register63_SCFG_funcshare_pad_ctrl_31(v) { \
  760. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register63_REG_ADDR); \
  761. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  762. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  763. MA_OUTW(syscon_iopad_ctrl_register63_REG_ADDR,_ezchip_macro_read_value_); \
  764. }
  765. #define _GET_SYSCON_REG_register63_SCFG_funcshare_pad_ctrl_31(_ezchip_macro_read_value_) { \
  766. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register63_REG_ADDR); \
  767. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  768. }
  769. #define _SET_SYSCON_REG_register64_SCFG_funcshare_pad_ctrl_32(v) { \
  770. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register64_REG_ADDR); \
  771. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  772. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  773. MA_OUTW(syscon_iopad_ctrl_register64_REG_ADDR,_ezchip_macro_read_value_); \
  774. }
  775. #define _GET_SYSCON_REG_register64_SCFG_funcshare_pad_ctrl_32(_ezchip_macro_read_value_) { \
  776. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register64_REG_ADDR); \
  777. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  778. }
  779. #define _SET_SYSCON_REG_register65_SCFG_funcshare_pad_ctrl_33(v) { \
  780. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register65_REG_ADDR); \
  781. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  782. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  783. MA_OUTW(syscon_iopad_ctrl_register65_REG_ADDR,_ezchip_macro_read_value_); \
  784. }
  785. #define _GET_SYSCON_REG_register65_SCFG_funcshare_pad_ctrl_33(_ezchip_macro_read_value_) { \
  786. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register65_REG_ADDR); \
  787. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  788. }
  789. #define _SET_SYSCON_REG_register66_SCFG_funcshare_pad_ctrl_34(v) { \
  790. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register66_REG_ADDR); \
  791. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  792. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  793. MA_OUTW(syscon_iopad_ctrl_register66_REG_ADDR,_ezchip_macro_read_value_); \
  794. }
  795. #define _GET_SYSCON_REG_register66_SCFG_funcshare_pad_ctrl_34(_ezchip_macro_read_value_) { \
  796. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register66_REG_ADDR); \
  797. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  798. }
  799. #define _SET_SYSCON_REG_register67_SCFG_funcshare_pad_ctrl_35(v) { \
  800. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register67_REG_ADDR); \
  801. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  802. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  803. MA_OUTW(syscon_iopad_ctrl_register67_REG_ADDR,_ezchip_macro_read_value_); \
  804. }
  805. #define _GET_SYSCON_REG_register67_SCFG_funcshare_pad_ctrl_35(_ezchip_macro_read_value_) { \
  806. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register67_REG_ADDR); \
  807. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  808. }
  809. #define _SET_SYSCON_REG_register68_SCFG_funcshare_pad_ctrl_36(v) { \
  810. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register68_REG_ADDR); \
  811. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  812. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  813. MA_OUTW(syscon_iopad_ctrl_register68_REG_ADDR,_ezchip_macro_read_value_); \
  814. }
  815. #define _GET_SYSCON_REG_register68_SCFG_funcshare_pad_ctrl_36(_ezchip_macro_read_value_) { \
  816. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register68_REG_ADDR); \
  817. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  818. }
  819. #define _SET_SYSCON_REG_register69_SCFG_funcshare_pad_ctrl_37(v) { \
  820. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register69_REG_ADDR); \
  821. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  822. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  823. MA_OUTW(syscon_iopad_ctrl_register69_REG_ADDR,_ezchip_macro_read_value_); \
  824. }
  825. #define _GET_SYSCON_REG_register69_SCFG_funcshare_pad_ctrl_37(_ezchip_macro_read_value_) { \
  826. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register69_REG_ADDR); \
  827. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  828. }
  829. #define _SET_SYSCON_REG_register70_SCFG_funcshare_pad_ctrl_38(v) { \
  830. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register70_REG_ADDR); \
  831. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  832. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  833. MA_OUTW(syscon_iopad_ctrl_register70_REG_ADDR,_ezchip_macro_read_value_); \
  834. }
  835. #define _GET_SYSCON_REG_register70_SCFG_funcshare_pad_ctrl_38(_ezchip_macro_read_value_) { \
  836. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register70_REG_ADDR); \
  837. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  838. }
  839. #define _SET_SYSCON_REG_register71_SCFG_funcshare_pad_ctrl_39(v) { \
  840. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register71_REG_ADDR); \
  841. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  842. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  843. MA_OUTW(syscon_iopad_ctrl_register71_REG_ADDR,_ezchip_macro_read_value_); \
  844. }
  845. #define _GET_SYSCON_REG_register71_SCFG_funcshare_pad_ctrl_39(_ezchip_macro_read_value_) { \
  846. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register71_REG_ADDR); \
  847. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  848. }
  849. #define _SET_SYSCON_REG_register72_SCFG_funcshare_pad_ctrl_40(v) { \
  850. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register72_REG_ADDR); \
  851. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  852. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  853. MA_OUTW(syscon_iopad_ctrl_register72_REG_ADDR,_ezchip_macro_read_value_); \
  854. }
  855. #define _GET_SYSCON_REG_register72_SCFG_funcshare_pad_ctrl_40(_ezchip_macro_read_value_) { \
  856. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register72_REG_ADDR); \
  857. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  858. }
  859. #define _SET_SYSCON_REG_register73_SCFG_funcshare_pad_ctrl_41(v) { \
  860. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register73_REG_ADDR); \
  861. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  862. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  863. MA_OUTW(syscon_iopad_ctrl_register73_REG_ADDR,_ezchip_macro_read_value_); \
  864. }
  865. #define _GET_SYSCON_REG_register73_SCFG_funcshare_pad_ctrl_41(_ezchip_macro_read_value_) { \
  866. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register73_REG_ADDR); \
  867. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  868. }
  869. #define _SET_SYSCON_REG_register74_SCFG_funcshare_pad_ctrl_42(v) { \
  870. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register74_REG_ADDR); \
  871. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  872. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  873. MA_OUTW(syscon_iopad_ctrl_register74_REG_ADDR,_ezchip_macro_read_value_); \
  874. }
  875. #define _GET_SYSCON_REG_register74_SCFG_funcshare_pad_ctrl_42(_ezchip_macro_read_value_) { \
  876. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register74_REG_ADDR); \
  877. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  878. }
  879. #define _SET_SYSCON_REG_register75_SCFG_funcshare_pad_ctrl_43(v) { \
  880. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register75_REG_ADDR); \
  881. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  882. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  883. MA_OUTW(syscon_iopad_ctrl_register75_REG_ADDR,_ezchip_macro_read_value_); \
  884. }
  885. #define _GET_SYSCON_REG_register75_SCFG_funcshare_pad_ctrl_43(_ezchip_macro_read_value_) { \
  886. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register75_REG_ADDR); \
  887. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  888. }
  889. #define _SET_SYSCON_REG_register76_SCFG_funcshare_pad_ctrl_44(v) { \
  890. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register76_REG_ADDR); \
  891. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  892. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  893. MA_OUTW(syscon_iopad_ctrl_register76_REG_ADDR,_ezchip_macro_read_value_); \
  894. }
  895. #define _GET_SYSCON_REG_register76_SCFG_funcshare_pad_ctrl_44(_ezchip_macro_read_value_) { \
  896. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register76_REG_ADDR); \
  897. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  898. }
  899. #define _SET_SYSCON_REG_register77_SCFG_funcshare_pad_ctrl_45(v) { \
  900. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register77_REG_ADDR); \
  901. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  902. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  903. MA_OUTW(syscon_iopad_ctrl_register77_REG_ADDR,_ezchip_macro_read_value_); \
  904. }
  905. #define _GET_SYSCON_REG_register77_SCFG_funcshare_pad_ctrl_45(_ezchip_macro_read_value_) { \
  906. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register77_REG_ADDR); \
  907. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  908. }
  909. #define _SET_SYSCON_REG_register78_SCFG_funcshare_pad_ctrl_46(v) { \
  910. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register78_REG_ADDR); \
  911. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  912. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  913. MA_OUTW(syscon_iopad_ctrl_register78_REG_ADDR,_ezchip_macro_read_value_); \
  914. }
  915. #define _GET_SYSCON_REG_register78_SCFG_funcshare_pad_ctrl_46(_ezchip_macro_read_value_) { \
  916. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register78_REG_ADDR); \
  917. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  918. }
  919. #define _SET_SYSCON_REG_register79_SCFG_funcshare_pad_ctrl_47(v) { \
  920. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register79_REG_ADDR); \
  921. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  922. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  923. MA_OUTW(syscon_iopad_ctrl_register79_REG_ADDR,_ezchip_macro_read_value_); \
  924. }
  925. #define _GET_SYSCON_REG_register79_SCFG_funcshare_pad_ctrl_47(_ezchip_macro_read_value_) { \
  926. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register79_REG_ADDR); \
  927. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  928. }
  929. #define _SET_SYSCON_REG_register80_SCFG_funcshare_pad_ctrl_48(v) { \
  930. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register80_REG_ADDR); \
  931. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  932. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  933. MA_OUTW(syscon_iopad_ctrl_register80_REG_ADDR,_ezchip_macro_read_value_); \
  934. }
  935. #define _GET_SYSCON_REG_register80_SCFG_funcshare_pad_ctrl_48(_ezchip_macro_read_value_) { \
  936. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register80_REG_ADDR); \
  937. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  938. }
  939. #define _SET_SYSCON_REG_register81_SCFG_funcshare_pad_ctrl_49(v) { \
  940. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register81_REG_ADDR); \
  941. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  942. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  943. MA_OUTW(syscon_iopad_ctrl_register81_REG_ADDR,_ezchip_macro_read_value_); \
  944. }
  945. #define _GET_SYSCON_REG_register81_SCFG_funcshare_pad_ctrl_49(_ezchip_macro_read_value_) { \
  946. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register81_REG_ADDR); \
  947. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  948. }
  949. #define _SET_SYSCON_REG_register82_SCFG_funcshare_pad_ctrl_50(v) { \
  950. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register82_REG_ADDR); \
  951. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  952. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  953. MA_OUTW(syscon_iopad_ctrl_register82_REG_ADDR,_ezchip_macro_read_value_); \
  954. }
  955. #define _GET_SYSCON_REG_register82_SCFG_funcshare_pad_ctrl_50(_ezchip_macro_read_value_) { \
  956. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register82_REG_ADDR); \
  957. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  958. }
  959. #define _SET_SYSCON_REG_register83_SCFG_funcshare_pad_ctrl_51(v) { \
  960. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register83_REG_ADDR); \
  961. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  962. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  963. MA_OUTW(syscon_iopad_ctrl_register83_REG_ADDR,_ezchip_macro_read_value_); \
  964. }
  965. #define _GET_SYSCON_REG_register83_SCFG_funcshare_pad_ctrl_51(_ezchip_macro_read_value_) { \
  966. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register83_REG_ADDR); \
  967. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  968. }
  969. #define _SET_SYSCON_REG_register84_SCFG_funcshare_pad_ctrl_52(v) { \
  970. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register84_REG_ADDR); \
  971. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  972. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  973. MA_OUTW(syscon_iopad_ctrl_register84_REG_ADDR,_ezchip_macro_read_value_); \
  974. }
  975. #define _GET_SYSCON_REG_register84_SCFG_funcshare_pad_ctrl_52(_ezchip_macro_read_value_) { \
  976. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register84_REG_ADDR); \
  977. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  978. }
  979. #define _SET_SYSCON_REG_register85_SCFG_funcshare_pad_ctrl_53(v) { \
  980. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register85_REG_ADDR); \
  981. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  982. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  983. MA_OUTW(syscon_iopad_ctrl_register85_REG_ADDR,_ezchip_macro_read_value_); \
  984. }
  985. #define _GET_SYSCON_REG_register85_SCFG_funcshare_pad_ctrl_53(_ezchip_macro_read_value_) { \
  986. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register85_REG_ADDR); \
  987. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  988. }
  989. #define _SET_SYSCON_REG_register86_SCFG_funcshare_pad_ctrl_54(v) { \
  990. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register86_REG_ADDR); \
  991. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  992. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  993. MA_OUTW(syscon_iopad_ctrl_register86_REG_ADDR,_ezchip_macro_read_value_); \
  994. }
  995. #define _GET_SYSCON_REG_register86_SCFG_funcshare_pad_ctrl_54(_ezchip_macro_read_value_) { \
  996. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register86_REG_ADDR); \
  997. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  998. }
  999. #define _SET_SYSCON_REG_register87_SCFG_funcshare_pad_ctrl_55(v) { \
  1000. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register87_REG_ADDR); \
  1001. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1002. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1003. MA_OUTW(syscon_iopad_ctrl_register87_REG_ADDR,_ezchip_macro_read_value_); \
  1004. }
  1005. #define _GET_SYSCON_REG_register87_SCFG_funcshare_pad_ctrl_55(_ezchip_macro_read_value_) { \
  1006. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register87_REG_ADDR); \
  1007. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1008. }
  1009. #define _SET_SYSCON_REG_register88_SCFG_funcshare_pad_ctrl_56(v) { \
  1010. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register88_REG_ADDR); \
  1011. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1012. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1013. MA_OUTW(syscon_iopad_ctrl_register88_REG_ADDR,_ezchip_macro_read_value_); \
  1014. }
  1015. #define _GET_SYSCON_REG_register88_SCFG_funcshare_pad_ctrl_56(_ezchip_macro_read_value_) { \
  1016. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register88_REG_ADDR); \
  1017. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1018. }
  1019. #define _SET_SYSCON_REG_register89_SCFG_funcshare_pad_ctrl_57(v) { \
  1020. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register89_REG_ADDR); \
  1021. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1022. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1023. MA_OUTW(syscon_iopad_ctrl_register89_REG_ADDR,_ezchip_macro_read_value_); \
  1024. }
  1025. #define _GET_SYSCON_REG_register89_SCFG_funcshare_pad_ctrl_57(_ezchip_macro_read_value_) { \
  1026. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register89_REG_ADDR); \
  1027. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1028. }
  1029. #define _SET_SYSCON_REG_register90_SCFG_funcshare_pad_ctrl_58(v) { \
  1030. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register90_REG_ADDR); \
  1031. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1032. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1033. MA_OUTW(syscon_iopad_ctrl_register90_REG_ADDR,_ezchip_macro_read_value_); \
  1034. }
  1035. #define _GET_SYSCON_REG_register90_SCFG_funcshare_pad_ctrl_58(_ezchip_macro_read_value_) { \
  1036. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register90_REG_ADDR); \
  1037. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1038. }
  1039. #define _SET_SYSCON_REG_register91_SCFG_funcshare_pad_ctrl_59(v) { \
  1040. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register91_REG_ADDR); \
  1041. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1042. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1043. MA_OUTW(syscon_iopad_ctrl_register91_REG_ADDR,_ezchip_macro_read_value_); \
  1044. }
  1045. #define _GET_SYSCON_REG_register91_SCFG_funcshare_pad_ctrl_59(_ezchip_macro_read_value_) { \
  1046. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register91_REG_ADDR); \
  1047. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1048. }
  1049. #define _SET_SYSCON_REG_register92_SCFG_funcshare_pad_ctrl_60(v) { \
  1050. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register92_REG_ADDR); \
  1051. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1052. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1053. MA_OUTW(syscon_iopad_ctrl_register92_REG_ADDR,_ezchip_macro_read_value_); \
  1054. }
  1055. #define _GET_SYSCON_REG_register92_SCFG_funcshare_pad_ctrl_60(_ezchip_macro_read_value_) { \
  1056. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register92_REG_ADDR); \
  1057. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1058. }
  1059. #define _SET_SYSCON_REG_register93_SCFG_funcshare_pad_ctrl_61(v) { \
  1060. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register93_REG_ADDR); \
  1061. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1062. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1063. MA_OUTW(syscon_iopad_ctrl_register93_REG_ADDR,_ezchip_macro_read_value_); \
  1064. }
  1065. #define _GET_SYSCON_REG_register93_SCFG_funcshare_pad_ctrl_61(_ezchip_macro_read_value_) { \
  1066. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register93_REG_ADDR); \
  1067. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1068. }
  1069. #define _SET_SYSCON_REG_register94_SCFG_funcshare_pad_ctrl_62(v) { \
  1070. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register94_REG_ADDR); \
  1071. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1072. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1073. MA_OUTW(syscon_iopad_ctrl_register94_REG_ADDR,_ezchip_macro_read_value_); \
  1074. }
  1075. #define _GET_SYSCON_REG_register94_SCFG_funcshare_pad_ctrl_62(_ezchip_macro_read_value_) { \
  1076. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register94_REG_ADDR); \
  1077. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1078. }
  1079. #define _SET_SYSCON_REG_register95_SCFG_funcshare_pad_ctrl_63(v) { \
  1080. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register95_REG_ADDR); \
  1081. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1082. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1083. MA_OUTW(syscon_iopad_ctrl_register95_REG_ADDR,_ezchip_macro_read_value_); \
  1084. }
  1085. #define _GET_SYSCON_REG_register95_SCFG_funcshare_pad_ctrl_63(_ezchip_macro_read_value_) { \
  1086. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register95_REG_ADDR); \
  1087. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1088. }
  1089. #define _SET_SYSCON_REG_register96_SCFG_funcshare_pad_ctrl_64(v) { \
  1090. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register96_REG_ADDR); \
  1091. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1092. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1093. MA_OUTW(syscon_iopad_ctrl_register96_REG_ADDR,_ezchip_macro_read_value_); \
  1094. }
  1095. #define _GET_SYSCON_REG_register96_SCFG_funcshare_pad_ctrl_64(_ezchip_macro_read_value_) { \
  1096. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register96_REG_ADDR); \
  1097. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1098. }
  1099. #define _SET_SYSCON_REG_register97_SCFG_funcshare_pad_ctrl_65(v) { \
  1100. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register97_REG_ADDR); \
  1101. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1102. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1103. MA_OUTW(syscon_iopad_ctrl_register97_REG_ADDR,_ezchip_macro_read_value_); \
  1104. }
  1105. #define _GET_SYSCON_REG_register97_SCFG_funcshare_pad_ctrl_65(_ezchip_macro_read_value_) { \
  1106. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register97_REG_ADDR); \
  1107. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1108. }
  1109. #define _SET_SYSCON_REG_register98_SCFG_funcshare_pad_ctrl_66(v) { \
  1110. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register98_REG_ADDR); \
  1111. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1112. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1113. MA_OUTW(syscon_iopad_ctrl_register98_REG_ADDR,_ezchip_macro_read_value_); \
  1114. }
  1115. #define _GET_SYSCON_REG_register98_SCFG_funcshare_pad_ctrl_66(_ezchip_macro_read_value_) { \
  1116. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register98_REG_ADDR); \
  1117. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1118. }
  1119. #define _SET_SYSCON_REG_register99_SCFG_funcshare_pad_ctrl_67(v) { \
  1120. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register99_REG_ADDR); \
  1121. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1122. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1123. MA_OUTW(syscon_iopad_ctrl_register99_REG_ADDR,_ezchip_macro_read_value_); \
  1124. }
  1125. #define _GET_SYSCON_REG_register99_SCFG_funcshare_pad_ctrl_67(_ezchip_macro_read_value_) { \
  1126. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register99_REG_ADDR); \
  1127. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1128. }
  1129. #define _SET_SYSCON_REG_register100_SCFG_funcshare_pad_ctrl_68(v) { \
  1130. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register100_REG_ADDR); \
  1131. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1132. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1133. MA_OUTW(syscon_iopad_ctrl_register100_REG_ADDR,_ezchip_macro_read_value_); \
  1134. }
  1135. #define _GET_SYSCON_REG_register100_SCFG_funcshare_pad_ctrl_68(_ezchip_macro_read_value_) { \
  1136. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register100_REG_ADDR); \
  1137. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1138. }
  1139. #define _SET_SYSCON_REG_register101_SCFG_funcshare_pad_ctrl_69(v) { \
  1140. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register101_REG_ADDR); \
  1141. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1142. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1143. MA_OUTW(syscon_iopad_ctrl_register101_REG_ADDR,_ezchip_macro_read_value_); \
  1144. }
  1145. #define _GET_SYSCON_REG_register101_SCFG_funcshare_pad_ctrl_69(_ezchip_macro_read_value_) { \
  1146. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register101_REG_ADDR); \
  1147. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1148. }
  1149. #define _SET_SYSCON_REG_register102_SCFG_funcshare_pad_ctrl_70(v) { \
  1150. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register102_REG_ADDR); \
  1151. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1152. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1153. MA_OUTW(syscon_iopad_ctrl_register102_REG_ADDR,_ezchip_macro_read_value_); \
  1154. }
  1155. #define _GET_SYSCON_REG_register102_SCFG_funcshare_pad_ctrl_70(_ezchip_macro_read_value_) { \
  1156. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register102_REG_ADDR); \
  1157. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1158. }
  1159. #define _SET_SYSCON_REG_register103_SCFG_qspi_ioctrl(v) { \
  1160. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register103_REG_ADDR); \
  1161. _ezchip_macro_read_value_ &= ~(0x7F); \
  1162. _ezchip_macro_read_value_ |= (v&0x7F); \
  1163. MA_OUTW(syscon_iopad_ctrl_register103_REG_ADDR,_ezchip_macro_read_value_); \
  1164. }
  1165. #define _GET_SYSCON_REG_register103_SCFG_qspi_ioctrl(_ezchip_macro_read_value_) { \
  1166. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register103_REG_ADDR); \
  1167. _ezchip_macro_read_value_ &= 0x7f;\
  1168. }
  1169. #define _SET_SYSCON_REG_register104_SCFG_io_padshare_sel(v) { \
  1170. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register104_REG_ADDR); \
  1171. _ezchip_macro_read_value_ &= ~(0x7); \
  1172. _ezchip_macro_read_value_ |= (v&0x7); \
  1173. MA_OUTW(syscon_iopad_ctrl_register104_REG_ADDR,_ezchip_macro_read_value_); \
  1174. }
  1175. #define _GET_SYSCON_REG_register104_SCFG_io_padshare_sel(_ezchip_macro_read_value_) { \
  1176. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register104_REG_ADDR); \
  1177. _ezchip_macro_read_value_ &= 0x7;\
  1178. }
  1179. #endif //_SYSCON_IOPAD_CTRL_MACRO_H_