sys.h 2.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111
  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /**
  3. ******************************************************************************
  4. * @file sys.h
  5. * @author StarFive Technology
  6. * @version V1.0
  7. * @date 06/25/2020
  8. * @brief
  9. ******************************************************************************
  10. * @copy
  11. *
  12. * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  13. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  14. * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
  15. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  16. * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  17. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  18. *
  19. * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
  20. */
  21. #ifndef SYS_H_
  22. #define SYS_H_
  23. /*********************************** sys clock************************/
  24. #define QSPI_CLK 100000000
  25. #define QSPI_REF_CLK 250000000
  26. #define DEFAULT_SD_BOOT_LOAD_BLOCK 1000
  27. #define DEFAULT_SPI_BOOT_START_ADDR 1
  28. #define DEFAULT_SPI_BOOT_SIZE_ADDR 0x0
  29. #define DEFAULT_SPI_BOOT_LOAD_PAGES 512
  30. // QSPI
  31. #define QSPI_BASE_ADDR 0x11860000
  32. //CADENCE QSPI AHB
  33. #define QSPI_BASE_AHB_ADDR 0x20000000
  34. // SDIO0
  35. #define SDIO0_BASE_ADDR 0x10000000
  36. // SDIO1
  37. #define SDIO1_BASE_ADDR 0x10010000
  38. // GPIO
  39. #define GPIO_BASE_ADDR 0x11910000///0xA9060000
  40. #define EZGPIO_FULLMUX_BASE_ADDR 0x11910000
  41. #define RSTGEN_BASE_ADDR 0x11840000
  42. #define CLKGEN_BASE_ADDR 0x11800000
  43. // CLKGEN
  44. #define VIC_CLKGEN_TOP_SV_BASE_ADDR 0x11800000///0xA9090000
  45. // RSTGEN
  46. #define VIC_RSTGEN_BASE_ADDR 0x11840000///0xA90A0000
  47. #define SYSCON_IOPAD_CTRL_BASE_ADDR 0x11858000
  48. // SYSCON
  49. #define SYSCON_SYSMAIN_CTRL_BASE_ADDR 0x11850000
  50. // HS-UART0
  51. #define UART0_HS_BASE_ADDR 0x11870000
  52. // HS-UART1
  53. #define UART1_HS_BASE_ADDR 0x11880000
  54. // UART2
  55. #define UART2_BASE_ADDR 0x12430000
  56. // UART3
  57. #define UART3_BASE_ADDR 0x12440000
  58. /*Reserved information:
  59. *second boot:64K 0x0 - 0xffff
  60. *ddr init:64K 0x10000 - 0x1ffff
  61. *uboot:1M 0x20000 - 0x11ffff
  62. *kernel:25M 0x120000 - 0x1a1ffff
  63. */
  64. /*Reserved information:
  65. *second boot:32K 0x0 - 0x7fff
  66. *ddr init:50K 0x8000 - 0x147ff
  67. *uboot:500K 0x14800 - 0x917ff
  68. *kernel:25M 0x130000 - 0x1a3ffff
  69. */
  70. /*DDR bin file */
  71. #define DEFAULT_DDR_ADDR 0x18080000
  72. #define DEFAULT_DDR_OFFSET 0x100
  73. /*uboot bin file*/
  74. #define DEFAULT_UBOOT_ADDR 0x80000000
  75. #define DEFAULT_UBOOT_OFFSET 0x200
  76. /*kernel image file*/
  77. #define DEFAULT_KERNEL_ADDR 0xa0000000
  78. #define DEFAULT_KERNEL_OFFSET 0x1200
  79. #define FLASH_SECONDBOOT_START_ADDR 0
  80. #define FLASH_DDRINIT_START_ADDR 0x10000
  81. #define FLASH_UBOOT_START_ADDR 0x20000
  82. #define DEFAULT_BOOT_LOAD_ADDR 0x80000000
  83. #endif