clkgen_ctrl_macro.h 173 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /**
  3. ******************************************************************************
  4. * @file clkgen_ctrl_macro.h
  5. * @author StarFive Technology
  6. * @version V1.0
  7. * @date 06/25/2020
  8. * @brief
  9. ******************************************************************************
  10. * @copy
  11. *
  12. * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  13. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  14. * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
  15. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  16. * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  17. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  18. *
  19. * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
  20. */
  21. #ifndef _CLKGEN_MACRO_H_
  22. #define _CLKGEN_MACRO_H_
  23. //#define CLKGEN_BASE_ADDR 0x0
  24. #define clk_cpundbus_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x0
  25. #define clk_dla_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x4
  26. #define clk_dsp_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x8
  27. #define clk_gmacusb_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xC
  28. #define clk_perh0_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x10
  29. #define clk_perh1_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x14
  30. #define clk_vin_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x18
  31. #define clk_vout_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1C
  32. #define clk_audio_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x20
  33. #define clk_cdechifi4_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x24
  34. #define clk_cdec_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x28
  35. #define clk_voutbus_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2C
  36. #define clk_cpunbus_root_div_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x30
  37. #define clk_dsp_root_div_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x34
  38. #define clk_perh0_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x38
  39. #define clk_perh1_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x3C
  40. #define clk_pll0_testout_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x40
  41. #define clk_pll1_testout_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x44
  42. #define clk_pll2_testout_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x48
  43. #define clk_pll2_refclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x4C
  44. #define clk_cpu_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x50
  45. #define clk_cpu_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x54
  46. #define clk_ahb_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x58
  47. #define clk_apb1_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x5C
  48. #define clk_apb2_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x60
  49. #define clk_dom3ahb_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x64
  50. #define clk_dom7ahb_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x68
  51. #define clk_u74_core0_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x6C
  52. #define clk_u74_core1_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x70
  53. #define clk_u74_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x74
  54. #define clk_u74rtc_toggle_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x78
  55. #define clk_sgdma2p_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x7C
  56. #define clk_dma2pnoc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x80
  57. #define clk_sgdma2p_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x84
  58. #define clk_dla_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x88
  59. #define clk_dla_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x8C
  60. #define clk_dlanoc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x90
  61. #define clk_dla_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x94
  62. #define clk_vp6_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x98
  63. #define clk_vp6bus_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x9C
  64. #define clk_vp6_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xA0
  65. #define clk_vcdecbus_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xA4
  66. #define clk_vdec_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xA8
  67. #define clk_vdec_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xAC
  68. #define clk_vdecbrg_mainclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xB0
  69. #define clk_vdec_bclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xB4
  70. #define clk_vdec_cclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xB8
  71. #define clk_vdec_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xBC
  72. #define clk_jpeg_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xC0
  73. #define clk_jpeg_cclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xC4
  74. #define clk_jpeg_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xC8
  75. #define clk_gc300_2x_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xCC
  76. #define clk_gc300_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xD0
  77. #define clk_jpcgc300_axibus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xD4
  78. #define clk_gc300_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xD8
  79. #define clk_jpcgc300_mainclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xDC
  80. #define clk_venc_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xE0
  81. #define clk_venc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xE4
  82. #define clk_vencbrg_mainclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xE8
  83. #define clk_venc_bclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xEC
  84. #define clk_venc_cclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xF0
  85. #define clk_venc_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xF4
  86. #define clk_ddrpll_div2_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xF8
  87. #define clk_ddrpll_div4_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xFC
  88. #define clk_ddrpll_div8_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x100
  89. #define clk_ddrosc_div2_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x104
  90. #define clk_ddrc0_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x108
  91. #define clk_ddrc1_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x10C
  92. #define clk_ddrphy_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x110
  93. #define clk_noc_rob_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x114
  94. #define clk_noc_cog_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x118
  95. #define clk_nne_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x11C
  96. #define clk_nnebus_src1_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x120
  97. #define clk_nne_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x124
  98. #define clk_nne_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x128
  99. #define clk_nnenoc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x12C
  100. #define clk_dlaslv_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x130
  101. #define clk_dspx2c_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x134
  102. #define clk_hifi4_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x138
  103. #define clk_hifi4_corefree_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x13C
  104. #define clk_hifi4_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x140
  105. #define clk_hifi4_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x144
  106. #define clk_hifi4_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x148
  107. #define clk_hifi4noc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x14C
  108. #define clk_sgdma1p_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x150
  109. #define clk_sgdma1p_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x154
  110. #define clk_dma1p_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x158
  111. #define clk_x2c_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x15C
  112. #define clk_usb_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x160
  113. #define clk_usb_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x164
  114. #define clk_usbnoc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x168
  115. #define clk_usbphy_rootdiv_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x16C
  116. #define clk_usbphy_125m_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x170
  117. #define clk_usbphy_plldiv25m_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x174
  118. #define clk_usbphy_25m_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x178
  119. #define clk_audio_div_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x17C
  120. #define clk_audio_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x180
  121. #define clk_audio_12288_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x184
  122. #define clk_vin_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x188
  123. #define clk_isp0_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x18C
  124. #define clk_isp0_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x190
  125. #define clk_isp0noc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x194
  126. #define clk_ispslv_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x198
  127. #define clk_isp1_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x19C
  128. #define clk_isp1_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1A0
  129. #define clk_isp1noc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1A4
  130. #define clk_vin_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1A8
  131. #define clk_vin_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1AC
  132. #define clk_vinnoc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1B0
  133. #define clk_vout_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1B4
  134. #define clk_dispbus_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1B8
  135. #define clk_disp_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1BC
  136. #define clk_disp_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1C0
  137. #define clk_dispnoc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1C4
  138. #define clk_sdio0_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1C8
  139. #define clk_sdio0_cclkint_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1CC
  140. #define clk_sdio0_cclkint_inv_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1D0
  141. #define clk_sdio1_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1D4
  142. #define clk_sdio1_cclkint_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1D8
  143. #define clk_sdio1_cclkint_inv_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1DC
  144. #define clk_gmac_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1E0
  145. #define clk_gmac_root_div_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1E4
  146. #define clk_gmac_ptp_refclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1E8
  147. #define clk_gmac_gtxclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1EC
  148. #define clk_gmac_rmii_txclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1F0
  149. #define clk_gmac_rmii_rxclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1F4
  150. #define clk_gmac_tx_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1F8
  151. #define clk_gmac_tx_inv_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1FC
  152. #define clk_gmac_rx_pre_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x200
  153. #define clk_gmac_rx_inv_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x204
  154. #define clk_gmac_rmii_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x208
  155. #define clk_gmac_tophyref_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x20C
  156. #define clk_spi2ahb_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x210
  157. #define clk_spi2ahb_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x214
  158. #define clk_ezmaster_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x218
  159. #define clk_e24_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x21C
  160. #define clk_e24rtc_toggle_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x220
  161. #define clk_qspi_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x224
  162. #define clk_qspi_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x228
  163. #define clk_qspi_refclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x22C
  164. #define clk_sec_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x230
  165. #define clk_aes_clk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x234
  166. #define clk_sha_clk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x238
  167. #define clk_pka_clk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x23C
  168. #define clk_trng_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x240
  169. #define clk_otp_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x244
  170. #define clk_uart0_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x248
  171. #define clk_uart0_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x24C
  172. #define clk_uart1_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x250
  173. #define clk_uart1_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x254
  174. #define clk_spi0_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x258
  175. #define clk_spi0_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x25C
  176. #define clk_spi1_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x260
  177. #define clk_spi1_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x264
  178. #define clk_i2c0_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x268
  179. #define clk_i2c0_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x26C
  180. #define clk_i2c1_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x270
  181. #define clk_i2c1_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x274
  182. #define clk_gpio_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x278
  183. #define clk_uart2_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x27C
  184. #define clk_uart2_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x280
  185. #define clk_uart3_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x284
  186. #define clk_uart3_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x288
  187. #define clk_spi2_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x28C
  188. #define clk_spi2_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x290
  189. #define clk_spi3_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x294
  190. #define clk_spi3_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x298
  191. #define clk_i2c2_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x29C
  192. #define clk_i2c2_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2A0
  193. #define clk_i2c3_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2A4
  194. #define clk_i2c3_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2A8
  195. #define clk_wdtimer_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2AC
  196. #define clk_wdt_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2B0
  197. #define clk_timer0_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2B4
  198. #define clk_timer1_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2B8
  199. #define clk_timer2_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2BC
  200. #define clk_timer3_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2C0
  201. #define clk_timer4_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2C4
  202. #define clk_timer5_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2C8
  203. #define clk_timer6_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2CC
  204. #define clk_vp6intc_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2D0
  205. #define clk_pwm_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2D4
  206. #define clk_msi_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2D8
  207. #define clk_temp_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2DC
  208. #define clk_temp_sense_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2E0
  209. #define clk_syserr_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2E4
  210. #define _ENABLE_CLOCK_clk_cpundbus_root_ {}
  211. #define _SWITCH_CLOCK_clk_cpundbus_root_SOURCE_clk_osc_sys_ { \
  212. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cpundbus_root_ctrl_REG_ADDR); \
  213. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  214. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  215. MA_OUTW(clk_cpundbus_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  216. }
  217. #define _SWITCH_CLOCK_clk_cpundbus_root_SOURCE_clk_pll0_out_ { \
  218. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cpundbus_root_ctrl_REG_ADDR); \
  219. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  220. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  221. MA_OUTW(clk_cpundbus_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  222. }
  223. #define _SWITCH_CLOCK_clk_cpundbus_root_SOURCE_clk_pll1_out_ { \
  224. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cpundbus_root_ctrl_REG_ADDR); \
  225. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  226. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  227. MA_OUTW(clk_cpundbus_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  228. }
  229. #define _SWITCH_CLOCK_clk_cpundbus_root_SOURCE_clk_pll2_out_ { \
  230. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cpundbus_root_ctrl_REG_ADDR); \
  231. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  232. _ezchip_macro_read_value_ |= (0x3&0x3)<<24; \
  233. MA_OUTW(clk_cpundbus_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  234. }
  235. #define _GET_CLOCK_SOURCE_STATUS_clk_cpundbus_root_(_ezchip_macro_read_value_) { \
  236. _ezchip_macro_read_value_=MA_INW(clk_cpundbus_root_ctrl_REG_ADDR) >> 24; \
  237. _ezchip_macro_read_value_ &= 0x3;\
  238. }
  239. #define _ENABLE_CLOCK_clk_dla_root_ {}
  240. #define _SWITCH_CLOCK_clk_dla_root_SOURCE_clk_osc_sys_ { \
  241. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_root_ctrl_REG_ADDR); \
  242. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  243. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  244. MA_OUTW(clk_dla_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  245. }
  246. #define _SWITCH_CLOCK_clk_dla_root_SOURCE_clk_pll1_out_ { \
  247. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_root_ctrl_REG_ADDR); \
  248. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  249. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  250. MA_OUTW(clk_dla_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  251. }
  252. #define _SWITCH_CLOCK_clk_dla_root_SOURCE_clk_pll2_out_ { \
  253. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_root_ctrl_REG_ADDR); \
  254. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  255. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  256. MA_OUTW(clk_dla_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  257. }
  258. #define _GET_CLOCK_SOURCE_STATUS_clk_dla_root_(_ezchip_macro_read_value_) { \
  259. _ezchip_macro_read_value_=MA_INW(clk_dla_root_ctrl_REG_ADDR) >> 24; \
  260. _ezchip_macro_read_value_ &= 0x3;\
  261. }
  262. #define _ENABLE_CLOCK_clk_dsp_root_ {}
  263. #define _SWITCH_CLOCK_clk_dsp_root_SOURCE_clk_osc_sys_ { \
  264. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dsp_root_ctrl_REG_ADDR); \
  265. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  266. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  267. MA_OUTW(clk_dsp_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  268. }
  269. #define _SWITCH_CLOCK_clk_dsp_root_SOURCE_clk_pll0_out_ { \
  270. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dsp_root_ctrl_REG_ADDR); \
  271. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  272. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  273. MA_OUTW(clk_dsp_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  274. }
  275. #define _SWITCH_CLOCK_clk_dsp_root_SOURCE_clk_pll1_out_ { \
  276. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dsp_root_ctrl_REG_ADDR); \
  277. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  278. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  279. MA_OUTW(clk_dsp_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  280. }
  281. #define _SWITCH_CLOCK_clk_dsp_root_SOURCE_clk_pll2_out_ { \
  282. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dsp_root_ctrl_REG_ADDR); \
  283. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  284. _ezchip_macro_read_value_ |= (0x3&0x3)<<24; \
  285. MA_OUTW(clk_dsp_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  286. }
  287. #define _GET_CLOCK_SOURCE_STATUS_clk_dsp_root_(_ezchip_macro_read_value_) { \
  288. _ezchip_macro_read_value_=MA_INW(clk_dsp_root_ctrl_REG_ADDR) >> 24; \
  289. _ezchip_macro_read_value_ &= 0x3;\
  290. }
  291. #define _ENABLE_CLOCK_clk_gmacusb_root_ {}
  292. #define _SWITCH_CLOCK_clk_gmacusb_root_SOURCE_clk_osc_sys_ { \
  293. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmacusb_root_ctrl_REG_ADDR); \
  294. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  295. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  296. MA_OUTW(clk_gmacusb_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  297. }
  298. #define _SWITCH_CLOCK_clk_gmacusb_root_SOURCE_clk_pll0_out_ { \
  299. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmacusb_root_ctrl_REG_ADDR); \
  300. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  301. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  302. MA_OUTW(clk_gmacusb_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  303. }
  304. #define _SWITCH_CLOCK_clk_gmacusb_root_SOURCE_clk_pll2_out_ { \
  305. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmacusb_root_ctrl_REG_ADDR); \
  306. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  307. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  308. MA_OUTW(clk_gmacusb_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  309. }
  310. #define _GET_CLOCK_SOURCE_STATUS_clk_gmacusb_root_(_ezchip_macro_read_value_) { \
  311. _ezchip_macro_read_value_=MA_INW(clk_gmacusb_root_ctrl_REG_ADDR) >> 24; \
  312. _ezchip_macro_read_value_ &= 0x3;\
  313. }
  314. #define _ENABLE_CLOCK_clk_perh0_root_ {}
  315. #define _SWITCH_CLOCK_clk_perh0_root_SOURCE_clk_osc_sys_ { \
  316. uint32_t _ezchip_macro_read_value_=MA_INW(clk_perh0_root_ctrl_REG_ADDR); \
  317. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  318. _ezchip_macro_read_value_ |= (0x0&0x1)<<24; \
  319. MA_OUTW(clk_perh0_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  320. }
  321. #define _SWITCH_CLOCK_clk_perh0_root_SOURCE_clk_pll0_out_ { \
  322. uint32_t _ezchip_macro_read_value_=MA_INW(clk_perh0_root_ctrl_REG_ADDR); \
  323. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  324. _ezchip_macro_read_value_ |= (0x1&0x1)<<24; \
  325. MA_OUTW(clk_perh0_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  326. }
  327. #define _GET_CLOCK_SOURCE_STATUS_clk_perh0_root_(_ezchip_macro_read_value_) { \
  328. _ezchip_macro_read_value_=MA_INW(clk_perh0_root_ctrl_REG_ADDR) >> 24; \
  329. _ezchip_macro_read_value_ &= 0x1;\
  330. }
  331. #define _ENABLE_CLOCK_clk_perh1_root_ {}
  332. #define _SWITCH_CLOCK_clk_perh1_root_SOURCE_clk_osc_sys_ { \
  333. uint32_t _ezchip_macro_read_value_=MA_INW(clk_perh1_root_ctrl_REG_ADDR); \
  334. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  335. _ezchip_macro_read_value_ |= (0x0&0x1)<<24; \
  336. MA_OUTW(clk_perh1_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  337. }
  338. #define _SWITCH_CLOCK_clk_perh1_root_SOURCE_clk_pll2_out_ { \
  339. uint32_t _ezchip_macro_read_value_=MA_INW(clk_perh1_root_ctrl_REG_ADDR); \
  340. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  341. _ezchip_macro_read_value_ |= (0x1&0x1)<<24; \
  342. MA_OUTW(clk_perh1_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  343. }
  344. #define _GET_CLOCK_SOURCE_STATUS_clk_perh1_root_(_ezchip_macro_read_value_) { \
  345. _ezchip_macro_read_value_=MA_INW(clk_perh1_root_ctrl_REG_ADDR) >> 24; \
  346. _ezchip_macro_read_value_ &= 0x1;\
  347. }
  348. #define _ENABLE_CLOCK_clk_vin_root_ {}
  349. #define _SWITCH_CLOCK_clk_vin_root_SOURCE_clk_osc_sys_ { \
  350. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_root_ctrl_REG_ADDR); \
  351. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  352. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  353. MA_OUTW(clk_vin_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  354. }
  355. #define _SWITCH_CLOCK_clk_vin_root_SOURCE_clk_pll1_out_ { \
  356. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_root_ctrl_REG_ADDR); \
  357. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  358. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  359. MA_OUTW(clk_vin_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  360. }
  361. #define _SWITCH_CLOCK_clk_vin_root_SOURCE_clk_pll2_out_ { \
  362. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_root_ctrl_REG_ADDR); \
  363. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  364. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  365. MA_OUTW(clk_vin_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  366. }
  367. #define _GET_CLOCK_SOURCE_STATUS_clk_vin_root_(_ezchip_macro_read_value_) { \
  368. _ezchip_macro_read_value_=MA_INW(clk_vin_root_ctrl_REG_ADDR) >> 24; \
  369. _ezchip_macro_read_value_ &= 0x3;\
  370. }
  371. #define _ENABLE_CLOCK_clk_vout_root_ {}
  372. #define _SWITCH_CLOCK_clk_vout_root_SOURCE_clk_osc_aud_ { \
  373. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vout_root_ctrl_REG_ADDR); \
  374. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  375. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  376. MA_OUTW(clk_vout_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  377. }
  378. #define _SWITCH_CLOCK_clk_vout_root_SOURCE_clk_pll0_out_ { \
  379. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vout_root_ctrl_REG_ADDR); \
  380. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  381. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  382. MA_OUTW(clk_vout_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  383. }
  384. #define _SWITCH_CLOCK_clk_vout_root_SOURCE_clk_pll2_out_ { \
  385. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vout_root_ctrl_REG_ADDR); \
  386. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  387. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  388. MA_OUTW(clk_vout_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  389. }
  390. #define _GET_CLOCK_SOURCE_STATUS_clk_vout_root_(_ezchip_macro_read_value_) { \
  391. _ezchip_macro_read_value_=MA_INW(clk_vout_root_ctrl_REG_ADDR) >> 24; \
  392. _ezchip_macro_read_value_ &= 0x3;\
  393. }
  394. #define _ENABLE_CLOCK_clk_audio_root_ { \
  395. uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_root_ctrl_REG_ADDR); \
  396. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  397. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  398. MA_OUTW(clk_audio_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  399. }
  400. #define _DISABLE_CLOCK_clk_audio_root_ { \
  401. uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_root_ctrl_REG_ADDR); \
  402. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  403. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  404. MA_OUTW(clk_audio_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  405. }
  406. #define _GET_CLOCK_ENABLE_STATUS_clk_audio_root_(_ezchip_macro_read_value_) { \
  407. _ezchip_macro_read_value_=MA_INW(clk_audio_root_ctrl_REG_ADDR) >> 31; \
  408. _ezchip_macro_read_value_ &= 0x1;\
  409. }
  410. #define _DIVIDE_CLOCK_clk_audio_root_(div) { \
  411. uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_root_ctrl_REG_ADDR); \
  412. _ezchip_macro_read_value_ &= ~(0xF); \
  413. _ezchip_macro_read_value_ |= (div&0xF); \
  414. MA_OUTW(clk_audio_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  415. }
  416. #define _GET_CLOCK_DIVIDE_STATUS_clk_audio_root_(_ezchip_macro_read_value_) { \
  417. _ezchip_macro_read_value_=MA_INW(clk_audio_root_ctrl_REG_ADDR); \
  418. _ezchip_macro_read_value_ &= 0xf;\
  419. }
  420. #define _ENABLE_CLOCK_clk_cdechifi4_root_ {}
  421. #define _SWITCH_CLOCK_clk_cdechifi4_root_SOURCE_clk_osc_sys_ { \
  422. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cdechifi4_root_ctrl_REG_ADDR); \
  423. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  424. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  425. MA_OUTW(clk_cdechifi4_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  426. }
  427. #define _SWITCH_CLOCK_clk_cdechifi4_root_SOURCE_clk_pll1_out_ { \
  428. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cdechifi4_root_ctrl_REG_ADDR); \
  429. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  430. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  431. MA_OUTW(clk_cdechifi4_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  432. }
  433. #define _SWITCH_CLOCK_clk_cdechifi4_root_SOURCE_clk_pll2_out_ { \
  434. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cdechifi4_root_ctrl_REG_ADDR); \
  435. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  436. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  437. MA_OUTW(clk_cdechifi4_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  438. }
  439. #define _GET_CLOCK_SOURCE_STATUS_clk_cdechifi4_root_(_ezchip_macro_read_value_) { \
  440. _ezchip_macro_read_value_=MA_INW(clk_cdechifi4_root_ctrl_REG_ADDR) >> 24; \
  441. _ezchip_macro_read_value_ &= 0x3;\
  442. }
  443. #define _ENABLE_CLOCK_clk_cdec_root_ {}
  444. #define _SWITCH_CLOCK_clk_cdec_root_SOURCE_clk_osc_sys_ { \
  445. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cdec_root_ctrl_REG_ADDR); \
  446. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  447. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  448. MA_OUTW(clk_cdec_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  449. }
  450. #define _SWITCH_CLOCK_clk_cdec_root_SOURCE_clk_pll0_out_ { \
  451. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cdec_root_ctrl_REG_ADDR); \
  452. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  453. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  454. MA_OUTW(clk_cdec_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  455. }
  456. #define _SWITCH_CLOCK_clk_cdec_root_SOURCE_clk_pll1_out_ { \
  457. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cdec_root_ctrl_REG_ADDR); \
  458. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  459. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  460. MA_OUTW(clk_cdec_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  461. }
  462. #define _GET_CLOCK_SOURCE_STATUS_clk_cdec_root_(_ezchip_macro_read_value_) { \
  463. _ezchip_macro_read_value_=MA_INW(clk_cdec_root_ctrl_REG_ADDR) >> 24; \
  464. _ezchip_macro_read_value_ &= 0x3;\
  465. }
  466. #define _ENABLE_CLOCK_clk_voutbus_root_ {}
  467. #define _SWITCH_CLOCK_clk_voutbus_root_SOURCE_clk_osc_aud_ { \
  468. uint32_t _ezchip_macro_read_value_=MA_INW(clk_voutbus_root_ctrl_REG_ADDR); \
  469. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  470. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  471. MA_OUTW(clk_voutbus_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  472. }
  473. #define _SWITCH_CLOCK_clk_voutbus_root_SOURCE_clk_pll0_out_ { \
  474. uint32_t _ezchip_macro_read_value_=MA_INW(clk_voutbus_root_ctrl_REG_ADDR); \
  475. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  476. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  477. MA_OUTW(clk_voutbus_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  478. }
  479. #define _SWITCH_CLOCK_clk_voutbus_root_SOURCE_clk_pll2_out_ { \
  480. uint32_t _ezchip_macro_read_value_=MA_INW(clk_voutbus_root_ctrl_REG_ADDR); \
  481. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  482. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  483. MA_OUTW(clk_voutbus_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  484. }
  485. #define _GET_CLOCK_SOURCE_STATUS_clk_voutbus_root_(_ezchip_macro_read_value_) { \
  486. _ezchip_macro_read_value_=MA_INW(clk_voutbus_root_ctrl_REG_ADDR) >> 24; \
  487. _ezchip_macro_read_value_ &= 0x3;\
  488. }
  489. #define _ENABLE_CLOCK_clk_cpunbus_root_div_ {}
  490. #define _DIVIDE_CLOCK_clk_cpunbus_root_div_(div) { \
  491. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cpunbus_root_div_ctrl_REG_ADDR); \
  492. _ezchip_macro_read_value_ &= ~(0x3); \
  493. _ezchip_macro_read_value_ |= (div&0x3); \
  494. MA_OUTW(clk_cpunbus_root_div_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  495. }
  496. #define _GET_CLOCK_DIVIDE_STATUS_clk_cpunbus_root_div_(_ezchip_macro_read_value_) { \
  497. _ezchip_macro_read_value_=MA_INW(clk_cpunbus_root_div_ctrl_REG_ADDR); \
  498. _ezchip_macro_read_value_ &= 0x3;\
  499. }
  500. #define _ENABLE_CLOCK_clk_dsp_root_div_ {}
  501. #define _DIVIDE_CLOCK_clk_dsp_root_div_(div) { \
  502. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dsp_root_div_ctrl_REG_ADDR); \
  503. _ezchip_macro_read_value_ &= ~(0x7); \
  504. _ezchip_macro_read_value_ |= (div&0x7); \
  505. MA_OUTW(clk_dsp_root_div_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  506. }
  507. #define _GET_CLOCK_DIVIDE_STATUS_clk_dsp_root_div_(_ezchip_macro_read_value_) { \
  508. _ezchip_macro_read_value_=MA_INW(clk_dsp_root_div_ctrl_REG_ADDR); \
  509. _ezchip_macro_read_value_ &= 0x7;\
  510. }
  511. #define _ENABLE_CLOCK_clk_perh0_src_ {}
  512. #define _DIVIDE_CLOCK_clk_perh0_src_(div) { \
  513. uint32_t _ezchip_macro_read_value_=MA_INW(clk_perh0_src_ctrl_REG_ADDR); \
  514. _ezchip_macro_read_value_ &= ~(0x7); \
  515. _ezchip_macro_read_value_ |= (div&0x7); \
  516. MA_OUTW(clk_perh0_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  517. }
  518. #define _GET_CLOCK_DIVIDE_STATUS_clk_perh0_src_(_ezchip_macro_read_value_) { \
  519. _ezchip_macro_read_value_=MA_INW(clk_perh0_src_ctrl_REG_ADDR); \
  520. _ezchip_macro_read_value_ &= 0x7;\
  521. }
  522. #define _ENABLE_CLOCK_clk_perh1_src_ {}
  523. #define _DIVIDE_CLOCK_clk_perh1_src_(div) { \
  524. uint32_t _ezchip_macro_read_value_=MA_INW(clk_perh1_src_ctrl_REG_ADDR); \
  525. _ezchip_macro_read_value_ &= ~(0x7); \
  526. _ezchip_macro_read_value_ |= (div&0x7); \
  527. MA_OUTW(clk_perh1_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  528. }
  529. #define _GET_CLOCK_DIVIDE_STATUS_clk_perh1_src_(_ezchip_macro_read_value_) { \
  530. _ezchip_macro_read_value_=MA_INW(clk_perh1_src_ctrl_REG_ADDR); \
  531. _ezchip_macro_read_value_ &= 0x7;\
  532. }
  533. #define _ENABLE_CLOCK_clk_pll0_testout_ { \
  534. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll0_testout_ctrl_REG_ADDR); \
  535. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  536. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  537. MA_OUTW(clk_pll0_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  538. }
  539. #define _DISABLE_CLOCK_clk_pll0_testout_ { \
  540. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll0_testout_ctrl_REG_ADDR); \
  541. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  542. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  543. MA_OUTW(clk_pll0_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  544. }
  545. #define _GET_CLOCK_ENABLE_STATUS_clk_pll0_testout_(_ezchip_macro_read_value_) { \
  546. _ezchip_macro_read_value_=MA_INW(clk_pll0_testout_ctrl_REG_ADDR) >> 31; \
  547. _ezchip_macro_read_value_ &= 0x1;\
  548. }
  549. #define _DIVIDE_CLOCK_clk_pll0_testout_(div) { \
  550. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll0_testout_ctrl_REG_ADDR); \
  551. _ezchip_macro_read_value_ &= ~(0x1F); \
  552. _ezchip_macro_read_value_ |= (div&0x1F); \
  553. MA_OUTW(clk_pll0_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  554. }
  555. #define _GET_CLOCK_DIVIDE_STATUS_clk_pll0_testout_(_ezchip_macro_read_value_) { \
  556. _ezchip_macro_read_value_=MA_INW(clk_pll0_testout_ctrl_REG_ADDR); \
  557. _ezchip_macro_read_value_ &= 0x1f;\
  558. }
  559. #define _ENABLE_CLOCK_clk_pll1_testout_ { \
  560. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll1_testout_ctrl_REG_ADDR); \
  561. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  562. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  563. MA_OUTW(clk_pll1_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  564. }
  565. #define _DISABLE_CLOCK_clk_pll1_testout_ { \
  566. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll1_testout_ctrl_REG_ADDR); \
  567. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  568. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  569. MA_OUTW(clk_pll1_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  570. }
  571. #define _GET_CLOCK_ENABLE_STATUS_clk_pll1_testout_(_ezchip_macro_read_value_) { \
  572. _ezchip_macro_read_value_=MA_INW(clk_pll1_testout_ctrl_REG_ADDR) >> 31; \
  573. _ezchip_macro_read_value_ &= 0x1;\
  574. }
  575. #define _DIVIDE_CLOCK_clk_pll1_testout_(div) { \
  576. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll1_testout_ctrl_REG_ADDR); \
  577. _ezchip_macro_read_value_ &= ~(0x1F); \
  578. _ezchip_macro_read_value_ |= (div&0x1F); \
  579. MA_OUTW(clk_pll1_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  580. }
  581. #define _GET_CLOCK_DIVIDE_STATUS_clk_pll1_testout_(_ezchip_macro_read_value_) { \
  582. _ezchip_macro_read_value_=MA_INW(clk_pll1_testout_ctrl_REG_ADDR); \
  583. _ezchip_macro_read_value_ &= 0x1f;\
  584. }
  585. #define _ENABLE_CLOCK_clk_pll2_testout_ { \
  586. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll2_testout_ctrl_REG_ADDR); \
  587. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  588. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  589. MA_OUTW(clk_pll2_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  590. }
  591. #define _DISABLE_CLOCK_clk_pll2_testout_ { \
  592. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll2_testout_ctrl_REG_ADDR); \
  593. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  594. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  595. MA_OUTW(clk_pll2_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  596. }
  597. #define _GET_CLOCK_ENABLE_STATUS_clk_pll2_testout_(_ezchip_macro_read_value_) { \
  598. _ezchip_macro_read_value_=MA_INW(clk_pll2_testout_ctrl_REG_ADDR) >> 31; \
  599. _ezchip_macro_read_value_ &= 0x1;\
  600. }
  601. #define _DIVIDE_CLOCK_clk_pll2_testout_(div) { \
  602. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll2_testout_ctrl_REG_ADDR); \
  603. _ezchip_macro_read_value_ &= ~(0x1F); \
  604. _ezchip_macro_read_value_ |= (div&0x1F); \
  605. MA_OUTW(clk_pll2_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  606. }
  607. #define _GET_CLOCK_DIVIDE_STATUS_clk_pll2_testout_(_ezchip_macro_read_value_) { \
  608. _ezchip_macro_read_value_=MA_INW(clk_pll2_testout_ctrl_REG_ADDR); \
  609. _ezchip_macro_read_value_ &= 0x1f;\
  610. }
  611. #define _ENABLE_CLOCK_clk_pll2_refclk_ {}
  612. #define _SWITCH_CLOCK_clk_pll2_refclk_SOURCE_clk_osc_sys_ { \
  613. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll2_refclk_ctrl_REG_ADDR); \
  614. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  615. _ezchip_macro_read_value_ |= (0x0&0x1)<<24; \
  616. MA_OUTW(clk_pll2_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  617. }
  618. #define _SWITCH_CLOCK_clk_pll2_refclk_SOURCE_clk_osc_aud_ { \
  619. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll2_refclk_ctrl_REG_ADDR); \
  620. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  621. _ezchip_macro_read_value_ |= (0x1&0x1)<<24; \
  622. MA_OUTW(clk_pll2_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  623. }
  624. #define _GET_CLOCK_SOURCE_STATUS_clk_pll2_refclk_(_ezchip_macro_read_value_) { \
  625. _ezchip_macro_read_value_=MA_INW(clk_pll2_refclk_ctrl_REG_ADDR) >> 24; \
  626. _ezchip_macro_read_value_ &= 0x1;\
  627. }
  628. #define _ENABLE_CLOCK_clk_cpu_core_ {}
  629. #define _DIVIDE_CLOCK_clk_cpu_core_(div) { \
  630. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cpu_core_ctrl_REG_ADDR); \
  631. _ezchip_macro_read_value_ &= ~(0xF); \
  632. _ezchip_macro_read_value_ |= (div&0xF); \
  633. MA_OUTW(clk_cpu_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  634. }
  635. #define _GET_CLOCK_DIVIDE_STATUS_clk_cpu_core_(_ezchip_macro_read_value_) { \
  636. _ezchip_macro_read_value_=MA_INW(clk_cpu_core_ctrl_REG_ADDR); \
  637. _ezchip_macro_read_value_ &= 0xf;\
  638. }
  639. #define _ENABLE_CLOCK_clk_cpu_axi_ {}
  640. #define _DIVIDE_CLOCK_clk_cpu_axi_(div) { \
  641. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cpu_axi_ctrl_REG_ADDR); \
  642. _ezchip_macro_read_value_ &= ~(0xF); \
  643. _ezchip_macro_read_value_ |= (div&0xF); \
  644. MA_OUTW(clk_cpu_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  645. }
  646. #define _GET_CLOCK_DIVIDE_STATUS_clk_cpu_axi_(_ezchip_macro_read_value_) { \
  647. _ezchip_macro_read_value_=MA_INW(clk_cpu_axi_ctrl_REG_ADDR); \
  648. _ezchip_macro_read_value_ &= 0xf;\
  649. }
  650. #define _ENABLE_CLOCK_clk_ahb_bus_ {}
  651. #define _DIVIDE_CLOCK_clk_ahb_bus_(div) { \
  652. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ahb_bus_ctrl_REG_ADDR); \
  653. _ezchip_macro_read_value_ &= ~(0xF); \
  654. _ezchip_macro_read_value_ |= (div&0xF); \
  655. MA_OUTW(clk_ahb_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  656. }
  657. #define _GET_CLOCK_DIVIDE_STATUS_clk_ahb_bus_(_ezchip_macro_read_value_) { \
  658. _ezchip_macro_read_value_=MA_INW(clk_ahb_bus_ctrl_REG_ADDR); \
  659. _ezchip_macro_read_value_ &= 0xf;\
  660. }
  661. #define _ENABLE_CLOCK_clk_apb1_bus_ {}
  662. #define _DIVIDE_CLOCK_clk_apb1_bus_(div) { \
  663. uint32_t _ezchip_macro_read_value_=MA_INW(clk_apb1_bus_ctrl_REG_ADDR); \
  664. _ezchip_macro_read_value_ &= ~(0xF); \
  665. _ezchip_macro_read_value_ |= (div&0xF); \
  666. MA_OUTW(clk_apb1_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  667. }
  668. #define _GET_CLOCK_DIVIDE_STATUS_clk_apb1_bus_(_ezchip_macro_read_value_) { \
  669. _ezchip_macro_read_value_=MA_INW(clk_apb1_bus_ctrl_REG_ADDR); \
  670. _ezchip_macro_read_value_ &= 0xf;\
  671. }
  672. #define _ENABLE_CLOCK_clk_apb2_bus_ {}
  673. #define _DIVIDE_CLOCK_clk_apb2_bus_(div) { \
  674. uint32_t _ezchip_macro_read_value_=MA_INW(clk_apb2_bus_ctrl_REG_ADDR); \
  675. _ezchip_macro_read_value_ &= ~(0xF); \
  676. _ezchip_macro_read_value_ |= (div&0xF); \
  677. MA_OUTW(clk_apb2_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  678. }
  679. #define _GET_CLOCK_DIVIDE_STATUS_clk_apb2_bus_(_ezchip_macro_read_value_) { \
  680. _ezchip_macro_read_value_=MA_INW(clk_apb2_bus_ctrl_REG_ADDR); \
  681. _ezchip_macro_read_value_ &= 0xf;\
  682. }
  683. #define _ENABLE_CLOCK_clk_dom3ahb_bus_ { \
  684. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dom3ahb_bus_ctrl_REG_ADDR); \
  685. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  686. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  687. MA_OUTW(clk_dom3ahb_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  688. }
  689. #define _DISABLE_CLOCK_clk_dom3ahb_bus_ { \
  690. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dom3ahb_bus_ctrl_REG_ADDR); \
  691. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  692. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  693. MA_OUTW(clk_dom3ahb_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  694. }
  695. #define _GET_CLOCK_ENABLE_STATUS_clk_dom3ahb_bus_(_ezchip_macro_read_value_) { \
  696. _ezchip_macro_read_value_=MA_INW(clk_dom3ahb_bus_ctrl_REG_ADDR) >> 31; \
  697. _ezchip_macro_read_value_ &= 0x1;\
  698. }
  699. #define _ENABLE_CLOCK_clk_dom7ahb_bus_ { \
  700. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dom7ahb_bus_ctrl_REG_ADDR); \
  701. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  702. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  703. MA_OUTW(clk_dom7ahb_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  704. }
  705. #define _DISABLE_CLOCK_clk_dom7ahb_bus_ { \
  706. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dom7ahb_bus_ctrl_REG_ADDR); \
  707. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  708. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  709. MA_OUTW(clk_dom7ahb_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  710. }
  711. #define _GET_CLOCK_ENABLE_STATUS_clk_dom7ahb_bus_(_ezchip_macro_read_value_) { \
  712. _ezchip_macro_read_value_=MA_INW(clk_dom7ahb_bus_ctrl_REG_ADDR) >> 31; \
  713. _ezchip_macro_read_value_ &= 0x1;\
  714. }
  715. #define _ENABLE_CLOCK_clk_u74_core0_ { \
  716. uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74_core0_ctrl_REG_ADDR); \
  717. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  718. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  719. MA_OUTW(clk_u74_core0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  720. }
  721. #define _DISABLE_CLOCK_clk_u74_core0_ { \
  722. uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74_core0_ctrl_REG_ADDR); \
  723. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  724. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  725. MA_OUTW(clk_u74_core0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  726. }
  727. #define _GET_CLOCK_ENABLE_STATUS_clk_u74_core0_(_ezchip_macro_read_value_) { \
  728. _ezchip_macro_read_value_=MA_INW(clk_u74_core0_ctrl_REG_ADDR) >> 31; \
  729. _ezchip_macro_read_value_ &= 0x1;\
  730. }
  731. #define _ENABLE_CLOCK_clk_u74_core1_ { \
  732. uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74_core1_ctrl_REG_ADDR); \
  733. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  734. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  735. MA_OUTW(clk_u74_core1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  736. }
  737. #define _DISABLE_CLOCK_clk_u74_core1_ { \
  738. uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74_core1_ctrl_REG_ADDR); \
  739. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  740. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  741. MA_OUTW(clk_u74_core1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  742. }
  743. #define _GET_CLOCK_ENABLE_STATUS_clk_u74_core1_(_ezchip_macro_read_value_) { \
  744. _ezchip_macro_read_value_=MA_INW(clk_u74_core1_ctrl_REG_ADDR) >> 31; \
  745. _ezchip_macro_read_value_ &= 0x1;\
  746. }
  747. #define _DIVIDE_CLOCK_clk_u74_core1_(div) { \
  748. uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74_core1_ctrl_REG_ADDR); \
  749. _ezchip_macro_read_value_ &= ~(0xF); \
  750. _ezchip_macro_read_value_ |= (div&0xF); \
  751. MA_OUTW(clk_u74_core1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  752. }
  753. #define _GET_CLOCK_DIVIDE_STATUS_clk_u74_core1_(_ezchip_macro_read_value_) { \
  754. _ezchip_macro_read_value_=MA_INW(clk_u74_core1_ctrl_REG_ADDR); \
  755. _ezchip_macro_read_value_ &= 0xf;\
  756. }
  757. #define _ENABLE_CLOCK_clk_u74_axi_ { \
  758. uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74_axi_ctrl_REG_ADDR); \
  759. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  760. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  761. MA_OUTW(clk_u74_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  762. }
  763. #define _DISABLE_CLOCK_clk_u74_axi_ { \
  764. uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74_axi_ctrl_REG_ADDR); \
  765. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  766. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  767. MA_OUTW(clk_u74_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  768. }
  769. #define _GET_CLOCK_ENABLE_STATUS_clk_u74_axi_(_ezchip_macro_read_value_) { \
  770. _ezchip_macro_read_value_=MA_INW(clk_u74_axi_ctrl_REG_ADDR) >> 31; \
  771. _ezchip_macro_read_value_ &= 0x1;\
  772. }
  773. #define _ENABLE_CLOCK_clk_u74rtc_toggle_ { \
  774. uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74rtc_toggle_ctrl_REG_ADDR); \
  775. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  776. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  777. MA_OUTW(clk_u74rtc_toggle_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  778. }
  779. #define _DISABLE_CLOCK_clk_u74rtc_toggle_ { \
  780. uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74rtc_toggle_ctrl_REG_ADDR); \
  781. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  782. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  783. MA_OUTW(clk_u74rtc_toggle_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  784. }
  785. #define _GET_CLOCK_ENABLE_STATUS_clk_u74rtc_toggle_(_ezchip_macro_read_value_) { \
  786. _ezchip_macro_read_value_=MA_INW(clk_u74rtc_toggle_ctrl_REG_ADDR) >> 31; \
  787. _ezchip_macro_read_value_ &= 0x1;\
  788. }
  789. #define _ENABLE_CLOCK_clk_sgdma2p_axi_ { \
  790. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sgdma2p_axi_ctrl_REG_ADDR); \
  791. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  792. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  793. MA_OUTW(clk_sgdma2p_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  794. }
  795. #define _DISABLE_CLOCK_clk_sgdma2p_axi_ { \
  796. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sgdma2p_axi_ctrl_REG_ADDR); \
  797. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  798. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  799. MA_OUTW(clk_sgdma2p_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  800. }
  801. #define _GET_CLOCK_ENABLE_STATUS_clk_sgdma2p_axi_(_ezchip_macro_read_value_) { \
  802. _ezchip_macro_read_value_=MA_INW(clk_sgdma2p_axi_ctrl_REG_ADDR) >> 31; \
  803. _ezchip_macro_read_value_ &= 0x1;\
  804. }
  805. #define _ENABLE_CLOCK_clk_dma2pnoc_axi_ { \
  806. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dma2pnoc_axi_ctrl_REG_ADDR); \
  807. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  808. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  809. MA_OUTW(clk_dma2pnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  810. }
  811. #define _DISABLE_CLOCK_clk_dma2pnoc_axi_ { \
  812. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dma2pnoc_axi_ctrl_REG_ADDR); \
  813. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  814. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  815. MA_OUTW(clk_dma2pnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  816. }
  817. #define _GET_CLOCK_ENABLE_STATUS_clk_dma2pnoc_axi_(_ezchip_macro_read_value_) { \
  818. _ezchip_macro_read_value_=MA_INW(clk_dma2pnoc_axi_ctrl_REG_ADDR) >> 31; \
  819. _ezchip_macro_read_value_ &= 0x1;\
  820. }
  821. #define _ENABLE_CLOCK_clk_sgdma2p_ahb_ { \
  822. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sgdma2p_ahb_ctrl_REG_ADDR); \
  823. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  824. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  825. MA_OUTW(clk_sgdma2p_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  826. }
  827. #define _DISABLE_CLOCK_clk_sgdma2p_ahb_ { \
  828. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sgdma2p_ahb_ctrl_REG_ADDR); \
  829. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  830. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  831. MA_OUTW(clk_sgdma2p_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  832. }
  833. #define _GET_CLOCK_ENABLE_STATUS_clk_sgdma2p_ahb_(_ezchip_macro_read_value_) { \
  834. _ezchip_macro_read_value_=MA_INW(clk_sgdma2p_ahb_ctrl_REG_ADDR) >> 31; \
  835. _ezchip_macro_read_value_ &= 0x1;\
  836. }
  837. #define _ENABLE_CLOCK_clk_dla_bus_ {}
  838. #define _DIVIDE_CLOCK_clk_dla_bus_(div) { \
  839. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_bus_ctrl_REG_ADDR); \
  840. _ezchip_macro_read_value_ &= ~(0x7); \
  841. _ezchip_macro_read_value_ |= (div&0x7); \
  842. MA_OUTW(clk_dla_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  843. }
  844. #define _GET_CLOCK_DIVIDE_STATUS_clk_dla_bus_(_ezchip_macro_read_value_) { \
  845. _ezchip_macro_read_value_=MA_INW(clk_dla_bus_ctrl_REG_ADDR); \
  846. _ezchip_macro_read_value_ &= 0x7;\
  847. }
  848. #define _ENABLE_CLOCK_clk_dla_axi_ { \
  849. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_axi_ctrl_REG_ADDR); \
  850. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  851. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  852. MA_OUTW(clk_dla_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  853. }
  854. #define _DISABLE_CLOCK_clk_dla_axi_ { \
  855. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_axi_ctrl_REG_ADDR); \
  856. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  857. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  858. MA_OUTW(clk_dla_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  859. }
  860. #define _GET_CLOCK_ENABLE_STATUS_clk_dla_axi_(_ezchip_macro_read_value_) { \
  861. _ezchip_macro_read_value_=MA_INW(clk_dla_axi_ctrl_REG_ADDR) >> 31; \
  862. _ezchip_macro_read_value_ &= 0x1;\
  863. }
  864. #define _ENABLE_CLOCK_clk_dlanoc_axi_ { \
  865. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dlanoc_axi_ctrl_REG_ADDR); \
  866. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  867. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  868. MA_OUTW(clk_dlanoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  869. }
  870. #define _DISABLE_CLOCK_clk_dlanoc_axi_ { \
  871. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dlanoc_axi_ctrl_REG_ADDR); \
  872. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  873. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  874. MA_OUTW(clk_dlanoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  875. }
  876. #define _GET_CLOCK_ENABLE_STATUS_clk_dlanoc_axi_(_ezchip_macro_read_value_) { \
  877. _ezchip_macro_read_value_=MA_INW(clk_dlanoc_axi_ctrl_REG_ADDR) >> 31; \
  878. _ezchip_macro_read_value_ &= 0x1;\
  879. }
  880. #define _ENABLE_CLOCK_clk_dla_apb_ { \
  881. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_apb_ctrl_REG_ADDR); \
  882. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  883. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  884. MA_OUTW(clk_dla_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  885. }
  886. #define _DISABLE_CLOCK_clk_dla_apb_ { \
  887. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_apb_ctrl_REG_ADDR); \
  888. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  889. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  890. MA_OUTW(clk_dla_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  891. }
  892. #define _GET_CLOCK_ENABLE_STATUS_clk_dla_apb_(_ezchip_macro_read_value_) { \
  893. _ezchip_macro_read_value_=MA_INW(clk_dla_apb_ctrl_REG_ADDR) >> 31; \
  894. _ezchip_macro_read_value_ &= 0x1;\
  895. }
  896. #define _ENABLE_CLOCK_clk_vp6_core_ { \
  897. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6_core_ctrl_REG_ADDR); \
  898. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  899. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  900. MA_OUTW(clk_vp6_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  901. }
  902. #define _DISABLE_CLOCK_clk_vp6_core_ { \
  903. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6_core_ctrl_REG_ADDR); \
  904. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  905. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  906. MA_OUTW(clk_vp6_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  907. }
  908. #define _GET_CLOCK_ENABLE_STATUS_clk_vp6_core_(_ezchip_macro_read_value_) { \
  909. _ezchip_macro_read_value_=MA_INW(clk_vp6_core_ctrl_REG_ADDR) >> 31; \
  910. _ezchip_macro_read_value_ &= 0x1;\
  911. }
  912. #define _DIVIDE_CLOCK_clk_vp6_core_(div) { \
  913. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6_core_ctrl_REG_ADDR); \
  914. _ezchip_macro_read_value_ &= ~(0x7); \
  915. _ezchip_macro_read_value_ |= (div&0x7); \
  916. MA_OUTW(clk_vp6_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  917. }
  918. #define _GET_CLOCK_DIVIDE_STATUS_clk_vp6_core_(_ezchip_macro_read_value_) { \
  919. _ezchip_macro_read_value_=MA_INW(clk_vp6_core_ctrl_REG_ADDR); \
  920. _ezchip_macro_read_value_ &= 0x7;\
  921. }
  922. #define _ENABLE_CLOCK_clk_vp6bus_src_ {}
  923. #define _DIVIDE_CLOCK_clk_vp6bus_src_(div) { \
  924. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6bus_src_ctrl_REG_ADDR); \
  925. _ezchip_macro_read_value_ &= ~(0x7); \
  926. _ezchip_macro_read_value_ |= (div&0x7); \
  927. MA_OUTW(clk_vp6bus_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  928. }
  929. #define _GET_CLOCK_DIVIDE_STATUS_clk_vp6bus_src_(_ezchip_macro_read_value_) { \
  930. _ezchip_macro_read_value_=MA_INW(clk_vp6bus_src_ctrl_REG_ADDR); \
  931. _ezchip_macro_read_value_ &= 0x7;\
  932. }
  933. #define _ENABLE_CLOCK_clk_vp6_axi_ { \
  934. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6_axi_ctrl_REG_ADDR); \
  935. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  936. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  937. MA_OUTW(clk_vp6_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  938. }
  939. #define _DISABLE_CLOCK_clk_vp6_axi_ { \
  940. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6_axi_ctrl_REG_ADDR); \
  941. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  942. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  943. MA_OUTW(clk_vp6_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  944. }
  945. #define _GET_CLOCK_ENABLE_STATUS_clk_vp6_axi_(_ezchip_macro_read_value_) { \
  946. _ezchip_macro_read_value_=MA_INW(clk_vp6_axi_ctrl_REG_ADDR) >> 31; \
  947. _ezchip_macro_read_value_ &= 0x1;\
  948. }
  949. #define _DIVIDE_CLOCK_clk_vp6_axi_(div) { \
  950. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6_axi_ctrl_REG_ADDR); \
  951. _ezchip_macro_read_value_ &= ~(0x7); \
  952. _ezchip_macro_read_value_ |= (div&0x7); \
  953. MA_OUTW(clk_vp6_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  954. }
  955. #define _GET_CLOCK_DIVIDE_STATUS_clk_vp6_axi_(_ezchip_macro_read_value_) { \
  956. _ezchip_macro_read_value_=MA_INW(clk_vp6_axi_ctrl_REG_ADDR); \
  957. _ezchip_macro_read_value_ &= 0x7;\
  958. }
  959. #define _ENABLE_CLOCK_clk_vcdecbus_src_ {}
  960. #define _DIVIDE_CLOCK_clk_vcdecbus_src_(div) { \
  961. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vcdecbus_src_ctrl_REG_ADDR); \
  962. _ezchip_macro_read_value_ &= ~(0x7); \
  963. _ezchip_macro_read_value_ |= (div&0x7); \
  964. MA_OUTW(clk_vcdecbus_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  965. }
  966. #define _GET_CLOCK_DIVIDE_STATUS_clk_vcdecbus_src_(_ezchip_macro_read_value_) { \
  967. _ezchip_macro_read_value_=MA_INW(clk_vcdecbus_src_ctrl_REG_ADDR); \
  968. _ezchip_macro_read_value_ &= 0x7;\
  969. }
  970. #define _ENABLE_CLOCK_clk_vdec_bus_ {}
  971. #define _DIVIDE_CLOCK_clk_vdec_bus_(div) { \
  972. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_bus_ctrl_REG_ADDR); \
  973. _ezchip_macro_read_value_ &= ~(0xF); \
  974. _ezchip_macro_read_value_ |= (div&0xF); \
  975. MA_OUTW(clk_vdec_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  976. }
  977. #define _GET_CLOCK_DIVIDE_STATUS_clk_vdec_bus_(_ezchip_macro_read_value_) { \
  978. _ezchip_macro_read_value_=MA_INW(clk_vdec_bus_ctrl_REG_ADDR); \
  979. _ezchip_macro_read_value_ &= 0xf;\
  980. }
  981. #define _ENABLE_CLOCK_clk_vdec_axi_ { \
  982. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_axi_ctrl_REG_ADDR); \
  983. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  984. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  985. MA_OUTW(clk_vdec_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  986. }
  987. #define _DISABLE_CLOCK_clk_vdec_axi_ { \
  988. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_axi_ctrl_REG_ADDR); \
  989. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  990. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  991. MA_OUTW(clk_vdec_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  992. }
  993. #define _GET_CLOCK_ENABLE_STATUS_clk_vdec_axi_(_ezchip_macro_read_value_) { \
  994. _ezchip_macro_read_value_=MA_INW(clk_vdec_axi_ctrl_REG_ADDR) >> 31; \
  995. _ezchip_macro_read_value_ &= 0x1;\
  996. }
  997. #define _ENABLE_CLOCK_clk_vdecbrg_mainclk_ { \
  998. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdecbrg_mainclk_ctrl_REG_ADDR); \
  999. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1000. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1001. MA_OUTW(clk_vdecbrg_mainclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1002. }
  1003. #define _DISABLE_CLOCK_clk_vdecbrg_mainclk_ { \
  1004. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdecbrg_mainclk_ctrl_REG_ADDR); \
  1005. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1006. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1007. MA_OUTW(clk_vdecbrg_mainclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1008. }
  1009. #define _GET_CLOCK_ENABLE_STATUS_clk_vdecbrg_mainclk_(_ezchip_macro_read_value_) { \
  1010. _ezchip_macro_read_value_=MA_INW(clk_vdecbrg_mainclk_ctrl_REG_ADDR) >> 31; \
  1011. _ezchip_macro_read_value_ &= 0x1;\
  1012. }
  1013. #define _ENABLE_CLOCK_clk_vdec_bclk_ { \
  1014. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_bclk_ctrl_REG_ADDR); \
  1015. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1016. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1017. MA_OUTW(clk_vdec_bclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1018. }
  1019. #define _DISABLE_CLOCK_clk_vdec_bclk_ { \
  1020. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_bclk_ctrl_REG_ADDR); \
  1021. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1022. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1023. MA_OUTW(clk_vdec_bclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1024. }
  1025. #define _GET_CLOCK_ENABLE_STATUS_clk_vdec_bclk_(_ezchip_macro_read_value_) { \
  1026. _ezchip_macro_read_value_=MA_INW(clk_vdec_bclk_ctrl_REG_ADDR) >> 31; \
  1027. _ezchip_macro_read_value_ &= 0x1;\
  1028. }
  1029. #define _DIVIDE_CLOCK_clk_vdec_bclk_(div) { \
  1030. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_bclk_ctrl_REG_ADDR); \
  1031. _ezchip_macro_read_value_ &= ~(0xF); \
  1032. _ezchip_macro_read_value_ |= (div&0xF); \
  1033. MA_OUTW(clk_vdec_bclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1034. }
  1035. #define _GET_CLOCK_DIVIDE_STATUS_clk_vdec_bclk_(_ezchip_macro_read_value_) { \
  1036. _ezchip_macro_read_value_=MA_INW(clk_vdec_bclk_ctrl_REG_ADDR); \
  1037. _ezchip_macro_read_value_ &= 0xf;\
  1038. }
  1039. #define _ENABLE_CLOCK_clk_vdec_cclk_ { \
  1040. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_cclk_ctrl_REG_ADDR); \
  1041. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1042. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1043. MA_OUTW(clk_vdec_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1044. }
  1045. #define _DISABLE_CLOCK_clk_vdec_cclk_ { \
  1046. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_cclk_ctrl_REG_ADDR); \
  1047. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1048. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1049. MA_OUTW(clk_vdec_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1050. }
  1051. #define _GET_CLOCK_ENABLE_STATUS_clk_vdec_cclk_(_ezchip_macro_read_value_) { \
  1052. _ezchip_macro_read_value_=MA_INW(clk_vdec_cclk_ctrl_REG_ADDR) >> 31; \
  1053. _ezchip_macro_read_value_ &= 0x1;\
  1054. }
  1055. #define _DIVIDE_CLOCK_clk_vdec_cclk_(div) { \
  1056. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_cclk_ctrl_REG_ADDR); \
  1057. _ezchip_macro_read_value_ &= ~(0xF); \
  1058. _ezchip_macro_read_value_ |= (div&0xF); \
  1059. MA_OUTW(clk_vdec_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1060. }
  1061. #define _GET_CLOCK_DIVIDE_STATUS_clk_vdec_cclk_(_ezchip_macro_read_value_) { \
  1062. _ezchip_macro_read_value_=MA_INW(clk_vdec_cclk_ctrl_REG_ADDR); \
  1063. _ezchip_macro_read_value_ &= 0xf;\
  1064. }
  1065. #define _ENABLE_CLOCK_clk_vdec_apb_ { \
  1066. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_apb_ctrl_REG_ADDR); \
  1067. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1068. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1069. MA_OUTW(clk_vdec_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1070. }
  1071. #define _DISABLE_CLOCK_clk_vdec_apb_ { \
  1072. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_apb_ctrl_REG_ADDR); \
  1073. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1074. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1075. MA_OUTW(clk_vdec_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1076. }
  1077. #define _GET_CLOCK_ENABLE_STATUS_clk_vdec_apb_(_ezchip_macro_read_value_) { \
  1078. _ezchip_macro_read_value_=MA_INW(clk_vdec_apb_ctrl_REG_ADDR) >> 31; \
  1079. _ezchip_macro_read_value_ &= 0x1;\
  1080. }
  1081. #define _ENABLE_CLOCK_clk_jpeg_axi_ { \
  1082. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_axi_ctrl_REG_ADDR); \
  1083. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1084. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1085. MA_OUTW(clk_jpeg_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1086. }
  1087. #define _DISABLE_CLOCK_clk_jpeg_axi_ { \
  1088. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_axi_ctrl_REG_ADDR); \
  1089. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1090. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1091. MA_OUTW(clk_jpeg_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1092. }
  1093. #define _GET_CLOCK_ENABLE_STATUS_clk_jpeg_axi_(_ezchip_macro_read_value_) { \
  1094. _ezchip_macro_read_value_=MA_INW(clk_jpeg_axi_ctrl_REG_ADDR) >> 31; \
  1095. _ezchip_macro_read_value_ &= 0x1;\
  1096. }
  1097. #define _DIVIDE_CLOCK_clk_jpeg_axi_(div) { \
  1098. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_axi_ctrl_REG_ADDR); \
  1099. _ezchip_macro_read_value_ &= ~(0xF); \
  1100. _ezchip_macro_read_value_ |= (div&0xF); \
  1101. MA_OUTW(clk_jpeg_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1102. }
  1103. #define _GET_CLOCK_DIVIDE_STATUS_clk_jpeg_axi_(_ezchip_macro_read_value_) { \
  1104. _ezchip_macro_read_value_=MA_INW(clk_jpeg_axi_ctrl_REG_ADDR); \
  1105. _ezchip_macro_read_value_ &= 0xf;\
  1106. }
  1107. #define _ENABLE_CLOCK_clk_jpeg_cclk_ { \
  1108. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_cclk_ctrl_REG_ADDR); \
  1109. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1110. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1111. MA_OUTW(clk_jpeg_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1112. }
  1113. #define _DISABLE_CLOCK_clk_jpeg_cclk_ { \
  1114. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_cclk_ctrl_REG_ADDR); \
  1115. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1116. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1117. MA_OUTW(clk_jpeg_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1118. }
  1119. #define _GET_CLOCK_ENABLE_STATUS_clk_jpeg_cclk_(_ezchip_macro_read_value_) { \
  1120. _ezchip_macro_read_value_=MA_INW(clk_jpeg_cclk_ctrl_REG_ADDR) >> 31; \
  1121. _ezchip_macro_read_value_ &= 0x1;\
  1122. }
  1123. #define _DIVIDE_CLOCK_clk_jpeg_cclk_(div) { \
  1124. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_cclk_ctrl_REG_ADDR); \
  1125. _ezchip_macro_read_value_ &= ~(0xF); \
  1126. _ezchip_macro_read_value_ |= (div&0xF); \
  1127. MA_OUTW(clk_jpeg_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1128. }
  1129. #define _GET_CLOCK_DIVIDE_STATUS_clk_jpeg_cclk_(_ezchip_macro_read_value_) { \
  1130. _ezchip_macro_read_value_=MA_INW(clk_jpeg_cclk_ctrl_REG_ADDR); \
  1131. _ezchip_macro_read_value_ &= 0xf;\
  1132. }
  1133. #define _ENABLE_CLOCK_clk_jpeg_apb_ { \
  1134. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_apb_ctrl_REG_ADDR); \
  1135. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1136. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1137. MA_OUTW(clk_jpeg_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1138. }
  1139. #define _DISABLE_CLOCK_clk_jpeg_apb_ { \
  1140. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_apb_ctrl_REG_ADDR); \
  1141. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1142. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1143. MA_OUTW(clk_jpeg_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1144. }
  1145. #define _GET_CLOCK_ENABLE_STATUS_clk_jpeg_apb_(_ezchip_macro_read_value_) { \
  1146. _ezchip_macro_read_value_=MA_INW(clk_jpeg_apb_ctrl_REG_ADDR) >> 31; \
  1147. _ezchip_macro_read_value_ &= 0x1;\
  1148. }
  1149. #define _ENABLE_CLOCK_clk_gc300_2x_ { \
  1150. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gc300_2x_ctrl_REG_ADDR); \
  1151. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1152. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1153. MA_OUTW(clk_gc300_2x_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1154. }
  1155. #define _DISABLE_CLOCK_clk_gc300_2x_ { \
  1156. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gc300_2x_ctrl_REG_ADDR); \
  1157. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1158. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1159. MA_OUTW(clk_gc300_2x_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1160. }
  1161. #define _GET_CLOCK_ENABLE_STATUS_clk_gc300_2x_(_ezchip_macro_read_value_) { \
  1162. _ezchip_macro_read_value_=MA_INW(clk_gc300_2x_ctrl_REG_ADDR) >> 31; \
  1163. _ezchip_macro_read_value_ &= 0x1;\
  1164. }
  1165. #define _DIVIDE_CLOCK_clk_gc300_2x_(div) { \
  1166. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gc300_2x_ctrl_REG_ADDR); \
  1167. _ezchip_macro_read_value_ &= ~(0xF); \
  1168. _ezchip_macro_read_value_ |= (div&0xF); \
  1169. MA_OUTW(clk_gc300_2x_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1170. }
  1171. #define _GET_CLOCK_DIVIDE_STATUS_clk_gc300_2x_(_ezchip_macro_read_value_) { \
  1172. _ezchip_macro_read_value_=MA_INW(clk_gc300_2x_ctrl_REG_ADDR); \
  1173. _ezchip_macro_read_value_ &= 0xf;\
  1174. }
  1175. #define _ENABLE_CLOCK_clk_gc300_ahb_ { \
  1176. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gc300_ahb_ctrl_REG_ADDR); \
  1177. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1178. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1179. MA_OUTW(clk_gc300_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1180. }
  1181. #define _DISABLE_CLOCK_clk_gc300_ahb_ { \
  1182. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gc300_ahb_ctrl_REG_ADDR); \
  1183. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1184. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1185. MA_OUTW(clk_gc300_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1186. }
  1187. #define _GET_CLOCK_ENABLE_STATUS_clk_gc300_ahb_(_ezchip_macro_read_value_) { \
  1188. _ezchip_macro_read_value_=MA_INW(clk_gc300_ahb_ctrl_REG_ADDR) >> 31; \
  1189. _ezchip_macro_read_value_ &= 0x1;\
  1190. }
  1191. #define _ENABLE_CLOCK_clk_jpcgc300_axibus_ {}
  1192. #define _DIVIDE_CLOCK_clk_jpcgc300_axibus_(div) { \
  1193. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpcgc300_axibus_ctrl_REG_ADDR); \
  1194. _ezchip_macro_read_value_ &= ~(0xF); \
  1195. _ezchip_macro_read_value_ |= (div&0xF); \
  1196. MA_OUTW(clk_jpcgc300_axibus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1197. }
  1198. #define _GET_CLOCK_DIVIDE_STATUS_clk_jpcgc300_axibus_(_ezchip_macro_read_value_) { \
  1199. _ezchip_macro_read_value_=MA_INW(clk_jpcgc300_axibus_ctrl_REG_ADDR); \
  1200. _ezchip_macro_read_value_ &= 0xf;\
  1201. }
  1202. #define _ENABLE_CLOCK_clk_gc300_axi_ { \
  1203. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gc300_axi_ctrl_REG_ADDR); \
  1204. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1205. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1206. MA_OUTW(clk_gc300_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1207. }
  1208. #define _DISABLE_CLOCK_clk_gc300_axi_ { \
  1209. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gc300_axi_ctrl_REG_ADDR); \
  1210. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1211. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1212. MA_OUTW(clk_gc300_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1213. }
  1214. #define _GET_CLOCK_ENABLE_STATUS_clk_gc300_axi_(_ezchip_macro_read_value_) { \
  1215. _ezchip_macro_read_value_=MA_INW(clk_gc300_axi_ctrl_REG_ADDR) >> 31; \
  1216. _ezchip_macro_read_value_ &= 0x1;\
  1217. }
  1218. #define _ENABLE_CLOCK_clk_jpcgc300_mainclk_ { \
  1219. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpcgc300_mainclk_ctrl_REG_ADDR); \
  1220. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1221. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1222. MA_OUTW(clk_jpcgc300_mainclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1223. }
  1224. #define _DISABLE_CLOCK_clk_jpcgc300_mainclk_ { \
  1225. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpcgc300_mainclk_ctrl_REG_ADDR); \
  1226. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1227. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1228. MA_OUTW(clk_jpcgc300_mainclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1229. }
  1230. #define _GET_CLOCK_ENABLE_STATUS_clk_jpcgc300_mainclk_(_ezchip_macro_read_value_) { \
  1231. _ezchip_macro_read_value_=MA_INW(clk_jpcgc300_mainclk_ctrl_REG_ADDR) >> 31; \
  1232. _ezchip_macro_read_value_ &= 0x1;\
  1233. }
  1234. #define _ENABLE_CLOCK_clk_venc_bus_ {}
  1235. #define _DIVIDE_CLOCK_clk_venc_bus_(div) { \
  1236. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_bus_ctrl_REG_ADDR); \
  1237. _ezchip_macro_read_value_ &= ~(0xF); \
  1238. _ezchip_macro_read_value_ |= (div&0xF); \
  1239. MA_OUTW(clk_venc_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1240. }
  1241. #define _GET_CLOCK_DIVIDE_STATUS_clk_venc_bus_(_ezchip_macro_read_value_) { \
  1242. _ezchip_macro_read_value_=MA_INW(clk_venc_bus_ctrl_REG_ADDR); \
  1243. _ezchip_macro_read_value_ &= 0xf;\
  1244. }
  1245. #define _ENABLE_CLOCK_clk_venc_axi_ { \
  1246. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_axi_ctrl_REG_ADDR); \
  1247. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1248. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1249. MA_OUTW(clk_venc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1250. }
  1251. #define _DISABLE_CLOCK_clk_venc_axi_ { \
  1252. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_axi_ctrl_REG_ADDR); \
  1253. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1254. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1255. MA_OUTW(clk_venc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1256. }
  1257. #define _GET_CLOCK_ENABLE_STATUS_clk_venc_axi_(_ezchip_macro_read_value_) { \
  1258. _ezchip_macro_read_value_=MA_INW(clk_venc_axi_ctrl_REG_ADDR) >> 31; \
  1259. _ezchip_macro_read_value_ &= 0x1;\
  1260. }
  1261. #define _ENABLE_CLOCK_clk_vencbrg_mainclk_ { \
  1262. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vencbrg_mainclk_ctrl_REG_ADDR); \
  1263. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1264. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1265. MA_OUTW(clk_vencbrg_mainclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1266. }
  1267. #define _DISABLE_CLOCK_clk_vencbrg_mainclk_ { \
  1268. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vencbrg_mainclk_ctrl_REG_ADDR); \
  1269. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1270. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1271. MA_OUTW(clk_vencbrg_mainclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1272. }
  1273. #define _GET_CLOCK_ENABLE_STATUS_clk_vencbrg_mainclk_(_ezchip_macro_read_value_) { \
  1274. _ezchip_macro_read_value_=MA_INW(clk_vencbrg_mainclk_ctrl_REG_ADDR) >> 31; \
  1275. _ezchip_macro_read_value_ &= 0x1;\
  1276. }
  1277. #define _ENABLE_CLOCK_clk_venc_bclk_ { \
  1278. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_bclk_ctrl_REG_ADDR); \
  1279. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1280. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1281. MA_OUTW(clk_venc_bclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1282. }
  1283. #define _DISABLE_CLOCK_clk_venc_bclk_ { \
  1284. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_bclk_ctrl_REG_ADDR); \
  1285. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1286. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1287. MA_OUTW(clk_venc_bclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1288. }
  1289. #define _GET_CLOCK_ENABLE_STATUS_clk_venc_bclk_(_ezchip_macro_read_value_) { \
  1290. _ezchip_macro_read_value_=MA_INW(clk_venc_bclk_ctrl_REG_ADDR) >> 31; \
  1291. _ezchip_macro_read_value_ &= 0x1;\
  1292. }
  1293. #define _DIVIDE_CLOCK_clk_venc_bclk_(div) { \
  1294. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_bclk_ctrl_REG_ADDR); \
  1295. _ezchip_macro_read_value_ &= ~(0xF); \
  1296. _ezchip_macro_read_value_ |= (div&0xF); \
  1297. MA_OUTW(clk_venc_bclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1298. }
  1299. #define _GET_CLOCK_DIVIDE_STATUS_clk_venc_bclk_(_ezchip_macro_read_value_) { \
  1300. _ezchip_macro_read_value_=MA_INW(clk_venc_bclk_ctrl_REG_ADDR); \
  1301. _ezchip_macro_read_value_ &= 0xf;\
  1302. }
  1303. #define _ENABLE_CLOCK_clk_venc_cclk_ { \
  1304. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_cclk_ctrl_REG_ADDR); \
  1305. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1306. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1307. MA_OUTW(clk_venc_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1308. }
  1309. #define _DISABLE_CLOCK_clk_venc_cclk_ { \
  1310. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_cclk_ctrl_REG_ADDR); \
  1311. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1312. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1313. MA_OUTW(clk_venc_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1314. }
  1315. #define _GET_CLOCK_ENABLE_STATUS_clk_venc_cclk_(_ezchip_macro_read_value_) { \
  1316. _ezchip_macro_read_value_=MA_INW(clk_venc_cclk_ctrl_REG_ADDR) >> 31; \
  1317. _ezchip_macro_read_value_ &= 0x1;\
  1318. }
  1319. #define _DIVIDE_CLOCK_clk_venc_cclk_(div) { \
  1320. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_cclk_ctrl_REG_ADDR); \
  1321. _ezchip_macro_read_value_ &= ~(0xF); \
  1322. _ezchip_macro_read_value_ |= (div&0xF); \
  1323. MA_OUTW(clk_venc_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1324. }
  1325. #define _GET_CLOCK_DIVIDE_STATUS_clk_venc_cclk_(_ezchip_macro_read_value_) { \
  1326. _ezchip_macro_read_value_=MA_INW(clk_venc_cclk_ctrl_REG_ADDR); \
  1327. _ezchip_macro_read_value_ &= 0xf;\
  1328. }
  1329. #define _ENABLE_CLOCK_clk_venc_apb_ { \
  1330. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_apb_ctrl_REG_ADDR); \
  1331. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1332. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1333. MA_OUTW(clk_venc_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1334. }
  1335. #define _DISABLE_CLOCK_clk_venc_apb_ { \
  1336. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_apb_ctrl_REG_ADDR); \
  1337. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1338. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1339. MA_OUTW(clk_venc_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1340. }
  1341. #define _GET_CLOCK_ENABLE_STATUS_clk_venc_apb_(_ezchip_macro_read_value_) { \
  1342. _ezchip_macro_read_value_=MA_INW(clk_venc_apb_ctrl_REG_ADDR) >> 31; \
  1343. _ezchip_macro_read_value_ &= 0x1;\
  1344. }
  1345. #define _ENABLE_CLOCK_clk_ddrpll_div2_ { \
  1346. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div2_ctrl_REG_ADDR); \
  1347. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1348. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1349. MA_OUTW(clk_ddrpll_div2_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1350. }
  1351. #define _DISABLE_CLOCK_clk_ddrpll_div2_ { \
  1352. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div2_ctrl_REG_ADDR); \
  1353. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1354. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1355. MA_OUTW(clk_ddrpll_div2_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1356. }
  1357. #define _GET_CLOCK_ENABLE_STATUS_clk_ddrpll_div2_(_ezchip_macro_read_value_) { \
  1358. _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div2_ctrl_REG_ADDR) >> 31; \
  1359. _ezchip_macro_read_value_ &= 0x1;\
  1360. }
  1361. #define _DIVIDE_CLOCK_clk_ddrpll_div2_(div) { \
  1362. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div2_ctrl_REG_ADDR); \
  1363. _ezchip_macro_read_value_ &= ~(0x3); \
  1364. _ezchip_macro_read_value_ |= (div&0x3); \
  1365. MA_OUTW(clk_ddrpll_div2_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1366. }
  1367. #define _GET_CLOCK_DIVIDE_STATUS_clk_ddrpll_div2_(_ezchip_macro_read_value_) { \
  1368. _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div2_ctrl_REG_ADDR); \
  1369. _ezchip_macro_read_value_ &= 0x3;\
  1370. }
  1371. #define _ENABLE_CLOCK_clk_ddrpll_div4_ { \
  1372. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div4_ctrl_REG_ADDR); \
  1373. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1374. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1375. MA_OUTW(clk_ddrpll_div4_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1376. }
  1377. #define _DISABLE_CLOCK_clk_ddrpll_div4_ { \
  1378. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div4_ctrl_REG_ADDR); \
  1379. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1380. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1381. MA_OUTW(clk_ddrpll_div4_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1382. }
  1383. #define _GET_CLOCK_ENABLE_STATUS_clk_ddrpll_div4_(_ezchip_macro_read_value_) { \
  1384. _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div4_ctrl_REG_ADDR) >> 31; \
  1385. _ezchip_macro_read_value_ &= 0x1;\
  1386. }
  1387. #define _DIVIDE_CLOCK_clk_ddrpll_div4_(div) { \
  1388. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div4_ctrl_REG_ADDR); \
  1389. _ezchip_macro_read_value_ &= ~(0x3); \
  1390. _ezchip_macro_read_value_ |= (div&0x3); \
  1391. MA_OUTW(clk_ddrpll_div4_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1392. }
  1393. #define _GET_CLOCK_DIVIDE_STATUS_clk_ddrpll_div4_(_ezchip_macro_read_value_) { \
  1394. _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div4_ctrl_REG_ADDR); \
  1395. _ezchip_macro_read_value_ &= 0x3;\
  1396. }
  1397. #define _ENABLE_CLOCK_clk_ddrpll_div8_ { \
  1398. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div8_ctrl_REG_ADDR); \
  1399. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1400. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1401. MA_OUTW(clk_ddrpll_div8_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1402. }
  1403. #define _DISABLE_CLOCK_clk_ddrpll_div8_ { \
  1404. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div8_ctrl_REG_ADDR); \
  1405. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1406. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1407. MA_OUTW(clk_ddrpll_div8_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1408. }
  1409. #define _GET_CLOCK_ENABLE_STATUS_clk_ddrpll_div8_(_ezchip_macro_read_value_) { \
  1410. _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div8_ctrl_REG_ADDR) >> 31; \
  1411. _ezchip_macro_read_value_ &= 0x1;\
  1412. }
  1413. #define _DIVIDE_CLOCK_clk_ddrpll_div8_(div) { \
  1414. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div8_ctrl_REG_ADDR); \
  1415. _ezchip_macro_read_value_ &= ~(0x3); \
  1416. _ezchip_macro_read_value_ |= (div&0x3); \
  1417. MA_OUTW(clk_ddrpll_div8_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1418. }
  1419. #define _GET_CLOCK_DIVIDE_STATUS_clk_ddrpll_div8_(_ezchip_macro_read_value_) { \
  1420. _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div8_ctrl_REG_ADDR); \
  1421. _ezchip_macro_read_value_ &= 0x3;\
  1422. }
  1423. #define _ENABLE_CLOCK_clk_ddrosc_div2_ { \
  1424. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrosc_div2_ctrl_REG_ADDR); \
  1425. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1426. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1427. MA_OUTW(clk_ddrosc_div2_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1428. }
  1429. #define _DISABLE_CLOCK_clk_ddrosc_div2_ { \
  1430. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrosc_div2_ctrl_REG_ADDR); \
  1431. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1432. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1433. MA_OUTW(clk_ddrosc_div2_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1434. }
  1435. #define _GET_CLOCK_ENABLE_STATUS_clk_ddrosc_div2_(_ezchip_macro_read_value_) { \
  1436. _ezchip_macro_read_value_=MA_INW(clk_ddrosc_div2_ctrl_REG_ADDR) >> 31; \
  1437. _ezchip_macro_read_value_ &= 0x1;\
  1438. }
  1439. #define _DIVIDE_CLOCK_clk_ddrosc_div2_(div) { \
  1440. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrosc_div2_ctrl_REG_ADDR); \
  1441. _ezchip_macro_read_value_ &= ~(0x3); \
  1442. _ezchip_macro_read_value_ |= (div&0x3); \
  1443. MA_OUTW(clk_ddrosc_div2_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1444. }
  1445. #define _GET_CLOCK_DIVIDE_STATUS_clk_ddrosc_div2_(_ezchip_macro_read_value_) { \
  1446. _ezchip_macro_read_value_=MA_INW(clk_ddrosc_div2_ctrl_REG_ADDR); \
  1447. _ezchip_macro_read_value_ &= 0x3;\
  1448. }
  1449. #define _ENABLE_CLOCK_clk_ddrc0_ { \
  1450. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR); \
  1451. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1452. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1453. MA_OUTW(clk_ddrc0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1454. }
  1455. #define _DISABLE_CLOCK_clk_ddrc0_ { \
  1456. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR); \
  1457. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1458. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1459. MA_OUTW(clk_ddrc0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1460. }
  1461. #define _GET_CLOCK_ENABLE_STATUS_clk_ddrc0_(_ezchip_macro_read_value_) { \
  1462. _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR) >> 31; \
  1463. _ezchip_macro_read_value_ &= 0x1;\
  1464. }
  1465. #define _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrosc_div2_ { \
  1466. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR); \
  1467. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  1468. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  1469. MA_OUTW(clk_ddrc0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1470. }
  1471. #define _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div2_ { \
  1472. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR); \
  1473. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  1474. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  1475. MA_OUTW(clk_ddrc0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1476. }
  1477. #define _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div4_ { \
  1478. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR); \
  1479. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  1480. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  1481. MA_OUTW(clk_ddrc0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1482. }
  1483. #define _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div8_ { \
  1484. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR); \
  1485. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  1486. _ezchip_macro_read_value_ |= (0x3&0x3)<<24; \
  1487. MA_OUTW(clk_ddrc0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1488. }
  1489. #define _GET_CLOCK_SOURCE_STATUS_clk_ddrc0_(_ezchip_macro_read_value_) { \
  1490. _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR) >> 24; \
  1491. _ezchip_macro_read_value_ &= 0x3;\
  1492. }
  1493. #define _ENABLE_CLOCK_clk_ddrc1_ { \
  1494. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR); \
  1495. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1496. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1497. MA_OUTW(clk_ddrc1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1498. }
  1499. #define _DISABLE_CLOCK_clk_ddrc1_ { \
  1500. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR); \
  1501. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1502. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1503. MA_OUTW(clk_ddrc1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1504. }
  1505. #define _GET_CLOCK_ENABLE_STATUS_clk_ddrc1_(_ezchip_macro_read_value_) { \
  1506. _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR) >> 31; \
  1507. _ezchip_macro_read_value_ &= 0x1;\
  1508. }
  1509. #define _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrosc_div2_ { \
  1510. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR); \
  1511. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  1512. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  1513. MA_OUTW(clk_ddrc1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1514. }
  1515. #define _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div2_ { \
  1516. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR); \
  1517. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  1518. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  1519. MA_OUTW(clk_ddrc1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1520. }
  1521. #define _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div4_ { \
  1522. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR); \
  1523. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  1524. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  1525. MA_OUTW(clk_ddrc1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1526. }
  1527. #define _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div8_ { \
  1528. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR); \
  1529. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  1530. _ezchip_macro_read_value_ |= (0x3&0x3)<<24; \
  1531. MA_OUTW(clk_ddrc1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1532. }
  1533. #define _GET_CLOCK_SOURCE_STATUS_clk_ddrc1_(_ezchip_macro_read_value_) { \
  1534. _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR) >> 24; \
  1535. _ezchip_macro_read_value_ &= 0x3;\
  1536. }
  1537. #define _ENABLE_CLOCK_clk_ddrphy_apb_ { \
  1538. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrphy_apb_ctrl_REG_ADDR); \
  1539. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1540. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1541. MA_OUTW(clk_ddrphy_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1542. }
  1543. #define _DISABLE_CLOCK_clk_ddrphy_apb_ { \
  1544. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrphy_apb_ctrl_REG_ADDR); \
  1545. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1546. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1547. MA_OUTW(clk_ddrphy_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1548. }
  1549. #define _GET_CLOCK_ENABLE_STATUS_clk_ddrphy_apb_(_ezchip_macro_read_value_) { \
  1550. _ezchip_macro_read_value_=MA_INW(clk_ddrphy_apb_ctrl_REG_ADDR) >> 31; \
  1551. _ezchip_macro_read_value_ &= 0x1;\
  1552. }
  1553. #define _ENABLE_CLOCK_clk_noc_rob_ {}
  1554. #define _DIVIDE_CLOCK_clk_noc_rob_(div) { \
  1555. uint32_t _ezchip_macro_read_value_=MA_INW(clk_noc_rob_ctrl_REG_ADDR); \
  1556. _ezchip_macro_read_value_ &= ~(0xF); \
  1557. _ezchip_macro_read_value_ |= (div&0xF); \
  1558. MA_OUTW(clk_noc_rob_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1559. }
  1560. #define _GET_CLOCK_DIVIDE_STATUS_clk_noc_rob_(_ezchip_macro_read_value_) { \
  1561. _ezchip_macro_read_value_=MA_INW(clk_noc_rob_ctrl_REG_ADDR); \
  1562. _ezchip_macro_read_value_ &= 0xf;\
  1563. }
  1564. #define _ENABLE_CLOCK_clk_noc_cog_ {}
  1565. #define _DIVIDE_CLOCK_clk_noc_cog_(div) { \
  1566. uint32_t _ezchip_macro_read_value_=MA_INW(clk_noc_cog_ctrl_REG_ADDR); \
  1567. _ezchip_macro_read_value_ &= ~(0xF); \
  1568. _ezchip_macro_read_value_ |= (div&0xF); \
  1569. MA_OUTW(clk_noc_cog_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1570. }
  1571. #define _GET_CLOCK_DIVIDE_STATUS_clk_noc_cog_(_ezchip_macro_read_value_) { \
  1572. _ezchip_macro_read_value_=MA_INW(clk_noc_cog_ctrl_REG_ADDR); \
  1573. _ezchip_macro_read_value_ &= 0xf;\
  1574. }
  1575. #define _ENABLE_CLOCK_clk_nne_ahb_ { \
  1576. uint32_t _ezchip_macro_read_value_=MA_INW(clk_nne_ahb_ctrl_REG_ADDR); \
  1577. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1578. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1579. MA_OUTW(clk_nne_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1580. }
  1581. #define _DISABLE_CLOCK_clk_nne_ahb_ { \
  1582. uint32_t _ezchip_macro_read_value_=MA_INW(clk_nne_ahb_ctrl_REG_ADDR); \
  1583. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1584. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1585. MA_OUTW(clk_nne_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1586. }
  1587. #define _GET_CLOCK_ENABLE_STATUS_clk_nne_ahb_(_ezchip_macro_read_value_) { \
  1588. _ezchip_macro_read_value_=MA_INW(clk_nne_ahb_ctrl_REG_ADDR) >> 31; \
  1589. _ezchip_macro_read_value_ &= 0x1;\
  1590. }
  1591. #define _ENABLE_CLOCK_clk_nnebus_src1_ {}
  1592. #define _DIVIDE_CLOCK_clk_nnebus_src1_(div) { \
  1593. uint32_t _ezchip_macro_read_value_=MA_INW(clk_nnebus_src1_ctrl_REG_ADDR); \
  1594. _ezchip_macro_read_value_ &= ~(0x7); \
  1595. _ezchip_macro_read_value_ |= (div&0x7); \
  1596. MA_OUTW(clk_nnebus_src1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1597. }
  1598. #define _GET_CLOCK_DIVIDE_STATUS_clk_nnebus_src1_(_ezchip_macro_read_value_) { \
  1599. _ezchip_macro_read_value_=MA_INW(clk_nnebus_src1_ctrl_REG_ADDR); \
  1600. _ezchip_macro_read_value_ &= 0x7;\
  1601. }
  1602. #define _ENABLE_CLOCK_clk_nne_bus_ {}
  1603. #define _SWITCH_CLOCK_clk_nne_bus_SOURCE_clk_cpu_axi_ { \
  1604. uint32_t _ezchip_macro_read_value_=MA_INW(clk_nne_bus_ctrl_REG_ADDR); \
  1605. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  1606. _ezchip_macro_read_value_ |= (0x0&0x1)<<24; \
  1607. MA_OUTW(clk_nne_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1608. }
  1609. #define _SWITCH_CLOCK_clk_nne_bus_SOURCE_clk_nnebus_src1_ { \
  1610. uint32_t _ezchip_macro_read_value_=MA_INW(clk_nne_bus_ctrl_REG_ADDR); \
  1611. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  1612. _ezchip_macro_read_value_ |= (0x1&0x1)<<24; \
  1613. MA_OUTW(clk_nne_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1614. }
  1615. #define _GET_CLOCK_SOURCE_STATUS_clk_nne_bus_(_ezchip_macro_read_value_) { \
  1616. _ezchip_macro_read_value_=MA_INW(clk_nne_bus_ctrl_REG_ADDR) >> 24; \
  1617. _ezchip_macro_read_value_ &= 0x1;\
  1618. }
  1619. #define _ENABLE_CLOCK_clk_nne_axi_ { \
  1620. uint32_t _ezchip_macro_read_value_=MA_INW(clk_nne_axi_ctrl_REG_ADDR); \
  1621. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1622. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1623. MA_OUTW(clk_nne_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1624. }
  1625. #define _DISABLE_CLOCK_clk_nne_axi_ { \
  1626. uint32_t _ezchip_macro_read_value_=MA_INW(clk_nne_axi_ctrl_REG_ADDR); \
  1627. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1628. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1629. MA_OUTW(clk_nne_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1630. }
  1631. #define _GET_CLOCK_ENABLE_STATUS_clk_nne_axi_(_ezchip_macro_read_value_) { \
  1632. _ezchip_macro_read_value_=MA_INW(clk_nne_axi_ctrl_REG_ADDR) >> 31; \
  1633. _ezchip_macro_read_value_ &= 0x1;\
  1634. }
  1635. #define _ENABLE_CLOCK_clk_nnenoc_axi_ { \
  1636. uint32_t _ezchip_macro_read_value_=MA_INW(clk_nnenoc_axi_ctrl_REG_ADDR); \
  1637. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1638. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1639. MA_OUTW(clk_nnenoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1640. }
  1641. #define _DISABLE_CLOCK_clk_nnenoc_axi_ { \
  1642. uint32_t _ezchip_macro_read_value_=MA_INW(clk_nnenoc_axi_ctrl_REG_ADDR); \
  1643. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1644. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1645. MA_OUTW(clk_nnenoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1646. }
  1647. #define _GET_CLOCK_ENABLE_STATUS_clk_nnenoc_axi_(_ezchip_macro_read_value_) { \
  1648. _ezchip_macro_read_value_=MA_INW(clk_nnenoc_axi_ctrl_REG_ADDR) >> 31; \
  1649. _ezchip_macro_read_value_ &= 0x1;\
  1650. }
  1651. #define _ENABLE_CLOCK_clk_dlaslv_axi_ { \
  1652. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dlaslv_axi_ctrl_REG_ADDR); \
  1653. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1654. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1655. MA_OUTW(clk_dlaslv_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1656. }
  1657. #define _DISABLE_CLOCK_clk_dlaslv_axi_ { \
  1658. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dlaslv_axi_ctrl_REG_ADDR); \
  1659. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1660. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1661. MA_OUTW(clk_dlaslv_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1662. }
  1663. #define _GET_CLOCK_ENABLE_STATUS_clk_dlaslv_axi_(_ezchip_macro_read_value_) { \
  1664. _ezchip_macro_read_value_=MA_INW(clk_dlaslv_axi_ctrl_REG_ADDR) >> 31; \
  1665. _ezchip_macro_read_value_ &= 0x1;\
  1666. }
  1667. #define _ENABLE_CLOCK_clk_dspx2c_axi_ { \
  1668. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dspx2c_axi_ctrl_REG_ADDR); \
  1669. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1670. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1671. MA_OUTW(clk_dspx2c_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1672. }
  1673. #define _DISABLE_CLOCK_clk_dspx2c_axi_ { \
  1674. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dspx2c_axi_ctrl_REG_ADDR); \
  1675. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1676. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1677. MA_OUTW(clk_dspx2c_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1678. }
  1679. #define _GET_CLOCK_ENABLE_STATUS_clk_dspx2c_axi_(_ezchip_macro_read_value_) { \
  1680. _ezchip_macro_read_value_=MA_INW(clk_dspx2c_axi_ctrl_REG_ADDR) >> 31; \
  1681. _ezchip_macro_read_value_ &= 0x1;\
  1682. }
  1683. #define _ENABLE_CLOCK_clk_hifi4_src_ {}
  1684. #define _DIVIDE_CLOCK_clk_hifi4_src_(div) { \
  1685. uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4_src_ctrl_REG_ADDR); \
  1686. _ezchip_macro_read_value_ &= ~(0x7); \
  1687. _ezchip_macro_read_value_ |= (div&0x7); \
  1688. MA_OUTW(clk_hifi4_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1689. }
  1690. #define _GET_CLOCK_DIVIDE_STATUS_clk_hifi4_src_(_ezchip_macro_read_value_) { \
  1691. _ezchip_macro_read_value_=MA_INW(clk_hifi4_src_ctrl_REG_ADDR); \
  1692. _ezchip_macro_read_value_ &= 0x7;\
  1693. }
  1694. #define _ENABLE_CLOCK_clk_hifi4_corefree_ {}
  1695. #define _DIVIDE_CLOCK_clk_hifi4_corefree_(div) { \
  1696. uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4_corefree_ctrl_REG_ADDR); \
  1697. _ezchip_macro_read_value_ &= ~(0xF); \
  1698. _ezchip_macro_read_value_ |= (div&0xF); \
  1699. MA_OUTW(clk_hifi4_corefree_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1700. }
  1701. #define _GET_CLOCK_DIVIDE_STATUS_clk_hifi4_corefree_(_ezchip_macro_read_value_) { \
  1702. _ezchip_macro_read_value_=MA_INW(clk_hifi4_corefree_ctrl_REG_ADDR); \
  1703. _ezchip_macro_read_value_ &= 0xf;\
  1704. }
  1705. #define _ENABLE_CLOCK_clk_hifi4_core_ { \
  1706. uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4_core_ctrl_REG_ADDR); \
  1707. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1708. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1709. MA_OUTW(clk_hifi4_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1710. }
  1711. #define _DISABLE_CLOCK_clk_hifi4_core_ { \
  1712. uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4_core_ctrl_REG_ADDR); \
  1713. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1714. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1715. MA_OUTW(clk_hifi4_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1716. }
  1717. #define _GET_CLOCK_ENABLE_STATUS_clk_hifi4_core_(_ezchip_macro_read_value_) { \
  1718. _ezchip_macro_read_value_=MA_INW(clk_hifi4_core_ctrl_REG_ADDR) >> 31; \
  1719. _ezchip_macro_read_value_ &= 0x1;\
  1720. }
  1721. #define _ENABLE_CLOCK_clk_hifi4_bus_ {}
  1722. #define _DIVIDE_CLOCK_clk_hifi4_bus_(div) { \
  1723. uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4_bus_ctrl_REG_ADDR); \
  1724. _ezchip_macro_read_value_ &= ~(0xF); \
  1725. _ezchip_macro_read_value_ |= (div&0xF); \
  1726. MA_OUTW(clk_hifi4_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1727. }
  1728. #define _GET_CLOCK_DIVIDE_STATUS_clk_hifi4_bus_(_ezchip_macro_read_value_) { \
  1729. _ezchip_macro_read_value_=MA_INW(clk_hifi4_bus_ctrl_REG_ADDR); \
  1730. _ezchip_macro_read_value_ &= 0xf;\
  1731. }
  1732. #define _ENABLE_CLOCK_clk_hifi4_axi_ { \
  1733. uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4_axi_ctrl_REG_ADDR); \
  1734. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1735. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1736. MA_OUTW(clk_hifi4_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1737. }
  1738. #define _DISABLE_CLOCK_clk_hifi4_axi_ { \
  1739. uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4_axi_ctrl_REG_ADDR); \
  1740. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1741. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1742. MA_OUTW(clk_hifi4_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1743. }
  1744. #define _GET_CLOCK_ENABLE_STATUS_clk_hifi4_axi_(_ezchip_macro_read_value_) { \
  1745. _ezchip_macro_read_value_=MA_INW(clk_hifi4_axi_ctrl_REG_ADDR) >> 31; \
  1746. _ezchip_macro_read_value_ &= 0x1;\
  1747. }
  1748. #define _ENABLE_CLOCK_clk_hifi4noc_axi_ { \
  1749. uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4noc_axi_ctrl_REG_ADDR); \
  1750. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1751. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1752. MA_OUTW(clk_hifi4noc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1753. }
  1754. #define _DISABLE_CLOCK_clk_hifi4noc_axi_ { \
  1755. uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4noc_axi_ctrl_REG_ADDR); \
  1756. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1757. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1758. MA_OUTW(clk_hifi4noc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1759. }
  1760. #define _GET_CLOCK_ENABLE_STATUS_clk_hifi4noc_axi_(_ezchip_macro_read_value_) { \
  1761. _ezchip_macro_read_value_=MA_INW(clk_hifi4noc_axi_ctrl_REG_ADDR) >> 31; \
  1762. _ezchip_macro_read_value_ &= 0x1;\
  1763. }
  1764. #define _ENABLE_CLOCK_clk_sgdma1p_bus_ {}
  1765. #define _DIVIDE_CLOCK_clk_sgdma1p_bus_(div) { \
  1766. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sgdma1p_bus_ctrl_REG_ADDR); \
  1767. _ezchip_macro_read_value_ &= ~(0xF); \
  1768. _ezchip_macro_read_value_ |= (div&0xF); \
  1769. MA_OUTW(clk_sgdma1p_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1770. }
  1771. #define _GET_CLOCK_DIVIDE_STATUS_clk_sgdma1p_bus_(_ezchip_macro_read_value_) { \
  1772. _ezchip_macro_read_value_=MA_INW(clk_sgdma1p_bus_ctrl_REG_ADDR); \
  1773. _ezchip_macro_read_value_ &= 0xf;\
  1774. }
  1775. #define _ENABLE_CLOCK_clk_sgdma1p_axi_ { \
  1776. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sgdma1p_axi_ctrl_REG_ADDR); \
  1777. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1778. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1779. MA_OUTW(clk_sgdma1p_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1780. }
  1781. #define _DISABLE_CLOCK_clk_sgdma1p_axi_ { \
  1782. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sgdma1p_axi_ctrl_REG_ADDR); \
  1783. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1784. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1785. MA_OUTW(clk_sgdma1p_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1786. }
  1787. #define _GET_CLOCK_ENABLE_STATUS_clk_sgdma1p_axi_(_ezchip_macro_read_value_) { \
  1788. _ezchip_macro_read_value_=MA_INW(clk_sgdma1p_axi_ctrl_REG_ADDR) >> 31; \
  1789. _ezchip_macro_read_value_ &= 0x1;\
  1790. }
  1791. #define _ENABLE_CLOCK_clk_dma1p_axi_ { \
  1792. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dma1p_axi_ctrl_REG_ADDR); \
  1793. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1794. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1795. MA_OUTW(clk_dma1p_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1796. }
  1797. #define _DISABLE_CLOCK_clk_dma1p_axi_ { \
  1798. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dma1p_axi_ctrl_REG_ADDR); \
  1799. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1800. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1801. MA_OUTW(clk_dma1p_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1802. }
  1803. #define _GET_CLOCK_ENABLE_STATUS_clk_dma1p_axi_(_ezchip_macro_read_value_) { \
  1804. _ezchip_macro_read_value_=MA_INW(clk_dma1p_axi_ctrl_REG_ADDR) >> 31; \
  1805. _ezchip_macro_read_value_ &= 0x1;\
  1806. }
  1807. #define _ENABLE_CLOCK_clk_x2c_axi_ { \
  1808. uint32_t _ezchip_macro_read_value_=MA_INW(clk_x2c_axi_ctrl_REG_ADDR); \
  1809. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1810. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1811. MA_OUTW(clk_x2c_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1812. }
  1813. #define _DISABLE_CLOCK_clk_x2c_axi_ { \
  1814. uint32_t _ezchip_macro_read_value_=MA_INW(clk_x2c_axi_ctrl_REG_ADDR); \
  1815. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1816. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1817. MA_OUTW(clk_x2c_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1818. }
  1819. #define _GET_CLOCK_ENABLE_STATUS_clk_x2c_axi_(_ezchip_macro_read_value_) { \
  1820. _ezchip_macro_read_value_=MA_INW(clk_x2c_axi_ctrl_REG_ADDR) >> 31; \
  1821. _ezchip_macro_read_value_ &= 0x1;\
  1822. }
  1823. #define _DIVIDE_CLOCK_clk_x2c_axi_(div) { \
  1824. uint32_t _ezchip_macro_read_value_=MA_INW(clk_x2c_axi_ctrl_REG_ADDR); \
  1825. _ezchip_macro_read_value_ &= ~(0xF); \
  1826. _ezchip_macro_read_value_ |= (div&0xF); \
  1827. MA_OUTW(clk_x2c_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1828. }
  1829. #define _GET_CLOCK_DIVIDE_STATUS_clk_x2c_axi_(_ezchip_macro_read_value_) { \
  1830. _ezchip_macro_read_value_=MA_INW(clk_x2c_axi_ctrl_REG_ADDR); \
  1831. _ezchip_macro_read_value_ &= 0xf;\
  1832. }
  1833. #define _ENABLE_CLOCK_clk_usb_bus_ {}
  1834. #define _DIVIDE_CLOCK_clk_usb_bus_(div) { \
  1835. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usb_bus_ctrl_REG_ADDR); \
  1836. _ezchip_macro_read_value_ &= ~(0xF); \
  1837. _ezchip_macro_read_value_ |= (div&0xF); \
  1838. MA_OUTW(clk_usb_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1839. }
  1840. #define _GET_CLOCK_DIVIDE_STATUS_clk_usb_bus_(_ezchip_macro_read_value_) { \
  1841. _ezchip_macro_read_value_=MA_INW(clk_usb_bus_ctrl_REG_ADDR); \
  1842. _ezchip_macro_read_value_ &= 0xf;\
  1843. }
  1844. #define _ENABLE_CLOCK_clk_usb_axi_ { \
  1845. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usb_axi_ctrl_REG_ADDR); \
  1846. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1847. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1848. MA_OUTW(clk_usb_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1849. }
  1850. #define _DISABLE_CLOCK_clk_usb_axi_ { \
  1851. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usb_axi_ctrl_REG_ADDR); \
  1852. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1853. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1854. MA_OUTW(clk_usb_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1855. }
  1856. #define _GET_CLOCK_ENABLE_STATUS_clk_usb_axi_(_ezchip_macro_read_value_) { \
  1857. _ezchip_macro_read_value_=MA_INW(clk_usb_axi_ctrl_REG_ADDR) >> 31; \
  1858. _ezchip_macro_read_value_ &= 0x1;\
  1859. }
  1860. #define _ENABLE_CLOCK_clk_usbnoc_axi_ { \
  1861. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbnoc_axi_ctrl_REG_ADDR); \
  1862. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1863. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1864. MA_OUTW(clk_usbnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1865. }
  1866. #define _DISABLE_CLOCK_clk_usbnoc_axi_ { \
  1867. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbnoc_axi_ctrl_REG_ADDR); \
  1868. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1869. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1870. MA_OUTW(clk_usbnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1871. }
  1872. #define _GET_CLOCK_ENABLE_STATUS_clk_usbnoc_axi_(_ezchip_macro_read_value_) { \
  1873. _ezchip_macro_read_value_=MA_INW(clk_usbnoc_axi_ctrl_REG_ADDR) >> 31; \
  1874. _ezchip_macro_read_value_ &= 0x1;\
  1875. }
  1876. #define _ENABLE_CLOCK_clk_usbphy_rootdiv_ {}
  1877. #define _DIVIDE_CLOCK_clk_usbphy_rootdiv_(div) { \
  1878. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_rootdiv_ctrl_REG_ADDR); \
  1879. _ezchip_macro_read_value_ &= ~(0x7); \
  1880. _ezchip_macro_read_value_ |= (div&0x7); \
  1881. MA_OUTW(clk_usbphy_rootdiv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1882. }
  1883. #define _GET_CLOCK_DIVIDE_STATUS_clk_usbphy_rootdiv_(_ezchip_macro_read_value_) { \
  1884. _ezchip_macro_read_value_=MA_INW(clk_usbphy_rootdiv_ctrl_REG_ADDR); \
  1885. _ezchip_macro_read_value_ &= 0x7;\
  1886. }
  1887. #define _ENABLE_CLOCK_clk_usbphy_125m_ { \
  1888. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_125m_ctrl_REG_ADDR); \
  1889. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1890. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1891. MA_OUTW(clk_usbphy_125m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1892. }
  1893. #define _DISABLE_CLOCK_clk_usbphy_125m_ { \
  1894. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_125m_ctrl_REG_ADDR); \
  1895. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1896. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1897. MA_OUTW(clk_usbphy_125m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1898. }
  1899. #define _GET_CLOCK_ENABLE_STATUS_clk_usbphy_125m_(_ezchip_macro_read_value_) { \
  1900. _ezchip_macro_read_value_=MA_INW(clk_usbphy_125m_ctrl_REG_ADDR) >> 31; \
  1901. _ezchip_macro_read_value_ &= 0x1;\
  1902. }
  1903. #define _DIVIDE_CLOCK_clk_usbphy_125m_(div) { \
  1904. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_125m_ctrl_REG_ADDR); \
  1905. _ezchip_macro_read_value_ &= ~(0xF); \
  1906. _ezchip_macro_read_value_ |= (div&0xF); \
  1907. MA_OUTW(clk_usbphy_125m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1908. }
  1909. #define _GET_CLOCK_DIVIDE_STATUS_clk_usbphy_125m_(_ezchip_macro_read_value_) { \
  1910. _ezchip_macro_read_value_=MA_INW(clk_usbphy_125m_ctrl_REG_ADDR); \
  1911. _ezchip_macro_read_value_ &= 0xf;\
  1912. }
  1913. #define _ENABLE_CLOCK_clk_usbphy_plldiv25m_ { \
  1914. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_plldiv25m_ctrl_REG_ADDR); \
  1915. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1916. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1917. MA_OUTW(clk_usbphy_plldiv25m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1918. }
  1919. #define _DISABLE_CLOCK_clk_usbphy_plldiv25m_ { \
  1920. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_plldiv25m_ctrl_REG_ADDR); \
  1921. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1922. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1923. MA_OUTW(clk_usbphy_plldiv25m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1924. }
  1925. #define _GET_CLOCK_ENABLE_STATUS_clk_usbphy_plldiv25m_(_ezchip_macro_read_value_) { \
  1926. _ezchip_macro_read_value_=MA_INW(clk_usbphy_plldiv25m_ctrl_REG_ADDR) >> 31; \
  1927. _ezchip_macro_read_value_ &= 0x1;\
  1928. }
  1929. #define _DIVIDE_CLOCK_clk_usbphy_plldiv25m_(div) { \
  1930. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_plldiv25m_ctrl_REG_ADDR); \
  1931. _ezchip_macro_read_value_ &= ~(0x3F); \
  1932. _ezchip_macro_read_value_ |= (div&0x3F); \
  1933. MA_OUTW(clk_usbphy_plldiv25m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1934. }
  1935. #define _GET_CLOCK_DIVIDE_STATUS_clk_usbphy_plldiv25m_(_ezchip_macro_read_value_) { \
  1936. _ezchip_macro_read_value_=MA_INW(clk_usbphy_plldiv25m_ctrl_REG_ADDR); \
  1937. _ezchip_macro_read_value_ &= 0x3f;\
  1938. }
  1939. #define _ENABLE_CLOCK_clk_usbphy_25m_ {}
  1940. #define _SWITCH_CLOCK_clk_usbphy_25m_SOURCE_clk_osc_sys_ { \
  1941. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_25m_ctrl_REG_ADDR); \
  1942. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  1943. _ezchip_macro_read_value_ |= (0x0&0x1)<<24; \
  1944. MA_OUTW(clk_usbphy_25m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1945. }
  1946. #define _SWITCH_CLOCK_clk_usbphy_25m_SOURCE_clk_usbphy_plldiv25m_ { \
  1947. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_25m_ctrl_REG_ADDR); \
  1948. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  1949. _ezchip_macro_read_value_ |= (0x1&0x1)<<24; \
  1950. MA_OUTW(clk_usbphy_25m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1951. }
  1952. #define _GET_CLOCK_SOURCE_STATUS_clk_usbphy_25m_(_ezchip_macro_read_value_) { \
  1953. _ezchip_macro_read_value_=MA_INW(clk_usbphy_25m_ctrl_REG_ADDR) >> 24; \
  1954. _ezchip_macro_read_value_ &= 0x1;\
  1955. }
  1956. #define _ENABLE_CLOCK_clk_audio_div_ {}
  1957. #define _DIVIDE_CLOCK_clk_audio_div_(div) { \
  1958. uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_div_ctrl_REG_ADDR); \
  1959. _ezchip_macro_read_value_ &= ~(0x3FFFF); \
  1960. _ezchip_macro_read_value_ |= (div&0x3FFFF); \
  1961. MA_OUTW(clk_audio_div_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1962. }
  1963. #define _GET_CLOCK_DIVIDE_STATUS_clk_audio_div_(_ezchip_macro_read_value_) { \
  1964. _ezchip_macro_read_value_=MA_INW(clk_audio_div_ctrl_REG_ADDR); \
  1965. _ezchip_macro_read_value_ &= 0x3ffff;\
  1966. }
  1967. #define _ENABLE_CLOCK_clk_audio_src_ { \
  1968. uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_src_ctrl_REG_ADDR); \
  1969. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1970. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1971. MA_OUTW(clk_audio_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1972. }
  1973. #define _DISABLE_CLOCK_clk_audio_src_ { \
  1974. uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_src_ctrl_REG_ADDR); \
  1975. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1976. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1977. MA_OUTW(clk_audio_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1978. }
  1979. #define _GET_CLOCK_ENABLE_STATUS_clk_audio_src_(_ezchip_macro_read_value_) { \
  1980. _ezchip_macro_read_value_=MA_INW(clk_audio_src_ctrl_REG_ADDR) >> 31; \
  1981. _ezchip_macro_read_value_ &= 0x1;\
  1982. }
  1983. #define _ENABLE_CLOCK_clk_audio_12288_ { \
  1984. uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_12288_ctrl_REG_ADDR); \
  1985. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1986. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1987. MA_OUTW(clk_audio_12288_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1988. }
  1989. #define _DISABLE_CLOCK_clk_audio_12288_ { \
  1990. uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_12288_ctrl_REG_ADDR); \
  1991. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1992. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1993. MA_OUTW(clk_audio_12288_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1994. }
  1995. #define _GET_CLOCK_ENABLE_STATUS_clk_audio_12288_(_ezchip_macro_read_value_) { \
  1996. _ezchip_macro_read_value_=MA_INW(clk_audio_12288_ctrl_REG_ADDR) >> 31; \
  1997. _ezchip_macro_read_value_ &= 0x1;\
  1998. }
  1999. #define _ENABLE_CLOCK_clk_vin_src_ { \
  2000. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_src_ctrl_REG_ADDR); \
  2001. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2002. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2003. MA_OUTW(clk_vin_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2004. }
  2005. #define _DISABLE_CLOCK_clk_vin_src_ { \
  2006. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_src_ctrl_REG_ADDR); \
  2007. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2008. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2009. MA_OUTW(clk_vin_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2010. }
  2011. #define _GET_CLOCK_ENABLE_STATUS_clk_vin_src_(_ezchip_macro_read_value_) { \
  2012. _ezchip_macro_read_value_=MA_INW(clk_vin_src_ctrl_REG_ADDR) >> 31; \
  2013. _ezchip_macro_read_value_ &= 0x1;\
  2014. }
  2015. #define _DIVIDE_CLOCK_clk_vin_src_(div) { \
  2016. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_src_ctrl_REG_ADDR); \
  2017. _ezchip_macro_read_value_ &= ~(0x7); \
  2018. _ezchip_macro_read_value_ |= (div&0x7); \
  2019. MA_OUTW(clk_vin_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2020. }
  2021. #define _GET_CLOCK_DIVIDE_STATUS_clk_vin_src_(_ezchip_macro_read_value_) { \
  2022. _ezchip_macro_read_value_=MA_INW(clk_vin_src_ctrl_REG_ADDR); \
  2023. _ezchip_macro_read_value_ &= 0x7;\
  2024. }
  2025. #define _ENABLE_CLOCK_clk_isp0_bus_ {}
  2026. #define _DIVIDE_CLOCK_clk_isp0_bus_(div) { \
  2027. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp0_bus_ctrl_REG_ADDR); \
  2028. _ezchip_macro_read_value_ &= ~(0xF); \
  2029. _ezchip_macro_read_value_ |= (div&0xF); \
  2030. MA_OUTW(clk_isp0_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2031. }
  2032. #define _GET_CLOCK_DIVIDE_STATUS_clk_isp0_bus_(_ezchip_macro_read_value_) { \
  2033. _ezchip_macro_read_value_=MA_INW(clk_isp0_bus_ctrl_REG_ADDR); \
  2034. _ezchip_macro_read_value_ &= 0xf;\
  2035. }
  2036. #define _ENABLE_CLOCK_clk_isp0_axi_ { \
  2037. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp0_axi_ctrl_REG_ADDR); \
  2038. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2039. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2040. MA_OUTW(clk_isp0_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2041. }
  2042. #define _DISABLE_CLOCK_clk_isp0_axi_ { \
  2043. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp0_axi_ctrl_REG_ADDR); \
  2044. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2045. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2046. MA_OUTW(clk_isp0_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2047. }
  2048. #define _GET_CLOCK_ENABLE_STATUS_clk_isp0_axi_(_ezchip_macro_read_value_) { \
  2049. _ezchip_macro_read_value_=MA_INW(clk_isp0_axi_ctrl_REG_ADDR) >> 31; \
  2050. _ezchip_macro_read_value_ &= 0x1;\
  2051. }
  2052. #define _ENABLE_CLOCK_clk_isp0noc_axi_ { \
  2053. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp0noc_axi_ctrl_REG_ADDR); \
  2054. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2055. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2056. MA_OUTW(clk_isp0noc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2057. }
  2058. #define _DISABLE_CLOCK_clk_isp0noc_axi_ { \
  2059. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp0noc_axi_ctrl_REG_ADDR); \
  2060. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2061. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2062. MA_OUTW(clk_isp0noc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2063. }
  2064. #define _GET_CLOCK_ENABLE_STATUS_clk_isp0noc_axi_(_ezchip_macro_read_value_) { \
  2065. _ezchip_macro_read_value_=MA_INW(clk_isp0noc_axi_ctrl_REG_ADDR) >> 31; \
  2066. _ezchip_macro_read_value_ &= 0x1;\
  2067. }
  2068. #define _ENABLE_CLOCK_clk_ispslv_axi_ { \
  2069. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ispslv_axi_ctrl_REG_ADDR); \
  2070. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2071. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2072. MA_OUTW(clk_ispslv_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2073. }
  2074. #define _DISABLE_CLOCK_clk_ispslv_axi_ { \
  2075. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ispslv_axi_ctrl_REG_ADDR); \
  2076. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2077. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2078. MA_OUTW(clk_ispslv_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2079. }
  2080. #define _GET_CLOCK_ENABLE_STATUS_clk_ispslv_axi_(_ezchip_macro_read_value_) { \
  2081. _ezchip_macro_read_value_=MA_INW(clk_ispslv_axi_ctrl_REG_ADDR) >> 31; \
  2082. _ezchip_macro_read_value_ &= 0x1;\
  2083. }
  2084. #define _ENABLE_CLOCK_clk_isp1_bus_ {}
  2085. #define _DIVIDE_CLOCK_clk_isp1_bus_(div) { \
  2086. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp1_bus_ctrl_REG_ADDR); \
  2087. _ezchip_macro_read_value_ &= ~(0xF); \
  2088. _ezchip_macro_read_value_ |= (div&0xF); \
  2089. MA_OUTW(clk_isp1_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2090. }
  2091. #define _GET_CLOCK_DIVIDE_STATUS_clk_isp1_bus_(_ezchip_macro_read_value_) { \
  2092. _ezchip_macro_read_value_=MA_INW(clk_isp1_bus_ctrl_REG_ADDR); \
  2093. _ezchip_macro_read_value_ &= 0xf;\
  2094. }
  2095. #define _ENABLE_CLOCK_clk_isp1_axi_ { \
  2096. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp1_axi_ctrl_REG_ADDR); \
  2097. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2098. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2099. MA_OUTW(clk_isp1_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2100. }
  2101. #define _DISABLE_CLOCK_clk_isp1_axi_ { \
  2102. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp1_axi_ctrl_REG_ADDR); \
  2103. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2104. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2105. MA_OUTW(clk_isp1_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2106. }
  2107. #define _GET_CLOCK_ENABLE_STATUS_clk_isp1_axi_(_ezchip_macro_read_value_) { \
  2108. _ezchip_macro_read_value_=MA_INW(clk_isp1_axi_ctrl_REG_ADDR) >> 31; \
  2109. _ezchip_macro_read_value_ &= 0x1;\
  2110. }
  2111. #define _ENABLE_CLOCK_clk_isp1noc_axi_ { \
  2112. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp1noc_axi_ctrl_REG_ADDR); \
  2113. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2114. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2115. MA_OUTW(clk_isp1noc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2116. }
  2117. #define _DISABLE_CLOCK_clk_isp1noc_axi_ { \
  2118. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp1noc_axi_ctrl_REG_ADDR); \
  2119. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2120. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2121. MA_OUTW(clk_isp1noc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2122. }
  2123. #define _GET_CLOCK_ENABLE_STATUS_clk_isp1noc_axi_(_ezchip_macro_read_value_) { \
  2124. _ezchip_macro_read_value_=MA_INW(clk_isp1noc_axi_ctrl_REG_ADDR) >> 31; \
  2125. _ezchip_macro_read_value_ &= 0x1;\
  2126. }
  2127. #define _ENABLE_CLOCK_clk_vin_bus_ {}
  2128. #define _DIVIDE_CLOCK_clk_vin_bus_(div) { \
  2129. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_bus_ctrl_REG_ADDR); \
  2130. _ezchip_macro_read_value_ &= ~(0xF); \
  2131. _ezchip_macro_read_value_ |= (div&0xF); \
  2132. MA_OUTW(clk_vin_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2133. }
  2134. #define _GET_CLOCK_DIVIDE_STATUS_clk_vin_bus_(_ezchip_macro_read_value_) { \
  2135. _ezchip_macro_read_value_=MA_INW(clk_vin_bus_ctrl_REG_ADDR); \
  2136. _ezchip_macro_read_value_ &= 0xf;\
  2137. }
  2138. #define _ENABLE_CLOCK_clk_vin_axi_ { \
  2139. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_axi_ctrl_REG_ADDR); \
  2140. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2141. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2142. MA_OUTW(clk_vin_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2143. }
  2144. #define _DISABLE_CLOCK_clk_vin_axi_ { \
  2145. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_axi_ctrl_REG_ADDR); \
  2146. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2147. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2148. MA_OUTW(clk_vin_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2149. }
  2150. #define _GET_CLOCK_ENABLE_STATUS_clk_vin_axi_(_ezchip_macro_read_value_) { \
  2151. _ezchip_macro_read_value_=MA_INW(clk_vin_axi_ctrl_REG_ADDR) >> 31; \
  2152. _ezchip_macro_read_value_ &= 0x1;\
  2153. }
  2154. #define _ENABLE_CLOCK_clk_vinnoc_axi_ { \
  2155. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vinnoc_axi_ctrl_REG_ADDR); \
  2156. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2157. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2158. MA_OUTW(clk_vinnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2159. }
  2160. #define _DISABLE_CLOCK_clk_vinnoc_axi_ { \
  2161. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vinnoc_axi_ctrl_REG_ADDR); \
  2162. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2163. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2164. MA_OUTW(clk_vinnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2165. }
  2166. #define _GET_CLOCK_ENABLE_STATUS_clk_vinnoc_axi_(_ezchip_macro_read_value_) { \
  2167. _ezchip_macro_read_value_=MA_INW(clk_vinnoc_axi_ctrl_REG_ADDR) >> 31; \
  2168. _ezchip_macro_read_value_ &= 0x1;\
  2169. }
  2170. #define _ENABLE_CLOCK_clk_vout_src_ { \
  2171. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vout_src_ctrl_REG_ADDR); \
  2172. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2173. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2174. MA_OUTW(clk_vout_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2175. }
  2176. #define _DISABLE_CLOCK_clk_vout_src_ { \
  2177. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vout_src_ctrl_REG_ADDR); \
  2178. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2179. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2180. MA_OUTW(clk_vout_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2181. }
  2182. #define _GET_CLOCK_ENABLE_STATUS_clk_vout_src_(_ezchip_macro_read_value_) { \
  2183. _ezchip_macro_read_value_=MA_INW(clk_vout_src_ctrl_REG_ADDR) >> 31; \
  2184. _ezchip_macro_read_value_ &= 0x1;\
  2185. }
  2186. #define _DIVIDE_CLOCK_clk_vout_src_(div) { \
  2187. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vout_src_ctrl_REG_ADDR); \
  2188. _ezchip_macro_read_value_ &= ~(0x7); \
  2189. _ezchip_macro_read_value_ |= (div&0x7); \
  2190. MA_OUTW(clk_vout_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2191. }
  2192. #define _GET_CLOCK_DIVIDE_STATUS_clk_vout_src_(_ezchip_macro_read_value_) { \
  2193. _ezchip_macro_read_value_=MA_INW(clk_vout_src_ctrl_REG_ADDR); \
  2194. _ezchip_macro_read_value_ &= 0x7;\
  2195. }
  2196. #define _ENABLE_CLOCK_clk_dispbus_src_ {}
  2197. #define _DIVIDE_CLOCK_clk_dispbus_src_(div) { \
  2198. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dispbus_src_ctrl_REG_ADDR); \
  2199. _ezchip_macro_read_value_ &= ~(0x7); \
  2200. _ezchip_macro_read_value_ |= (div&0x7); \
  2201. MA_OUTW(clk_dispbus_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2202. }
  2203. #define _GET_CLOCK_DIVIDE_STATUS_clk_dispbus_src_(_ezchip_macro_read_value_) { \
  2204. _ezchip_macro_read_value_=MA_INW(clk_dispbus_src_ctrl_REG_ADDR); \
  2205. _ezchip_macro_read_value_ &= 0x7;\
  2206. }
  2207. #define _ENABLE_CLOCK_clk_disp_bus_ {}
  2208. #define _DIVIDE_CLOCK_clk_disp_bus_(div) { \
  2209. uint32_t _ezchip_macro_read_value_=MA_INW(clk_disp_bus_ctrl_REG_ADDR); \
  2210. _ezchip_macro_read_value_ &= ~(0x7); \
  2211. _ezchip_macro_read_value_ |= (div&0x7); \
  2212. MA_OUTW(clk_disp_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2213. }
  2214. #define _GET_CLOCK_DIVIDE_STATUS_clk_disp_bus_(_ezchip_macro_read_value_) { \
  2215. _ezchip_macro_read_value_=MA_INW(clk_disp_bus_ctrl_REG_ADDR); \
  2216. _ezchip_macro_read_value_ &= 0x7;\
  2217. }
  2218. #define _ENABLE_CLOCK_clk_disp_axi_ { \
  2219. uint32_t _ezchip_macro_read_value_=MA_INW(clk_disp_axi_ctrl_REG_ADDR); \
  2220. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2221. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2222. MA_OUTW(clk_disp_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2223. }
  2224. #define _DISABLE_CLOCK_clk_disp_axi_ { \
  2225. uint32_t _ezchip_macro_read_value_=MA_INW(clk_disp_axi_ctrl_REG_ADDR); \
  2226. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2227. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2228. MA_OUTW(clk_disp_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2229. }
  2230. #define _GET_CLOCK_ENABLE_STATUS_clk_disp_axi_(_ezchip_macro_read_value_) { \
  2231. _ezchip_macro_read_value_=MA_INW(clk_disp_axi_ctrl_REG_ADDR) >> 31; \
  2232. _ezchip_macro_read_value_ &= 0x1;\
  2233. }
  2234. #define _ENABLE_CLOCK_clk_dispnoc_axi_ { \
  2235. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dispnoc_axi_ctrl_REG_ADDR); \
  2236. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2237. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2238. MA_OUTW(clk_dispnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2239. }
  2240. #define _DISABLE_CLOCK_clk_dispnoc_axi_ { \
  2241. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dispnoc_axi_ctrl_REG_ADDR); \
  2242. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2243. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2244. MA_OUTW(clk_dispnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2245. }
  2246. #define _GET_CLOCK_ENABLE_STATUS_clk_dispnoc_axi_(_ezchip_macro_read_value_) { \
  2247. _ezchip_macro_read_value_=MA_INW(clk_dispnoc_axi_ctrl_REG_ADDR) >> 31; \
  2248. _ezchip_macro_read_value_ &= 0x1;\
  2249. }
  2250. #define _ENABLE_CLOCK_clk_sdio0_ahb_ { \
  2251. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio0_ahb_ctrl_REG_ADDR); \
  2252. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2253. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2254. MA_OUTW(clk_sdio0_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2255. }
  2256. #define _DISABLE_CLOCK_clk_sdio0_ahb_ { \
  2257. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio0_ahb_ctrl_REG_ADDR); \
  2258. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2259. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2260. MA_OUTW(clk_sdio0_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2261. }
  2262. #define _GET_CLOCK_ENABLE_STATUS_clk_sdio0_ahb_(_ezchip_macro_read_value_) { \
  2263. _ezchip_macro_read_value_=MA_INW(clk_sdio0_ahb_ctrl_REG_ADDR) >> 31; \
  2264. _ezchip_macro_read_value_ &= 0x1;\
  2265. }
  2266. #define _ENABLE_CLOCK_clk_sdio0_cclkint_ { \
  2267. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_ctrl_REG_ADDR); \
  2268. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2269. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2270. MA_OUTW(clk_sdio0_cclkint_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2271. }
  2272. #define _DISABLE_CLOCK_clk_sdio0_cclkint_ { \
  2273. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_ctrl_REG_ADDR); \
  2274. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2275. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2276. MA_OUTW(clk_sdio0_cclkint_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2277. }
  2278. #define _GET_CLOCK_ENABLE_STATUS_clk_sdio0_cclkint_(_ezchip_macro_read_value_) { \
  2279. _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_ctrl_REG_ADDR) >> 31; \
  2280. _ezchip_macro_read_value_ &= 0x1;\
  2281. }
  2282. #define _DIVIDE_CLOCK_clk_sdio0_cclkint_(div) { \
  2283. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_ctrl_REG_ADDR); \
  2284. _ezchip_macro_read_value_ &= ~(0x1F); \
  2285. _ezchip_macro_read_value_ |= (div&0x1F); \
  2286. MA_OUTW(clk_sdio0_cclkint_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2287. }
  2288. #define _GET_CLOCK_DIVIDE_STATUS_clk_sdio0_cclkint_(_ezchip_macro_read_value_) { \
  2289. _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_ctrl_REG_ADDR); \
  2290. _ezchip_macro_read_value_ &= 0x1f;\
  2291. }
  2292. #define _ENABLE_CLOCK_clk_sdio0_cclkint_inv_ {}
  2293. #define _SET_CLOCK_clk_sdio0_cclkint_inv_POLARITY_ { \
  2294. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_inv_ctrl_REG_ADDR); \
  2295. _ezchip_macro_read_value_ &= ~(0x1<<30); \
  2296. _ezchip_macro_read_value_ |= (0x1&0x1)<<30; \
  2297. MA_OUTW(clk_sdio0_cclkint_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2298. }
  2299. #define _UNSET_CLOCK_clk_sdio0_cclkint_inv_POLARITY_ { \
  2300. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_inv_ctrl_REG_ADDR); \
  2301. _ezchip_macro_read_value_ &= ~(0x1<<30); \
  2302. _ezchip_macro_read_value_ |= (0x0&0x1)<<30; \
  2303. MA_OUTW(clk_sdio0_cclkint_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2304. }
  2305. #define _GET_CLOCK_POLARITY_STATUS_clk_sdio0_cclkint_inv_(_ezchip_macro_read_value_) { \
  2306. _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_inv_ctrl_REG_ADDR) >> 30; \
  2307. _ezchip_macro_read_value_ &= 0x1;\
  2308. }
  2309. #define _ENABLE_CLOCK_clk_sdio1_ahb_ { \
  2310. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio1_ahb_ctrl_REG_ADDR); \
  2311. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2312. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2313. MA_OUTW(clk_sdio1_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2314. }
  2315. #define _DISABLE_CLOCK_clk_sdio1_ahb_ { \
  2316. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio1_ahb_ctrl_REG_ADDR); \
  2317. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2318. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2319. MA_OUTW(clk_sdio1_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2320. }
  2321. #define _GET_CLOCK_ENABLE_STATUS_clk_sdio1_ahb_(_ezchip_macro_read_value_) { \
  2322. _ezchip_macro_read_value_=MA_INW(clk_sdio1_ahb_ctrl_REG_ADDR) >> 31; \
  2323. _ezchip_macro_read_value_ &= 0x1;\
  2324. }
  2325. #define _ENABLE_CLOCK_clk_sdio1_cclkint_ { \
  2326. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_ctrl_REG_ADDR); \
  2327. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2328. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2329. MA_OUTW(clk_sdio1_cclkint_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2330. }
  2331. #define _DISABLE_CLOCK_clk_sdio1_cclkint_ { \
  2332. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_ctrl_REG_ADDR); \
  2333. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2334. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2335. MA_OUTW(clk_sdio1_cclkint_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2336. }
  2337. #define _GET_CLOCK_ENABLE_STATUS_clk_sdio1_cclkint_(_ezchip_macro_read_value_) { \
  2338. _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_ctrl_REG_ADDR) >> 31; \
  2339. _ezchip_macro_read_value_ &= 0x1;\
  2340. }
  2341. #define _DIVIDE_CLOCK_clk_sdio1_cclkint_(div) { \
  2342. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_ctrl_REG_ADDR); \
  2343. _ezchip_macro_read_value_ &= ~(0x1F); \
  2344. _ezchip_macro_read_value_ |= (div&0x1F); \
  2345. MA_OUTW(clk_sdio1_cclkint_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2346. }
  2347. #define _GET_CLOCK_DIVIDE_STATUS_clk_sdio1_cclkint_(_ezchip_macro_read_value_) { \
  2348. _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_ctrl_REG_ADDR); \
  2349. _ezchip_macro_read_value_ &= 0x1f;\
  2350. }
  2351. #define _ENABLE_CLOCK_clk_sdio1_cclkint_inv_ {}
  2352. #define _SET_CLOCK_clk_sdio1_cclkint_inv_POLARITY_ { \
  2353. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_inv_ctrl_REG_ADDR); \
  2354. _ezchip_macro_read_value_ &= ~(0x1<<30); \
  2355. _ezchip_macro_read_value_ |= (0x1&0x1)<<30; \
  2356. MA_OUTW(clk_sdio1_cclkint_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2357. }
  2358. #define _UNSET_CLOCK_clk_sdio1_cclkint_inv_POLARITY_ { \
  2359. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_inv_ctrl_REG_ADDR); \
  2360. _ezchip_macro_read_value_ &= ~(0x1<<30); \
  2361. _ezchip_macro_read_value_ |= (0x0&0x1)<<30; \
  2362. MA_OUTW(clk_sdio1_cclkint_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2363. }
  2364. #define _GET_CLOCK_POLARITY_STATUS_clk_sdio1_cclkint_inv_(_ezchip_macro_read_value_) { \
  2365. _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_inv_ctrl_REG_ADDR) >> 30; \
  2366. _ezchip_macro_read_value_ &= 0x1;\
  2367. }
  2368. #define _ENABLE_CLOCK_clk_gmac_ahb_ { \
  2369. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_ahb_ctrl_REG_ADDR); \
  2370. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2371. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2372. MA_OUTW(clk_gmac_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2373. }
  2374. #define _DISABLE_CLOCK_clk_gmac_ahb_ { \
  2375. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_ahb_ctrl_REG_ADDR); \
  2376. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2377. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2378. MA_OUTW(clk_gmac_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2379. }
  2380. #define _GET_CLOCK_ENABLE_STATUS_clk_gmac_ahb_(_ezchip_macro_read_value_) { \
  2381. _ezchip_macro_read_value_=MA_INW(clk_gmac_ahb_ctrl_REG_ADDR) >> 31; \
  2382. _ezchip_macro_read_value_ &= 0x1;\
  2383. }
  2384. #define _ENABLE_CLOCK_clk_gmac_root_div_ {}
  2385. #define _DIVIDE_CLOCK_clk_gmac_root_div_(div) { \
  2386. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_root_div_ctrl_REG_ADDR); \
  2387. _ezchip_macro_read_value_ &= ~(0xF); \
  2388. _ezchip_macro_read_value_ |= (div&0xF); \
  2389. MA_OUTW(clk_gmac_root_div_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2390. }
  2391. #define _GET_CLOCK_DIVIDE_STATUS_clk_gmac_root_div_(_ezchip_macro_read_value_) { \
  2392. _ezchip_macro_read_value_=MA_INW(clk_gmac_root_div_ctrl_REG_ADDR); \
  2393. _ezchip_macro_read_value_ &= 0xf;\
  2394. }
  2395. #define _ENABLE_CLOCK_clk_gmac_ptp_refclk_ { \
  2396. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_ptp_refclk_ctrl_REG_ADDR); \
  2397. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2398. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2399. MA_OUTW(clk_gmac_ptp_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2400. }
  2401. #define _DISABLE_CLOCK_clk_gmac_ptp_refclk_ { \
  2402. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_ptp_refclk_ctrl_REG_ADDR); \
  2403. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2404. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2405. MA_OUTW(clk_gmac_ptp_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2406. }
  2407. #define _GET_CLOCK_ENABLE_STATUS_clk_gmac_ptp_refclk_(_ezchip_macro_read_value_) { \
  2408. _ezchip_macro_read_value_=MA_INW(clk_gmac_ptp_refclk_ctrl_REG_ADDR) >> 31; \
  2409. _ezchip_macro_read_value_ &= 0x1;\
  2410. }
  2411. #define _DIVIDE_CLOCK_clk_gmac_ptp_refclk_(div) { \
  2412. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_ptp_refclk_ctrl_REG_ADDR); \
  2413. _ezchip_macro_read_value_ &= ~(0x1F); \
  2414. _ezchip_macro_read_value_ |= (div&0x1F); \
  2415. MA_OUTW(clk_gmac_ptp_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2416. }
  2417. #define _GET_CLOCK_DIVIDE_STATUS_clk_gmac_ptp_refclk_(_ezchip_macro_read_value_) { \
  2418. _ezchip_macro_read_value_=MA_INW(clk_gmac_ptp_refclk_ctrl_REG_ADDR); \
  2419. _ezchip_macro_read_value_ &= 0x1f;\
  2420. }
  2421. #define _ENABLE_CLOCK_clk_gmac_gtxclk_ { \
  2422. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_gtxclk_ctrl_REG_ADDR); \
  2423. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2424. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2425. MA_OUTW(clk_gmac_gtxclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2426. }
  2427. #define _DISABLE_CLOCK_clk_gmac_gtxclk_ { \
  2428. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_gtxclk_ctrl_REG_ADDR); \
  2429. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2430. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2431. MA_OUTW(clk_gmac_gtxclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2432. }
  2433. #define _GET_CLOCK_ENABLE_STATUS_clk_gmac_gtxclk_(_ezchip_macro_read_value_) { \
  2434. _ezchip_macro_read_value_=MA_INW(clk_gmac_gtxclk_ctrl_REG_ADDR) >> 31; \
  2435. _ezchip_macro_read_value_ &= 0x1;\
  2436. }
  2437. #define _DIVIDE_CLOCK_clk_gmac_gtxclk_(div) { \
  2438. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_gtxclk_ctrl_REG_ADDR); \
  2439. _ezchip_macro_read_value_ &= ~(0xFF); \
  2440. _ezchip_macro_read_value_ |= (div&0xFF); \
  2441. MA_OUTW(clk_gmac_gtxclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2442. }
  2443. #define _GET_CLOCK_DIVIDE_STATUS_clk_gmac_gtxclk_(_ezchip_macro_read_value_) { \
  2444. _ezchip_macro_read_value_=MA_INW(clk_gmac_gtxclk_ctrl_REG_ADDR); \
  2445. _ezchip_macro_read_value_ &= 0xff;\
  2446. }
  2447. #define _ENABLE_CLOCK_clk_gmac_rmii_txclk_ { \
  2448. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_txclk_ctrl_REG_ADDR); \
  2449. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2450. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2451. MA_OUTW(clk_gmac_rmii_txclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2452. }
  2453. #define _DISABLE_CLOCK_clk_gmac_rmii_txclk_ { \
  2454. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_txclk_ctrl_REG_ADDR); \
  2455. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2456. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2457. MA_OUTW(clk_gmac_rmii_txclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2458. }
  2459. #define _GET_CLOCK_ENABLE_STATUS_clk_gmac_rmii_txclk_(_ezchip_macro_read_value_) { \
  2460. _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_txclk_ctrl_REG_ADDR) >> 31; \
  2461. _ezchip_macro_read_value_ &= 0x1;\
  2462. }
  2463. #define _DIVIDE_CLOCK_clk_gmac_rmii_txclk_(div) { \
  2464. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_txclk_ctrl_REG_ADDR); \
  2465. _ezchip_macro_read_value_ &= ~(0xF); \
  2466. _ezchip_macro_read_value_ |= (div&0xF); \
  2467. MA_OUTW(clk_gmac_rmii_txclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2468. }
  2469. #define _GET_CLOCK_DIVIDE_STATUS_clk_gmac_rmii_txclk_(_ezchip_macro_read_value_) { \
  2470. _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_txclk_ctrl_REG_ADDR); \
  2471. _ezchip_macro_read_value_ &= 0xf;\
  2472. }
  2473. #define _ENABLE_CLOCK_clk_gmac_rmii_rxclk_ { \
  2474. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR); \
  2475. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2476. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2477. MA_OUTW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2478. }
  2479. #define _DISABLE_CLOCK_clk_gmac_rmii_rxclk_ { \
  2480. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR); \
  2481. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2482. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2483. MA_OUTW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2484. }
  2485. #define _GET_CLOCK_ENABLE_STATUS_clk_gmac_rmii_rxclk_(_ezchip_macro_read_value_) { \
  2486. _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR) >> 31; \
  2487. _ezchip_macro_read_value_ &= 0x1;\
  2488. }
  2489. #define _DIVIDE_CLOCK_clk_gmac_rmii_rxclk_(div) { \
  2490. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR); \
  2491. _ezchip_macro_read_value_ &= ~(0xF); \
  2492. _ezchip_macro_read_value_ |= (div&0xF); \
  2493. MA_OUTW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2494. }
  2495. #define _GET_CLOCK_DIVIDE_STATUS_clk_gmac_rmii_rxclk_(_ezchip_macro_read_value_) { \
  2496. _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR); \
  2497. _ezchip_macro_read_value_ &= 0xf;\
  2498. }
  2499. #define _ENABLE_CLOCK_clk_gmac_tx_ {}
  2500. #define _SWITCH_CLOCK_clk_gmac_tx_SOURCE_clk_gmac_gtxclk_ { \
  2501. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tx_ctrl_REG_ADDR); \
  2502. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  2503. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  2504. MA_OUTW(clk_gmac_tx_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2505. }
  2506. #define _SWITCH_CLOCK_clk_gmac_tx_SOURCE_clk_gmac_mii_txclk_ { \
  2507. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tx_ctrl_REG_ADDR); \
  2508. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  2509. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  2510. MA_OUTW(clk_gmac_tx_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2511. }
  2512. #define _SWITCH_CLOCK_clk_gmac_tx_SOURCE_clk_gmac_rmii_txclk_ { \
  2513. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tx_ctrl_REG_ADDR); \
  2514. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  2515. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  2516. MA_OUTW(clk_gmac_tx_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2517. }
  2518. #define _GET_CLOCK_SOURCE_STATUS_clk_gmac_tx_(_ezchip_macro_read_value_) { \
  2519. _ezchip_macro_read_value_=MA_INW(clk_gmac_tx_ctrl_REG_ADDR) >> 24; \
  2520. _ezchip_macro_read_value_ &= 0x3;\
  2521. }
  2522. #define _ENABLE_CLOCK_clk_gmac_tx_inv_ {}
  2523. #define _SET_CLOCK_clk_gmac_tx_inv_POLARITY_ { \
  2524. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tx_inv_ctrl_REG_ADDR); \
  2525. _ezchip_macro_read_value_ &= ~(0x1<<30); \
  2526. _ezchip_macro_read_value_ |= (0x1&0x1)<<30; \
  2527. MA_OUTW(clk_gmac_tx_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2528. }
  2529. #define _UNSET_CLOCK_clk_gmac_tx_inv_POLARITY_ { \
  2530. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tx_inv_ctrl_REG_ADDR); \
  2531. _ezchip_macro_read_value_ &= ~(0x1<<30); \
  2532. _ezchip_macro_read_value_ |= (0x0&0x1)<<30; \
  2533. MA_OUTW(clk_gmac_tx_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2534. }
  2535. #define _GET_CLOCK_POLARITY_STATUS_clk_gmac_tx_inv_(_ezchip_macro_read_value_) { \
  2536. _ezchip_macro_read_value_=MA_INW(clk_gmac_tx_inv_ctrl_REG_ADDR) >> 30; \
  2537. _ezchip_macro_read_value_ &= 0x1;\
  2538. }
  2539. #define _ENABLE_CLOCK_clk_gmac_rx_pre_ {}
  2540. #define _SWITCH_CLOCK_clk_gmac_rx_pre_SOURCE_clk_gmac_gr_mii_rxclk_ { \
  2541. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rx_pre_ctrl_REG_ADDR); \
  2542. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  2543. _ezchip_macro_read_value_ |= (0x0&0x1)<<24; \
  2544. MA_OUTW(clk_gmac_rx_pre_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2545. }
  2546. #define _SWITCH_CLOCK_clk_gmac_rx_pre_SOURCE_clk_gmac_rmii_rxclk_ { \
  2547. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rx_pre_ctrl_REG_ADDR); \
  2548. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  2549. _ezchip_macro_read_value_ |= (0x1&0x1)<<24; \
  2550. MA_OUTW(clk_gmac_rx_pre_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2551. }
  2552. #define _GET_CLOCK_SOURCE_STATUS_clk_gmac_rx_pre_(_ezchip_macro_read_value_) { \
  2553. _ezchip_macro_read_value_=MA_INW(clk_gmac_rx_pre_ctrl_REG_ADDR) >> 24; \
  2554. _ezchip_macro_read_value_ &= 0x1;\
  2555. }
  2556. #define _ENABLE_CLOCK_clk_gmac_rx_inv_ {}
  2557. #define _SET_CLOCK_clk_gmac_rx_inv_POLARITY_ { \
  2558. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rx_inv_ctrl_REG_ADDR); \
  2559. _ezchip_macro_read_value_ &= ~(0x1<<30); \
  2560. _ezchip_macro_read_value_ |= (0x1&0x1)<<30; \
  2561. MA_OUTW(clk_gmac_rx_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2562. }
  2563. #define _UNSET_CLOCK_clk_gmac_rx_inv_POLARITY_ { \
  2564. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rx_inv_ctrl_REG_ADDR); \
  2565. _ezchip_macro_read_value_ &= ~(0x1<<30); \
  2566. _ezchip_macro_read_value_ |= (0x0&0x1)<<30; \
  2567. MA_OUTW(clk_gmac_rx_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2568. }
  2569. #define _GET_CLOCK_POLARITY_STATUS_clk_gmac_rx_inv_(_ezchip_macro_read_value_) { \
  2570. _ezchip_macro_read_value_=MA_INW(clk_gmac_rx_inv_ctrl_REG_ADDR) >> 30; \
  2571. _ezchip_macro_read_value_ &= 0x1;\
  2572. }
  2573. #define _ENABLE_CLOCK_clk_gmac_rmii_ { \
  2574. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_ctrl_REG_ADDR); \
  2575. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2576. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2577. MA_OUTW(clk_gmac_rmii_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2578. }
  2579. #define _DISABLE_CLOCK_clk_gmac_rmii_ { \
  2580. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_ctrl_REG_ADDR); \
  2581. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2582. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2583. MA_OUTW(clk_gmac_rmii_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2584. }
  2585. #define _GET_CLOCK_ENABLE_STATUS_clk_gmac_rmii_(_ezchip_macro_read_value_) { \
  2586. _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_ctrl_REG_ADDR) >> 31; \
  2587. _ezchip_macro_read_value_ &= 0x1;\
  2588. }
  2589. #define _ENABLE_CLOCK_clk_gmac_tophyref_ { \
  2590. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tophyref_ctrl_REG_ADDR); \
  2591. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2592. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2593. MA_OUTW(clk_gmac_tophyref_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2594. }
  2595. #define _DISABLE_CLOCK_clk_gmac_tophyref_ { \
  2596. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tophyref_ctrl_REG_ADDR); \
  2597. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2598. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2599. MA_OUTW(clk_gmac_tophyref_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2600. }
  2601. #define _GET_CLOCK_ENABLE_STATUS_clk_gmac_tophyref_(_ezchip_macro_read_value_) { \
  2602. _ezchip_macro_read_value_=MA_INW(clk_gmac_tophyref_ctrl_REG_ADDR) >> 31; \
  2603. _ezchip_macro_read_value_ &= 0x1;\
  2604. }
  2605. #define _DIVIDE_CLOCK_clk_gmac_tophyref_(div) { \
  2606. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tophyref_ctrl_REG_ADDR); \
  2607. _ezchip_macro_read_value_ &= ~(0x7F); \
  2608. _ezchip_macro_read_value_ |= (div&0x7F); \
  2609. MA_OUTW(clk_gmac_tophyref_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2610. }
  2611. #define _GET_CLOCK_DIVIDE_STATUS_clk_gmac_tophyref_(_ezchip_macro_read_value_) { \
  2612. _ezchip_macro_read_value_=MA_INW(clk_gmac_tophyref_ctrl_REG_ADDR); \
  2613. _ezchip_macro_read_value_ &= 0x7f;\
  2614. }
  2615. #define _ENABLE_CLOCK_clk_spi2ahb_ahb_ { \
  2616. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_ahb_ctrl_REG_ADDR); \
  2617. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2618. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2619. MA_OUTW(clk_spi2ahb_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2620. }
  2621. #define _DISABLE_CLOCK_clk_spi2ahb_ahb_ { \
  2622. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_ahb_ctrl_REG_ADDR); \
  2623. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2624. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2625. MA_OUTW(clk_spi2ahb_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2626. }
  2627. #define _GET_CLOCK_ENABLE_STATUS_clk_spi2ahb_ahb_(_ezchip_macro_read_value_) { \
  2628. _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_ahb_ctrl_REG_ADDR) >> 31; \
  2629. _ezchip_macro_read_value_ &= 0x1;\
  2630. }
  2631. #define _ENABLE_CLOCK_clk_spi2ahb_core_ { \
  2632. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_core_ctrl_REG_ADDR); \
  2633. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2634. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2635. MA_OUTW(clk_spi2ahb_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2636. }
  2637. #define _DISABLE_CLOCK_clk_spi2ahb_core_ { \
  2638. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_core_ctrl_REG_ADDR); \
  2639. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2640. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2641. MA_OUTW(clk_spi2ahb_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2642. }
  2643. #define _GET_CLOCK_ENABLE_STATUS_clk_spi2ahb_core_(_ezchip_macro_read_value_) { \
  2644. _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_core_ctrl_REG_ADDR) >> 31; \
  2645. _ezchip_macro_read_value_ &= 0x1;\
  2646. }
  2647. #define _DIVIDE_CLOCK_clk_spi2ahb_core_(div) { \
  2648. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_core_ctrl_REG_ADDR); \
  2649. _ezchip_macro_read_value_ &= ~(0x1F); \
  2650. _ezchip_macro_read_value_ |= (div&0x1F); \
  2651. MA_OUTW(clk_spi2ahb_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2652. }
  2653. #define _GET_CLOCK_DIVIDE_STATUS_clk_spi2ahb_core_(_ezchip_macro_read_value_) { \
  2654. _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_core_ctrl_REG_ADDR); \
  2655. _ezchip_macro_read_value_ &= 0x1f;\
  2656. }
  2657. #define _ENABLE_CLOCK_clk_ezmaster_ahb_ { \
  2658. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ezmaster_ahb_ctrl_REG_ADDR); \
  2659. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2660. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2661. MA_OUTW(clk_ezmaster_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2662. }
  2663. #define _DISABLE_CLOCK_clk_ezmaster_ahb_ { \
  2664. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ezmaster_ahb_ctrl_REG_ADDR); \
  2665. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2666. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2667. MA_OUTW(clk_ezmaster_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2668. }
  2669. #define _GET_CLOCK_ENABLE_STATUS_clk_ezmaster_ahb_(_ezchip_macro_read_value_) { \
  2670. _ezchip_macro_read_value_=MA_INW(clk_ezmaster_ahb_ctrl_REG_ADDR) >> 31; \
  2671. _ezchip_macro_read_value_ &= 0x1;\
  2672. }
  2673. #define _ENABLE_CLOCK_clk_e24_ahb_ { \
  2674. uint32_t _ezchip_macro_read_value_=MA_INW(clk_e24_ahb_ctrl_REG_ADDR); \
  2675. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2676. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2677. MA_OUTW(clk_e24_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2678. }
  2679. #define _DISABLE_CLOCK_clk_e24_ahb_ { \
  2680. uint32_t _ezchip_macro_read_value_=MA_INW(clk_e24_ahb_ctrl_REG_ADDR); \
  2681. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2682. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2683. MA_OUTW(clk_e24_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2684. }
  2685. #define _GET_CLOCK_ENABLE_STATUS_clk_e24_ahb_(_ezchip_macro_read_value_) { \
  2686. _ezchip_macro_read_value_=MA_INW(clk_e24_ahb_ctrl_REG_ADDR) >> 31; \
  2687. _ezchip_macro_read_value_ &= 0x1;\
  2688. }
  2689. #define _ENABLE_CLOCK_clk_e24rtc_toggle_ { \
  2690. uint32_t _ezchip_macro_read_value_=MA_INW(clk_e24rtc_toggle_ctrl_REG_ADDR); \
  2691. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2692. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2693. MA_OUTW(clk_e24rtc_toggle_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2694. }
  2695. #define _DISABLE_CLOCK_clk_e24rtc_toggle_ { \
  2696. uint32_t _ezchip_macro_read_value_=MA_INW(clk_e24rtc_toggle_ctrl_REG_ADDR); \
  2697. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2698. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2699. MA_OUTW(clk_e24rtc_toggle_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2700. }
  2701. #define _GET_CLOCK_ENABLE_STATUS_clk_e24rtc_toggle_(_ezchip_macro_read_value_) { \
  2702. _ezchip_macro_read_value_=MA_INW(clk_e24rtc_toggle_ctrl_REG_ADDR) >> 31; \
  2703. _ezchip_macro_read_value_ &= 0x1;\
  2704. }
  2705. #define _ENABLE_CLOCK_clk_qspi_ahb_ { \
  2706. uint32_t _ezchip_macro_read_value_=MA_INW(clk_qspi_ahb_ctrl_REG_ADDR); \
  2707. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2708. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2709. MA_OUTW(clk_qspi_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2710. }
  2711. #define _DISABLE_CLOCK_clk_qspi_ahb_ { \
  2712. uint32_t _ezchip_macro_read_value_=MA_INW(clk_qspi_ahb_ctrl_REG_ADDR); \
  2713. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2714. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2715. MA_OUTW(clk_qspi_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2716. }
  2717. #define _GET_CLOCK_ENABLE_STATUS_clk_qspi_ahb_(_ezchip_macro_read_value_) { \
  2718. _ezchip_macro_read_value_=MA_INW(clk_qspi_ahb_ctrl_REG_ADDR) >> 31; \
  2719. _ezchip_macro_read_value_ &= 0x1;\
  2720. }
  2721. #define _ENABLE_CLOCK_clk_qspi_apb_ { \
  2722. uint32_t _ezchip_macro_read_value_=MA_INW(clk_qspi_apb_ctrl_REG_ADDR); \
  2723. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2724. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2725. MA_OUTW(clk_qspi_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2726. }
  2727. #define _DISABLE_CLOCK_clk_qspi_apb_ { \
  2728. uint32_t _ezchip_macro_read_value_=MA_INW(clk_qspi_apb_ctrl_REG_ADDR); \
  2729. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2730. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2731. MA_OUTW(clk_qspi_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2732. }
  2733. #define _GET_CLOCK_ENABLE_STATUS_clk_qspi_apb_(_ezchip_macro_read_value_) { \
  2734. _ezchip_macro_read_value_=MA_INW(clk_qspi_apb_ctrl_REG_ADDR) >> 31; \
  2735. _ezchip_macro_read_value_ &= 0x1;\
  2736. }
  2737. #define _ENABLE_CLOCK_clk_qspi_refclk_ { \
  2738. uint32_t _ezchip_macro_read_value_=MA_INW(clk_qspi_refclk_ctrl_REG_ADDR); \
  2739. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2740. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2741. MA_OUTW(clk_qspi_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2742. }
  2743. #define _DISABLE_CLOCK_clk_qspi_refclk_ { \
  2744. uint32_t _ezchip_macro_read_value_=MA_INW(clk_qspi_refclk_ctrl_REG_ADDR); \
  2745. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2746. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2747. MA_OUTW(clk_qspi_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2748. }
  2749. #define _GET_CLOCK_ENABLE_STATUS_clk_qspi_refclk_(_ezchip_macro_read_value_) { \
  2750. _ezchip_macro_read_value_=MA_INW(clk_qspi_refclk_ctrl_REG_ADDR) >> 31; \
  2751. _ezchip_macro_read_value_ &= 0x1;\
  2752. }
  2753. #define _DIVIDE_CLOCK_clk_qspi_refclk_(div) { \
  2754. uint32_t _ezchip_macro_read_value_=MA_INW(clk_qspi_refclk_ctrl_REG_ADDR); \
  2755. _ezchip_macro_read_value_ &= ~(0x1F); \
  2756. _ezchip_macro_read_value_ |= (div&0x1F); \
  2757. MA_OUTW(clk_qspi_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2758. }
  2759. #define _GET_CLOCK_DIVIDE_STATUS_clk_qspi_refclk_(_ezchip_macro_read_value_) { \
  2760. _ezchip_macro_read_value_=MA_INW(clk_qspi_refclk_ctrl_REG_ADDR); \
  2761. _ezchip_macro_read_value_ &= 0x1f;\
  2762. }
  2763. #define _ENABLE_CLOCK_clk_sec_ahb_ { \
  2764. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sec_ahb_ctrl_REG_ADDR); \
  2765. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2766. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2767. MA_OUTW(clk_sec_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2768. }
  2769. #define _DISABLE_CLOCK_clk_sec_ahb_ { \
  2770. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sec_ahb_ctrl_REG_ADDR); \
  2771. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2772. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2773. MA_OUTW(clk_sec_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2774. }
  2775. #define _GET_CLOCK_ENABLE_STATUS_clk_sec_ahb_(_ezchip_macro_read_value_) { \
  2776. _ezchip_macro_read_value_=MA_INW(clk_sec_ahb_ctrl_REG_ADDR) >> 31; \
  2777. _ezchip_macro_read_value_ &= 0x1;\
  2778. }
  2779. #define _ENABLE_CLOCK_clk_aes_clk_ { \
  2780. uint32_t _ezchip_macro_read_value_=MA_INW(clk_aes_clk_ctrl_REG_ADDR); \
  2781. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2782. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2783. MA_OUTW(clk_aes_clk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2784. }
  2785. #define _DISABLE_CLOCK_clk_aes_clk_ { \
  2786. uint32_t _ezchip_macro_read_value_=MA_INW(clk_aes_clk_ctrl_REG_ADDR); \
  2787. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2788. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2789. MA_OUTW(clk_aes_clk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2790. }
  2791. #define _GET_CLOCK_ENABLE_STATUS_clk_aes_clk_(_ezchip_macro_read_value_) { \
  2792. _ezchip_macro_read_value_=MA_INW(clk_aes_clk_ctrl_REG_ADDR) >> 31; \
  2793. _ezchip_macro_read_value_ &= 0x1;\
  2794. }
  2795. #define _ENABLE_CLOCK_clk_sha_clk_ { \
  2796. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sha_clk_ctrl_REG_ADDR); \
  2797. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2798. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2799. MA_OUTW(clk_sha_clk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2800. }
  2801. #define _DISABLE_CLOCK_clk_sha_clk_ { \
  2802. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sha_clk_ctrl_REG_ADDR); \
  2803. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2804. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2805. MA_OUTW(clk_sha_clk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2806. }
  2807. #define _GET_CLOCK_ENABLE_STATUS_clk_sha_clk_(_ezchip_macro_read_value_) { \
  2808. _ezchip_macro_read_value_=MA_INW(clk_sha_clk_ctrl_REG_ADDR) >> 31; \
  2809. _ezchip_macro_read_value_ &= 0x1;\
  2810. }
  2811. #define _ENABLE_CLOCK_clk_pka_clk_ { \
  2812. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pka_clk_ctrl_REG_ADDR); \
  2813. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2814. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2815. MA_OUTW(clk_pka_clk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2816. }
  2817. #define _DISABLE_CLOCK_clk_pka_clk_ { \
  2818. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pka_clk_ctrl_REG_ADDR); \
  2819. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2820. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2821. MA_OUTW(clk_pka_clk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2822. }
  2823. #define _GET_CLOCK_ENABLE_STATUS_clk_pka_clk_(_ezchip_macro_read_value_) { \
  2824. _ezchip_macro_read_value_=MA_INW(clk_pka_clk_ctrl_REG_ADDR) >> 31; \
  2825. _ezchip_macro_read_value_ &= 0x1;\
  2826. }
  2827. #define _ENABLE_CLOCK_clk_trng_apb_ { \
  2828. uint32_t _ezchip_macro_read_value_=MA_INW(clk_trng_apb_ctrl_REG_ADDR); \
  2829. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2830. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2831. MA_OUTW(clk_trng_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2832. }
  2833. #define _DISABLE_CLOCK_clk_trng_apb_ { \
  2834. uint32_t _ezchip_macro_read_value_=MA_INW(clk_trng_apb_ctrl_REG_ADDR); \
  2835. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2836. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2837. MA_OUTW(clk_trng_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2838. }
  2839. #define _GET_CLOCK_ENABLE_STATUS_clk_trng_apb_(_ezchip_macro_read_value_) { \
  2840. _ezchip_macro_read_value_=MA_INW(clk_trng_apb_ctrl_REG_ADDR) >> 31; \
  2841. _ezchip_macro_read_value_ &= 0x1;\
  2842. }
  2843. #define _ENABLE_CLOCK_clk_otp_apb_ { \
  2844. uint32_t _ezchip_macro_read_value_=MA_INW(clk_otp_apb_ctrl_REG_ADDR); \
  2845. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2846. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2847. MA_OUTW(clk_otp_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2848. }
  2849. #define _DISABLE_CLOCK_clk_otp_apb_ { \
  2850. uint32_t _ezchip_macro_read_value_=MA_INW(clk_otp_apb_ctrl_REG_ADDR); \
  2851. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2852. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2853. MA_OUTW(clk_otp_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2854. }
  2855. #define _GET_CLOCK_ENABLE_STATUS_clk_otp_apb_(_ezchip_macro_read_value_) { \
  2856. _ezchip_macro_read_value_=MA_INW(clk_otp_apb_ctrl_REG_ADDR) >> 31; \
  2857. _ezchip_macro_read_value_ &= 0x1;\
  2858. }
  2859. #define _ENABLE_CLOCK_clk_uart0_apb_ { \
  2860. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart0_apb_ctrl_REG_ADDR); \
  2861. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2862. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2863. MA_OUTW(clk_uart0_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2864. }
  2865. #define _DISABLE_CLOCK_clk_uart0_apb_ { \
  2866. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart0_apb_ctrl_REG_ADDR); \
  2867. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2868. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2869. MA_OUTW(clk_uart0_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2870. }
  2871. #define _GET_CLOCK_ENABLE_STATUS_clk_uart0_apb_(_ezchip_macro_read_value_) { \
  2872. _ezchip_macro_read_value_=MA_INW(clk_uart0_apb_ctrl_REG_ADDR) >> 31; \
  2873. _ezchip_macro_read_value_ &= 0x1;\
  2874. }
  2875. #define _ENABLE_CLOCK_clk_uart0_core_ { \
  2876. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart0_core_ctrl_REG_ADDR); \
  2877. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2878. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2879. MA_OUTW(clk_uart0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2880. }
  2881. #define _DISABLE_CLOCK_clk_uart0_core_ { \
  2882. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart0_core_ctrl_REG_ADDR); \
  2883. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2884. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2885. MA_OUTW(clk_uart0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2886. }
  2887. #define _GET_CLOCK_ENABLE_STATUS_clk_uart0_core_(_ezchip_macro_read_value_) { \
  2888. _ezchip_macro_read_value_=MA_INW(clk_uart0_core_ctrl_REG_ADDR) >> 31; \
  2889. _ezchip_macro_read_value_ &= 0x1;\
  2890. }
  2891. #define _DIVIDE_CLOCK_clk_uart0_core_(div) { \
  2892. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart0_core_ctrl_REG_ADDR); \
  2893. _ezchip_macro_read_value_ &= ~(0x3F); \
  2894. _ezchip_macro_read_value_ |= (div&0x3F); \
  2895. MA_OUTW(clk_uart0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2896. }
  2897. #define _GET_CLOCK_DIVIDE_STATUS_clk_uart0_core_(_ezchip_macro_read_value_) { \
  2898. _ezchip_macro_read_value_=MA_INW(clk_uart0_core_ctrl_REG_ADDR); \
  2899. _ezchip_macro_read_value_ &= 0x3f;\
  2900. }
  2901. #define _ENABLE_CLOCK_clk_uart1_apb_ { \
  2902. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart1_apb_ctrl_REG_ADDR); \
  2903. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2904. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2905. MA_OUTW(clk_uart1_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2906. }
  2907. #define _DISABLE_CLOCK_clk_uart1_apb_ { \
  2908. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart1_apb_ctrl_REG_ADDR); \
  2909. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2910. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2911. MA_OUTW(clk_uart1_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2912. }
  2913. #define _GET_CLOCK_ENABLE_STATUS_clk_uart1_apb_(_ezchip_macro_read_value_) { \
  2914. _ezchip_macro_read_value_=MA_INW(clk_uart1_apb_ctrl_REG_ADDR) >> 31; \
  2915. _ezchip_macro_read_value_ &= 0x1;\
  2916. }
  2917. #define _ENABLE_CLOCK_clk_uart1_core_ { \
  2918. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart1_core_ctrl_REG_ADDR); \
  2919. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2920. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2921. MA_OUTW(clk_uart1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2922. }
  2923. #define _DISABLE_CLOCK_clk_uart1_core_ { \
  2924. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart1_core_ctrl_REG_ADDR); \
  2925. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2926. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2927. MA_OUTW(clk_uart1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2928. }
  2929. #define _GET_CLOCK_ENABLE_STATUS_clk_uart1_core_(_ezchip_macro_read_value_) { \
  2930. _ezchip_macro_read_value_=MA_INW(clk_uart1_core_ctrl_REG_ADDR) >> 31; \
  2931. _ezchip_macro_read_value_ &= 0x1;\
  2932. }
  2933. #define _DIVIDE_CLOCK_clk_uart1_core_(div) { \
  2934. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart1_core_ctrl_REG_ADDR); \
  2935. _ezchip_macro_read_value_ &= ~(0x3F); \
  2936. _ezchip_macro_read_value_ |= (div&0x3F); \
  2937. MA_OUTW(clk_uart1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2938. }
  2939. #define _GET_CLOCK_DIVIDE_STATUS_clk_uart1_core_(_ezchip_macro_read_value_) { \
  2940. _ezchip_macro_read_value_=MA_INW(clk_uart1_core_ctrl_REG_ADDR); \
  2941. _ezchip_macro_read_value_ &= 0x3f;\
  2942. }
  2943. #define _ENABLE_CLOCK_clk_spi0_apb_ { \
  2944. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi0_apb_ctrl_REG_ADDR); \
  2945. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2946. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2947. MA_OUTW(clk_spi0_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2948. }
  2949. #define _DISABLE_CLOCK_clk_spi0_apb_ { \
  2950. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi0_apb_ctrl_REG_ADDR); \
  2951. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2952. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2953. MA_OUTW(clk_spi0_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2954. }
  2955. #define _GET_CLOCK_ENABLE_STATUS_clk_spi0_apb_(_ezchip_macro_read_value_) { \
  2956. _ezchip_macro_read_value_=MA_INW(clk_spi0_apb_ctrl_REG_ADDR) >> 31; \
  2957. _ezchip_macro_read_value_ &= 0x1;\
  2958. }
  2959. #define _ENABLE_CLOCK_clk_spi0_core_ { \
  2960. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi0_core_ctrl_REG_ADDR); \
  2961. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2962. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2963. MA_OUTW(clk_spi0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2964. }
  2965. #define _DISABLE_CLOCK_clk_spi0_core_ { \
  2966. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi0_core_ctrl_REG_ADDR); \
  2967. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2968. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2969. MA_OUTW(clk_spi0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2970. }
  2971. #define _GET_CLOCK_ENABLE_STATUS_clk_spi0_core_(_ezchip_macro_read_value_) { \
  2972. _ezchip_macro_read_value_=MA_INW(clk_spi0_core_ctrl_REG_ADDR) >> 31; \
  2973. _ezchip_macro_read_value_ &= 0x1;\
  2974. }
  2975. #define _DIVIDE_CLOCK_clk_spi0_core_(div) { \
  2976. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi0_core_ctrl_REG_ADDR); \
  2977. _ezchip_macro_read_value_ &= ~(0x3F); \
  2978. _ezchip_macro_read_value_ |= (div&0x3F); \
  2979. MA_OUTW(clk_spi0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2980. }
  2981. #define _GET_CLOCK_DIVIDE_STATUS_clk_spi0_core_(_ezchip_macro_read_value_) { \
  2982. _ezchip_macro_read_value_=MA_INW(clk_spi0_core_ctrl_REG_ADDR); \
  2983. _ezchip_macro_read_value_ &= 0x3f;\
  2984. }
  2985. #define _ENABLE_CLOCK_clk_spi1_apb_ { \
  2986. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi1_apb_ctrl_REG_ADDR); \
  2987. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2988. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2989. MA_OUTW(clk_spi1_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2990. }
  2991. #define _DISABLE_CLOCK_clk_spi1_apb_ { \
  2992. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi1_apb_ctrl_REG_ADDR); \
  2993. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2994. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2995. MA_OUTW(clk_spi1_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2996. }
  2997. #define _GET_CLOCK_ENABLE_STATUS_clk_spi1_apb_(_ezchip_macro_read_value_) { \
  2998. _ezchip_macro_read_value_=MA_INW(clk_spi1_apb_ctrl_REG_ADDR) >> 31; \
  2999. _ezchip_macro_read_value_ &= 0x1;\
  3000. }
  3001. #define _ENABLE_CLOCK_clk_spi1_core_ { \
  3002. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi1_core_ctrl_REG_ADDR); \
  3003. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3004. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3005. MA_OUTW(clk_spi1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3006. }
  3007. #define _DISABLE_CLOCK_clk_spi1_core_ { \
  3008. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi1_core_ctrl_REG_ADDR); \
  3009. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3010. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3011. MA_OUTW(clk_spi1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3012. }
  3013. #define _GET_CLOCK_ENABLE_STATUS_clk_spi1_core_(_ezchip_macro_read_value_) { \
  3014. _ezchip_macro_read_value_=MA_INW(clk_spi1_core_ctrl_REG_ADDR) >> 31; \
  3015. _ezchip_macro_read_value_ &= 0x1;\
  3016. }
  3017. #define _DIVIDE_CLOCK_clk_spi1_core_(div) { \
  3018. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi1_core_ctrl_REG_ADDR); \
  3019. _ezchip_macro_read_value_ &= ~(0x3F); \
  3020. _ezchip_macro_read_value_ |= (div&0x3F); \
  3021. MA_OUTW(clk_spi1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3022. }
  3023. #define _GET_CLOCK_DIVIDE_STATUS_clk_spi1_core_(_ezchip_macro_read_value_) { \
  3024. _ezchip_macro_read_value_=MA_INW(clk_spi1_core_ctrl_REG_ADDR); \
  3025. _ezchip_macro_read_value_ &= 0x3f;\
  3026. }
  3027. #define _ENABLE_CLOCK_clk_i2c0_apb_ { \
  3028. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c0_apb_ctrl_REG_ADDR); \
  3029. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3030. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3031. MA_OUTW(clk_i2c0_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3032. }
  3033. #define _DISABLE_CLOCK_clk_i2c0_apb_ { \
  3034. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c0_apb_ctrl_REG_ADDR); \
  3035. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3036. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3037. MA_OUTW(clk_i2c0_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3038. }
  3039. #define _GET_CLOCK_ENABLE_STATUS_clk_i2c0_apb_(_ezchip_macro_read_value_) { \
  3040. _ezchip_macro_read_value_=MA_INW(clk_i2c0_apb_ctrl_REG_ADDR) >> 31; \
  3041. _ezchip_macro_read_value_ &= 0x1;\
  3042. }
  3043. #define _ENABLE_CLOCK_clk_i2c0_core_ { \
  3044. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c0_core_ctrl_REG_ADDR); \
  3045. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3046. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3047. MA_OUTW(clk_i2c0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3048. }
  3049. #define _DISABLE_CLOCK_clk_i2c0_core_ { \
  3050. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c0_core_ctrl_REG_ADDR); \
  3051. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3052. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3053. MA_OUTW(clk_i2c0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3054. }
  3055. #define _GET_CLOCK_ENABLE_STATUS_clk_i2c0_core_(_ezchip_macro_read_value_) { \
  3056. _ezchip_macro_read_value_=MA_INW(clk_i2c0_core_ctrl_REG_ADDR) >> 31; \
  3057. _ezchip_macro_read_value_ &= 0x1;\
  3058. }
  3059. #define _DIVIDE_CLOCK_clk_i2c0_core_(div) { \
  3060. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c0_core_ctrl_REG_ADDR); \
  3061. _ezchip_macro_read_value_ &= ~(0x3F); \
  3062. _ezchip_macro_read_value_ |= (div&0x3F); \
  3063. MA_OUTW(clk_i2c0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3064. }
  3065. #define _GET_CLOCK_DIVIDE_STATUS_clk_i2c0_core_(_ezchip_macro_read_value_) { \
  3066. _ezchip_macro_read_value_=MA_INW(clk_i2c0_core_ctrl_REG_ADDR); \
  3067. _ezchip_macro_read_value_ &= 0x3f;\
  3068. }
  3069. #define _ENABLE_CLOCK_clk_i2c1_apb_ { \
  3070. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c1_apb_ctrl_REG_ADDR); \
  3071. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3072. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3073. MA_OUTW(clk_i2c1_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3074. }
  3075. #define _DISABLE_CLOCK_clk_i2c1_apb_ { \
  3076. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c1_apb_ctrl_REG_ADDR); \
  3077. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3078. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3079. MA_OUTW(clk_i2c1_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3080. }
  3081. #define _GET_CLOCK_ENABLE_STATUS_clk_i2c1_apb_(_ezchip_macro_read_value_) { \
  3082. _ezchip_macro_read_value_=MA_INW(clk_i2c1_apb_ctrl_REG_ADDR) >> 31; \
  3083. _ezchip_macro_read_value_ &= 0x1;\
  3084. }
  3085. #define _ENABLE_CLOCK_clk_i2c1_core_ { \
  3086. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c1_core_ctrl_REG_ADDR); \
  3087. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3088. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3089. MA_OUTW(clk_i2c1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3090. }
  3091. #define _DISABLE_CLOCK_clk_i2c1_core_ { \
  3092. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c1_core_ctrl_REG_ADDR); \
  3093. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3094. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3095. MA_OUTW(clk_i2c1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3096. }
  3097. #define _GET_CLOCK_ENABLE_STATUS_clk_i2c1_core_(_ezchip_macro_read_value_) { \
  3098. _ezchip_macro_read_value_=MA_INW(clk_i2c1_core_ctrl_REG_ADDR) >> 31; \
  3099. _ezchip_macro_read_value_ &= 0x1;\
  3100. }
  3101. #define _DIVIDE_CLOCK_clk_i2c1_core_(div) { \
  3102. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c1_core_ctrl_REG_ADDR); \
  3103. _ezchip_macro_read_value_ &= ~(0x3F); \
  3104. _ezchip_macro_read_value_ |= (div&0x3F); \
  3105. MA_OUTW(clk_i2c1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3106. }
  3107. #define _GET_CLOCK_DIVIDE_STATUS_clk_i2c1_core_(_ezchip_macro_read_value_) { \
  3108. _ezchip_macro_read_value_=MA_INW(clk_i2c1_core_ctrl_REG_ADDR); \
  3109. _ezchip_macro_read_value_ &= 0x3f;\
  3110. }
  3111. #define _ENABLE_CLOCK_clk_gpio_apb_ { \
  3112. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gpio_apb_ctrl_REG_ADDR); \
  3113. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3114. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3115. MA_OUTW(clk_gpio_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3116. }
  3117. #define _DISABLE_CLOCK_clk_gpio_apb_ { \
  3118. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gpio_apb_ctrl_REG_ADDR); \
  3119. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3120. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3121. MA_OUTW(clk_gpio_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3122. }
  3123. #define _GET_CLOCK_ENABLE_STATUS_clk_gpio_apb_(_ezchip_macro_read_value_) { \
  3124. _ezchip_macro_read_value_=MA_INW(clk_gpio_apb_ctrl_REG_ADDR) >> 31; \
  3125. _ezchip_macro_read_value_ &= 0x1;\
  3126. }
  3127. #define _ENABLE_CLOCK_clk_uart2_apb_ { \
  3128. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart2_apb_ctrl_REG_ADDR); \
  3129. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3130. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3131. MA_OUTW(clk_uart2_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3132. }
  3133. #define _DISABLE_CLOCK_clk_uart2_apb_ { \
  3134. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart2_apb_ctrl_REG_ADDR); \
  3135. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3136. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3137. MA_OUTW(clk_uart2_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3138. }
  3139. #define _GET_CLOCK_ENABLE_STATUS_clk_uart2_apb_(_ezchip_macro_read_value_) { \
  3140. _ezchip_macro_read_value_=MA_INW(clk_uart2_apb_ctrl_REG_ADDR) >> 31; \
  3141. _ezchip_macro_read_value_ &= 0x1;\
  3142. }
  3143. #define _ENABLE_CLOCK_clk_uart2_core_ { \
  3144. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart2_core_ctrl_REG_ADDR); \
  3145. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3146. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3147. MA_OUTW(clk_uart2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3148. }
  3149. #define _DISABLE_CLOCK_clk_uart2_core_ { \
  3150. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart2_core_ctrl_REG_ADDR); \
  3151. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3152. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3153. MA_OUTW(clk_uart2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3154. }
  3155. #define _GET_CLOCK_ENABLE_STATUS_clk_uart2_core_(_ezchip_macro_read_value_) { \
  3156. _ezchip_macro_read_value_=MA_INW(clk_uart2_core_ctrl_REG_ADDR) >> 31; \
  3157. _ezchip_macro_read_value_ &= 0x1;\
  3158. }
  3159. #define _DIVIDE_CLOCK_clk_uart2_core_(div) { \
  3160. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart2_core_ctrl_REG_ADDR); \
  3161. _ezchip_macro_read_value_ &= ~(0x3F); \
  3162. _ezchip_macro_read_value_ |= (div&0x3F); \
  3163. MA_OUTW(clk_uart2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3164. }
  3165. #define _GET_CLOCK_DIVIDE_STATUS_clk_uart2_core_(_ezchip_macro_read_value_) { \
  3166. _ezchip_macro_read_value_=MA_INW(clk_uart2_core_ctrl_REG_ADDR); \
  3167. _ezchip_macro_read_value_ &= 0x3f;\
  3168. }
  3169. #define _ENABLE_CLOCK_clk_uart3_apb_ { \
  3170. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart3_apb_ctrl_REG_ADDR); \
  3171. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3172. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3173. MA_OUTW(clk_uart3_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3174. }
  3175. #define _DISABLE_CLOCK_clk_uart3_apb_ { \
  3176. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart3_apb_ctrl_REG_ADDR); \
  3177. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3178. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3179. MA_OUTW(clk_uart3_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3180. }
  3181. #define _GET_CLOCK_ENABLE_STATUS_clk_uart3_apb_(_ezchip_macro_read_value_) { \
  3182. _ezchip_macro_read_value_=MA_INW(clk_uart3_apb_ctrl_REG_ADDR) >> 31; \
  3183. _ezchip_macro_read_value_ &= 0x1;\
  3184. }
  3185. #define _ENABLE_CLOCK_clk_uart3_core_ { \
  3186. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart3_core_ctrl_REG_ADDR); \
  3187. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3188. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3189. MA_OUTW(clk_uart3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3190. }
  3191. #define _DISABLE_CLOCK_clk_uart3_core_ { \
  3192. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart3_core_ctrl_REG_ADDR); \
  3193. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3194. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3195. MA_OUTW(clk_uart3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3196. }
  3197. #define _GET_CLOCK_ENABLE_STATUS_clk_uart3_core_(_ezchip_macro_read_value_) { \
  3198. _ezchip_macro_read_value_=MA_INW(clk_uart3_core_ctrl_REG_ADDR) >> 31; \
  3199. _ezchip_macro_read_value_ &= 0x1;\
  3200. }
  3201. #define _DIVIDE_CLOCK_clk_uart3_core_(div) { \
  3202. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart3_core_ctrl_REG_ADDR); \
  3203. _ezchip_macro_read_value_ &= ~(0x3F); \
  3204. _ezchip_macro_read_value_ |= (div&0x3F); \
  3205. MA_OUTW(clk_uart3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3206. }
  3207. #define _GET_CLOCK_DIVIDE_STATUS_clk_uart3_core_(_ezchip_macro_read_value_) { \
  3208. _ezchip_macro_read_value_=MA_INW(clk_uart3_core_ctrl_REG_ADDR); \
  3209. _ezchip_macro_read_value_ &= 0x3f;\
  3210. }
  3211. #define _ENABLE_CLOCK_clk_spi2_apb_ { \
  3212. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2_apb_ctrl_REG_ADDR); \
  3213. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3214. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3215. MA_OUTW(clk_spi2_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3216. }
  3217. #define _DISABLE_CLOCK_clk_spi2_apb_ { \
  3218. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2_apb_ctrl_REG_ADDR); \
  3219. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3220. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3221. MA_OUTW(clk_spi2_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3222. }
  3223. #define _GET_CLOCK_ENABLE_STATUS_clk_spi2_apb_(_ezchip_macro_read_value_) { \
  3224. _ezchip_macro_read_value_=MA_INW(clk_spi2_apb_ctrl_REG_ADDR) >> 31; \
  3225. _ezchip_macro_read_value_ &= 0x1;\
  3226. }
  3227. #define _ENABLE_CLOCK_clk_spi2_core_ { \
  3228. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2_core_ctrl_REG_ADDR); \
  3229. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3230. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3231. MA_OUTW(clk_spi2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3232. }
  3233. #define _DISABLE_CLOCK_clk_spi2_core_ { \
  3234. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2_core_ctrl_REG_ADDR); \
  3235. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3236. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3237. MA_OUTW(clk_spi2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3238. }
  3239. #define _GET_CLOCK_ENABLE_STATUS_clk_spi2_core_(_ezchip_macro_read_value_) { \
  3240. _ezchip_macro_read_value_=MA_INW(clk_spi2_core_ctrl_REG_ADDR) >> 31; \
  3241. _ezchip_macro_read_value_ &= 0x1;\
  3242. }
  3243. #define _DIVIDE_CLOCK_clk_spi2_core_(div) { \
  3244. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2_core_ctrl_REG_ADDR); \
  3245. _ezchip_macro_read_value_ &= ~(0x3F); \
  3246. _ezchip_macro_read_value_ |= (div&0x3F); \
  3247. MA_OUTW(clk_spi2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3248. }
  3249. #define _GET_CLOCK_DIVIDE_STATUS_clk_spi2_core_(_ezchip_macro_read_value_) { \
  3250. _ezchip_macro_read_value_=MA_INW(clk_spi2_core_ctrl_REG_ADDR); \
  3251. _ezchip_macro_read_value_ &= 0x3f;\
  3252. }
  3253. #define _ENABLE_CLOCK_clk_spi3_apb_ { \
  3254. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi3_apb_ctrl_REG_ADDR); \
  3255. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3256. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3257. MA_OUTW(clk_spi3_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3258. }
  3259. #define _DISABLE_CLOCK_clk_spi3_apb_ { \
  3260. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi3_apb_ctrl_REG_ADDR); \
  3261. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3262. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3263. MA_OUTW(clk_spi3_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3264. }
  3265. #define _GET_CLOCK_ENABLE_STATUS_clk_spi3_apb_(_ezchip_macro_read_value_) { \
  3266. _ezchip_macro_read_value_=MA_INW(clk_spi3_apb_ctrl_REG_ADDR) >> 31; \
  3267. _ezchip_macro_read_value_ &= 0x1;\
  3268. }
  3269. #define _ENABLE_CLOCK_clk_spi3_core_ { \
  3270. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi3_core_ctrl_REG_ADDR); \
  3271. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3272. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3273. MA_OUTW(clk_spi3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3274. }
  3275. #define _DISABLE_CLOCK_clk_spi3_core_ { \
  3276. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi3_core_ctrl_REG_ADDR); \
  3277. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3278. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3279. MA_OUTW(clk_spi3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3280. }
  3281. #define _GET_CLOCK_ENABLE_STATUS_clk_spi3_core_(_ezchip_macro_read_value_) { \
  3282. _ezchip_macro_read_value_=MA_INW(clk_spi3_core_ctrl_REG_ADDR) >> 31; \
  3283. _ezchip_macro_read_value_ &= 0x1;\
  3284. }
  3285. #define _DIVIDE_CLOCK_clk_spi3_core_(div) { \
  3286. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi3_core_ctrl_REG_ADDR); \
  3287. _ezchip_macro_read_value_ &= ~(0x3F); \
  3288. _ezchip_macro_read_value_ |= (div&0x3F); \
  3289. MA_OUTW(clk_spi3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3290. }
  3291. #define _GET_CLOCK_DIVIDE_STATUS_clk_spi3_core_(_ezchip_macro_read_value_) { \
  3292. _ezchip_macro_read_value_=MA_INW(clk_spi3_core_ctrl_REG_ADDR); \
  3293. _ezchip_macro_read_value_ &= 0x3f;\
  3294. }
  3295. #define _ENABLE_CLOCK_clk_i2c2_apb_ { \
  3296. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c2_apb_ctrl_REG_ADDR); \
  3297. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3298. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3299. MA_OUTW(clk_i2c2_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3300. }
  3301. #define _DISABLE_CLOCK_clk_i2c2_apb_ { \
  3302. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c2_apb_ctrl_REG_ADDR); \
  3303. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3304. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3305. MA_OUTW(clk_i2c2_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3306. }
  3307. #define _GET_CLOCK_ENABLE_STATUS_clk_i2c2_apb_(_ezchip_macro_read_value_) { \
  3308. _ezchip_macro_read_value_=MA_INW(clk_i2c2_apb_ctrl_REG_ADDR) >> 31; \
  3309. _ezchip_macro_read_value_ &= 0x1;\
  3310. }
  3311. #define _ENABLE_CLOCK_clk_i2c2_core_ { \
  3312. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c2_core_ctrl_REG_ADDR); \
  3313. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3314. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3315. MA_OUTW(clk_i2c2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3316. }
  3317. #define _DISABLE_CLOCK_clk_i2c2_core_ { \
  3318. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c2_core_ctrl_REG_ADDR); \
  3319. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3320. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3321. MA_OUTW(clk_i2c2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3322. }
  3323. #define _GET_CLOCK_ENABLE_STATUS_clk_i2c2_core_(_ezchip_macro_read_value_) { \
  3324. _ezchip_macro_read_value_=MA_INW(clk_i2c2_core_ctrl_REG_ADDR) >> 31; \
  3325. _ezchip_macro_read_value_ &= 0x1;\
  3326. }
  3327. #define _DIVIDE_CLOCK_clk_i2c2_core_(div) { \
  3328. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c2_core_ctrl_REG_ADDR); \
  3329. _ezchip_macro_read_value_ &= ~(0x3F); \
  3330. _ezchip_macro_read_value_ |= (div&0x3F); \
  3331. MA_OUTW(clk_i2c2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3332. }
  3333. #define _GET_CLOCK_DIVIDE_STATUS_clk_i2c2_core_(_ezchip_macro_read_value_) { \
  3334. _ezchip_macro_read_value_=MA_INW(clk_i2c2_core_ctrl_REG_ADDR); \
  3335. _ezchip_macro_read_value_ &= 0x3f;\
  3336. }
  3337. #define _ENABLE_CLOCK_clk_i2c3_apb_ { \
  3338. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c3_apb_ctrl_REG_ADDR); \
  3339. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3340. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3341. MA_OUTW(clk_i2c3_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3342. }
  3343. #define _DISABLE_CLOCK_clk_i2c3_apb_ { \
  3344. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c3_apb_ctrl_REG_ADDR); \
  3345. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3346. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3347. MA_OUTW(clk_i2c3_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3348. }
  3349. #define _GET_CLOCK_ENABLE_STATUS_clk_i2c3_apb_(_ezchip_macro_read_value_) { \
  3350. _ezchip_macro_read_value_=MA_INW(clk_i2c3_apb_ctrl_REG_ADDR) >> 31; \
  3351. _ezchip_macro_read_value_ &= 0x1;\
  3352. }
  3353. #define _ENABLE_CLOCK_clk_i2c3_core_ { \
  3354. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c3_core_ctrl_REG_ADDR); \
  3355. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3356. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3357. MA_OUTW(clk_i2c3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3358. }
  3359. #define _DISABLE_CLOCK_clk_i2c3_core_ { \
  3360. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c3_core_ctrl_REG_ADDR); \
  3361. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3362. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3363. MA_OUTW(clk_i2c3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3364. }
  3365. #define _GET_CLOCK_ENABLE_STATUS_clk_i2c3_core_(_ezchip_macro_read_value_) { \
  3366. _ezchip_macro_read_value_=MA_INW(clk_i2c3_core_ctrl_REG_ADDR) >> 31; \
  3367. _ezchip_macro_read_value_ &= 0x1;\
  3368. }
  3369. #define _DIVIDE_CLOCK_clk_i2c3_core_(div) { \
  3370. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c3_core_ctrl_REG_ADDR); \
  3371. _ezchip_macro_read_value_ &= ~(0x3F); \
  3372. _ezchip_macro_read_value_ |= (div&0x3F); \
  3373. MA_OUTW(clk_i2c3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3374. }
  3375. #define _GET_CLOCK_DIVIDE_STATUS_clk_i2c3_core_(_ezchip_macro_read_value_) { \
  3376. _ezchip_macro_read_value_=MA_INW(clk_i2c3_core_ctrl_REG_ADDR); \
  3377. _ezchip_macro_read_value_ &= 0x3f;\
  3378. }
  3379. #define _ENABLE_CLOCK_clk_wdtimer_apb_ { \
  3380. uint32_t _ezchip_macro_read_value_=MA_INW(clk_wdtimer_apb_ctrl_REG_ADDR); \
  3381. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3382. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3383. MA_OUTW(clk_wdtimer_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3384. }
  3385. #define _DISABLE_CLOCK_clk_wdtimer_apb_ { \
  3386. uint32_t _ezchip_macro_read_value_=MA_INW(clk_wdtimer_apb_ctrl_REG_ADDR); \
  3387. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3388. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3389. MA_OUTW(clk_wdtimer_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3390. }
  3391. #define _GET_CLOCK_ENABLE_STATUS_clk_wdtimer_apb_(_ezchip_macro_read_value_) { \
  3392. _ezchip_macro_read_value_=MA_INW(clk_wdtimer_apb_ctrl_REG_ADDR) >> 31; \
  3393. _ezchip_macro_read_value_ &= 0x1;\
  3394. }
  3395. #define _ENABLE_CLOCK_clk_wdt_coreclk_ { \
  3396. uint32_t _ezchip_macro_read_value_=MA_INW(clk_wdt_coreclk_ctrl_REG_ADDR); \
  3397. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3398. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3399. MA_OUTW(clk_wdt_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3400. }
  3401. #define _DISABLE_CLOCK_clk_wdt_coreclk_ { \
  3402. uint32_t _ezchip_macro_read_value_=MA_INW(clk_wdt_coreclk_ctrl_REG_ADDR); \
  3403. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3404. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3405. MA_OUTW(clk_wdt_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3406. }
  3407. #define _GET_CLOCK_ENABLE_STATUS_clk_wdt_coreclk_(_ezchip_macro_read_value_) { \
  3408. _ezchip_macro_read_value_=MA_INW(clk_wdt_coreclk_ctrl_REG_ADDR) >> 31; \
  3409. _ezchip_macro_read_value_ &= 0x1;\
  3410. }
  3411. #define _DIVIDE_CLOCK_clk_wdt_coreclk_(div) { \
  3412. uint32_t _ezchip_macro_read_value_=MA_INW(clk_wdt_coreclk_ctrl_REG_ADDR); \
  3413. _ezchip_macro_read_value_ &= ~(0x3F); \
  3414. _ezchip_macro_read_value_ |= (div&0x3F); \
  3415. MA_OUTW(clk_wdt_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3416. }
  3417. #define _GET_CLOCK_DIVIDE_STATUS_clk_wdt_coreclk_(_ezchip_macro_read_value_) { \
  3418. _ezchip_macro_read_value_=MA_INW(clk_wdt_coreclk_ctrl_REG_ADDR); \
  3419. _ezchip_macro_read_value_ &= 0x3f;\
  3420. }
  3421. #define _ENABLE_CLOCK_clk_timer0_coreclk_ { \
  3422. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer0_coreclk_ctrl_REG_ADDR); \
  3423. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3424. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3425. MA_OUTW(clk_timer0_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3426. }
  3427. #define _DISABLE_CLOCK_clk_timer0_coreclk_ { \
  3428. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer0_coreclk_ctrl_REG_ADDR); \
  3429. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3430. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3431. MA_OUTW(clk_timer0_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3432. }
  3433. #define _GET_CLOCK_ENABLE_STATUS_clk_timer0_coreclk_(_ezchip_macro_read_value_) { \
  3434. _ezchip_macro_read_value_=MA_INW(clk_timer0_coreclk_ctrl_REG_ADDR) >> 31; \
  3435. _ezchip_macro_read_value_ &= 0x1;\
  3436. }
  3437. #define _DIVIDE_CLOCK_clk_timer0_coreclk_(div) { \
  3438. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer0_coreclk_ctrl_REG_ADDR); \
  3439. _ezchip_macro_read_value_ &= ~(0x3F); \
  3440. _ezchip_macro_read_value_ |= (div&0x3F); \
  3441. MA_OUTW(clk_timer0_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3442. }
  3443. #define _GET_CLOCK_DIVIDE_STATUS_clk_timer0_coreclk_(_ezchip_macro_read_value_) { \
  3444. _ezchip_macro_read_value_=MA_INW(clk_timer0_coreclk_ctrl_REG_ADDR); \
  3445. _ezchip_macro_read_value_ &= 0x3f;\
  3446. }
  3447. #define _ENABLE_CLOCK_clk_timer1_coreclk_ { \
  3448. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer1_coreclk_ctrl_REG_ADDR); \
  3449. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3450. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3451. MA_OUTW(clk_timer1_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3452. }
  3453. #define _DISABLE_CLOCK_clk_timer1_coreclk_ { \
  3454. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer1_coreclk_ctrl_REG_ADDR); \
  3455. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3456. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3457. MA_OUTW(clk_timer1_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3458. }
  3459. #define _GET_CLOCK_ENABLE_STATUS_clk_timer1_coreclk_(_ezchip_macro_read_value_) { \
  3460. _ezchip_macro_read_value_=MA_INW(clk_timer1_coreclk_ctrl_REG_ADDR) >> 31; \
  3461. _ezchip_macro_read_value_ &= 0x1;\
  3462. }
  3463. #define _DIVIDE_CLOCK_clk_timer1_coreclk_(div) { \
  3464. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer1_coreclk_ctrl_REG_ADDR); \
  3465. _ezchip_macro_read_value_ &= ~(0x3F); \
  3466. _ezchip_macro_read_value_ |= (div&0x3F); \
  3467. MA_OUTW(clk_timer1_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3468. }
  3469. #define _GET_CLOCK_DIVIDE_STATUS_clk_timer1_coreclk_(_ezchip_macro_read_value_) { \
  3470. _ezchip_macro_read_value_=MA_INW(clk_timer1_coreclk_ctrl_REG_ADDR); \
  3471. _ezchip_macro_read_value_ &= 0x3f;\
  3472. }
  3473. #define _ENABLE_CLOCK_clk_timer2_coreclk_ { \
  3474. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer2_coreclk_ctrl_REG_ADDR); \
  3475. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3476. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3477. MA_OUTW(clk_timer2_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3478. }
  3479. #define _DISABLE_CLOCK_clk_timer2_coreclk_ { \
  3480. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer2_coreclk_ctrl_REG_ADDR); \
  3481. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3482. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3483. MA_OUTW(clk_timer2_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3484. }
  3485. #define _GET_CLOCK_ENABLE_STATUS_clk_timer2_coreclk_(_ezchip_macro_read_value_) { \
  3486. _ezchip_macro_read_value_=MA_INW(clk_timer2_coreclk_ctrl_REG_ADDR) >> 31; \
  3487. _ezchip_macro_read_value_ &= 0x1;\
  3488. }
  3489. #define _DIVIDE_CLOCK_clk_timer2_coreclk_(div) { \
  3490. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer2_coreclk_ctrl_REG_ADDR); \
  3491. _ezchip_macro_read_value_ &= ~(0x3F); \
  3492. _ezchip_macro_read_value_ |= (div&0x3F); \
  3493. MA_OUTW(clk_timer2_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3494. }
  3495. #define _GET_CLOCK_DIVIDE_STATUS_clk_timer2_coreclk_(_ezchip_macro_read_value_) { \
  3496. _ezchip_macro_read_value_=MA_INW(clk_timer2_coreclk_ctrl_REG_ADDR); \
  3497. _ezchip_macro_read_value_ &= 0x3f;\
  3498. }
  3499. #define _ENABLE_CLOCK_clk_timer3_coreclk_ { \
  3500. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer3_coreclk_ctrl_REG_ADDR); \
  3501. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3502. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3503. MA_OUTW(clk_timer3_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3504. }
  3505. #define _DISABLE_CLOCK_clk_timer3_coreclk_ { \
  3506. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer3_coreclk_ctrl_REG_ADDR); \
  3507. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3508. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3509. MA_OUTW(clk_timer3_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3510. }
  3511. #define _GET_CLOCK_ENABLE_STATUS_clk_timer3_coreclk_(_ezchip_macro_read_value_) { \
  3512. _ezchip_macro_read_value_=MA_INW(clk_timer3_coreclk_ctrl_REG_ADDR) >> 31; \
  3513. _ezchip_macro_read_value_ &= 0x1;\
  3514. }
  3515. #define _DIVIDE_CLOCK_clk_timer3_coreclk_(div) { \
  3516. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer3_coreclk_ctrl_REG_ADDR); \
  3517. _ezchip_macro_read_value_ &= ~(0x3F); \
  3518. _ezchip_macro_read_value_ |= (div&0x3F); \
  3519. MA_OUTW(clk_timer3_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3520. }
  3521. #define _GET_CLOCK_DIVIDE_STATUS_clk_timer3_coreclk_(_ezchip_macro_read_value_) { \
  3522. _ezchip_macro_read_value_=MA_INW(clk_timer3_coreclk_ctrl_REG_ADDR); \
  3523. _ezchip_macro_read_value_ &= 0x3f;\
  3524. }
  3525. #define _ENABLE_CLOCK_clk_timer4_coreclk_ { \
  3526. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer4_coreclk_ctrl_REG_ADDR); \
  3527. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3528. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3529. MA_OUTW(clk_timer4_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3530. }
  3531. #define _DISABLE_CLOCK_clk_timer4_coreclk_ { \
  3532. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer4_coreclk_ctrl_REG_ADDR); \
  3533. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3534. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3535. MA_OUTW(clk_timer4_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3536. }
  3537. #define _GET_CLOCK_ENABLE_STATUS_clk_timer4_coreclk_(_ezchip_macro_read_value_) { \
  3538. _ezchip_macro_read_value_=MA_INW(clk_timer4_coreclk_ctrl_REG_ADDR) >> 31; \
  3539. _ezchip_macro_read_value_ &= 0x1;\
  3540. }
  3541. #define _DIVIDE_CLOCK_clk_timer4_coreclk_(div) { \
  3542. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer4_coreclk_ctrl_REG_ADDR); \
  3543. _ezchip_macro_read_value_ &= ~(0x3F); \
  3544. _ezchip_macro_read_value_ |= (div&0x3F); \
  3545. MA_OUTW(clk_timer4_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3546. }
  3547. #define _GET_CLOCK_DIVIDE_STATUS_clk_timer4_coreclk_(_ezchip_macro_read_value_) { \
  3548. _ezchip_macro_read_value_=MA_INW(clk_timer4_coreclk_ctrl_REG_ADDR); \
  3549. _ezchip_macro_read_value_ &= 0x3f;\
  3550. }
  3551. #define _ENABLE_CLOCK_clk_timer5_coreclk_ { \
  3552. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer5_coreclk_ctrl_REG_ADDR); \
  3553. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3554. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3555. MA_OUTW(clk_timer5_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3556. }
  3557. #define _DISABLE_CLOCK_clk_timer5_coreclk_ { \
  3558. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer5_coreclk_ctrl_REG_ADDR); \
  3559. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3560. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3561. MA_OUTW(clk_timer5_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3562. }
  3563. #define _GET_CLOCK_ENABLE_STATUS_clk_timer5_coreclk_(_ezchip_macro_read_value_) { \
  3564. _ezchip_macro_read_value_=MA_INW(clk_timer5_coreclk_ctrl_REG_ADDR) >> 31; \
  3565. _ezchip_macro_read_value_ &= 0x1;\
  3566. }
  3567. #define _DIVIDE_CLOCK_clk_timer5_coreclk_(div) { \
  3568. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer5_coreclk_ctrl_REG_ADDR); \
  3569. _ezchip_macro_read_value_ &= ~(0x3F); \
  3570. _ezchip_macro_read_value_ |= (div&0x3F); \
  3571. MA_OUTW(clk_timer5_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3572. }
  3573. #define _GET_CLOCK_DIVIDE_STATUS_clk_timer5_coreclk_(_ezchip_macro_read_value_) { \
  3574. _ezchip_macro_read_value_=MA_INW(clk_timer5_coreclk_ctrl_REG_ADDR); \
  3575. _ezchip_macro_read_value_ &= 0x3f;\
  3576. }
  3577. #define _ENABLE_CLOCK_clk_timer6_coreclk_ { \
  3578. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer6_coreclk_ctrl_REG_ADDR); \
  3579. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3580. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3581. MA_OUTW(clk_timer6_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3582. }
  3583. #define _DISABLE_CLOCK_clk_timer6_coreclk_ { \
  3584. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer6_coreclk_ctrl_REG_ADDR); \
  3585. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3586. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3587. MA_OUTW(clk_timer6_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3588. }
  3589. #define _GET_CLOCK_ENABLE_STATUS_clk_timer6_coreclk_(_ezchip_macro_read_value_) { \
  3590. _ezchip_macro_read_value_=MA_INW(clk_timer6_coreclk_ctrl_REG_ADDR) >> 31; \
  3591. _ezchip_macro_read_value_ &= 0x1;\
  3592. }
  3593. #define _DIVIDE_CLOCK_clk_timer6_coreclk_(div) { \
  3594. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer6_coreclk_ctrl_REG_ADDR); \
  3595. _ezchip_macro_read_value_ &= ~(0x3F); \
  3596. _ezchip_macro_read_value_ |= (div&0x3F); \
  3597. MA_OUTW(clk_timer6_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3598. }
  3599. #define _GET_CLOCK_DIVIDE_STATUS_clk_timer6_coreclk_(_ezchip_macro_read_value_) { \
  3600. _ezchip_macro_read_value_=MA_INW(clk_timer6_coreclk_ctrl_REG_ADDR); \
  3601. _ezchip_macro_read_value_ &= 0x3f;\
  3602. }
  3603. #define _ENABLE_CLOCK_clk_vp6intc_apb_ { \
  3604. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6intc_apb_ctrl_REG_ADDR); \
  3605. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3606. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3607. MA_OUTW(clk_vp6intc_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3608. }
  3609. #define _DISABLE_CLOCK_clk_vp6intc_apb_ { \
  3610. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6intc_apb_ctrl_REG_ADDR); \
  3611. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3612. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3613. MA_OUTW(clk_vp6intc_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3614. }
  3615. #define _GET_CLOCK_ENABLE_STATUS_clk_vp6intc_apb_(_ezchip_macro_read_value_) { \
  3616. _ezchip_macro_read_value_=MA_INW(clk_vp6intc_apb_ctrl_REG_ADDR) >> 31; \
  3617. _ezchip_macro_read_value_ &= 0x1;\
  3618. }
  3619. #define _ENABLE_CLOCK_clk_pwm_apb_ { \
  3620. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pwm_apb_ctrl_REG_ADDR); \
  3621. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3622. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3623. MA_OUTW(clk_pwm_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3624. }
  3625. #define _DISABLE_CLOCK_clk_pwm_apb_ { \
  3626. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pwm_apb_ctrl_REG_ADDR); \
  3627. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3628. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3629. MA_OUTW(clk_pwm_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3630. }
  3631. #define _GET_CLOCK_ENABLE_STATUS_clk_pwm_apb_(_ezchip_macro_read_value_) { \
  3632. _ezchip_macro_read_value_=MA_INW(clk_pwm_apb_ctrl_REG_ADDR) >> 31; \
  3633. _ezchip_macro_read_value_ &= 0x1;\
  3634. }
  3635. #define _ENABLE_CLOCK_clk_msi_apb_ { \
  3636. uint32_t _ezchip_macro_read_value_=MA_INW(clk_msi_apb_ctrl_REG_ADDR); \
  3637. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3638. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3639. MA_OUTW(clk_msi_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3640. }
  3641. #define _DISABLE_CLOCK_clk_msi_apb_ { \
  3642. uint32_t _ezchip_macro_read_value_=MA_INW(clk_msi_apb_ctrl_REG_ADDR); \
  3643. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3644. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3645. MA_OUTW(clk_msi_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3646. }
  3647. #define _GET_CLOCK_ENABLE_STATUS_clk_msi_apb_(_ezchip_macro_read_value_) { \
  3648. _ezchip_macro_read_value_=MA_INW(clk_msi_apb_ctrl_REG_ADDR) >> 31; \
  3649. _ezchip_macro_read_value_ &= 0x1;\
  3650. }
  3651. #define _ENABLE_CLOCK_clk_temp_apb_ { \
  3652. uint32_t _ezchip_macro_read_value_=MA_INW(clk_temp_apb_ctrl_REG_ADDR); \
  3653. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3654. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3655. MA_OUTW(clk_temp_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3656. }
  3657. #define _DISABLE_CLOCK_clk_temp_apb_ { \
  3658. uint32_t _ezchip_macro_read_value_=MA_INW(clk_temp_apb_ctrl_REG_ADDR); \
  3659. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3660. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3661. MA_OUTW(clk_temp_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3662. }
  3663. #define _GET_CLOCK_ENABLE_STATUS_clk_temp_apb_(_ezchip_macro_read_value_) { \
  3664. _ezchip_macro_read_value_=MA_INW(clk_temp_apb_ctrl_REG_ADDR) >> 31; \
  3665. _ezchip_macro_read_value_ &= 0x1;\
  3666. }
  3667. #define _ENABLE_CLOCK_clk_temp_sense_ { \
  3668. uint32_t _ezchip_macro_read_value_=MA_INW(clk_temp_sense_ctrl_REG_ADDR); \
  3669. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3670. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3671. MA_OUTW(clk_temp_sense_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3672. }
  3673. #define _DISABLE_CLOCK_clk_temp_sense_ { \
  3674. uint32_t _ezchip_macro_read_value_=MA_INW(clk_temp_sense_ctrl_REG_ADDR); \
  3675. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3676. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3677. MA_OUTW(clk_temp_sense_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3678. }
  3679. #define _GET_CLOCK_ENABLE_STATUS_clk_temp_sense_(_ezchip_macro_read_value_) { \
  3680. _ezchip_macro_read_value_=MA_INW(clk_temp_sense_ctrl_REG_ADDR) >> 31; \
  3681. _ezchip_macro_read_value_ &= 0x1;\
  3682. }
  3683. #define _DIVIDE_CLOCK_clk_temp_sense_(div) { \
  3684. uint32_t _ezchip_macro_read_value_=MA_INW(clk_temp_sense_ctrl_REG_ADDR); \
  3685. _ezchip_macro_read_value_ &= ~(0x1F); \
  3686. _ezchip_macro_read_value_ |= (div&0x1F); \
  3687. MA_OUTW(clk_temp_sense_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3688. }
  3689. #define _GET_CLOCK_DIVIDE_STATUS_clk_temp_sense_(_ezchip_macro_read_value_) { \
  3690. _ezchip_macro_read_value_=MA_INW(clk_temp_sense_ctrl_REG_ADDR); \
  3691. _ezchip_macro_read_value_ &= 0x1f;\
  3692. }
  3693. #define _ENABLE_CLOCK_clk_syserr_apb_ { \
  3694. uint32_t _ezchip_macro_read_value_=MA_INW(clk_syserr_apb_ctrl_REG_ADDR); \
  3695. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3696. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3697. MA_OUTW(clk_syserr_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3698. }
  3699. #define _DISABLE_CLOCK_clk_syserr_apb_ { \
  3700. uint32_t _ezchip_macro_read_value_=MA_INW(clk_syserr_apb_ctrl_REG_ADDR); \
  3701. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3702. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3703. MA_OUTW(clk_syserr_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3704. }
  3705. #define _GET_CLOCK_ENABLE_STATUS_clk_syserr_apb_(_ezchip_macro_read_value_) { \
  3706. _ezchip_macro_read_value_=MA_INW(clk_syserr_apb_ctrl_REG_ADDR) >> 31; \
  3707. _ezchip_macro_read_value_ &= 0x1;\
  3708. }
  3709. #endif //_CLKGEN_MACRO_H_