spi_flash.c 12 KB

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  1. /**
  2. ******************************************************************************
  3. * @file spi_flash.c
  4. * @author StarFive Technology
  5. * @version V1.0
  6. * @date 06/25/2020
  7. * @brief
  8. ******************************************************************************
  9. * @copy
  10. *
  11. * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  12. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  13. * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
  14. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  15. * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  16. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  17. *
  18. * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
  19. */
  20. #include <comdef.h>
  21. #include "spi.h"
  22. #include "spi_flash.h"
  23. #include "spi_flash_internal.h"
  24. #include <cadence_qspi.h>
  25. static void spi_flash_addr(u32 addr, u8 *cmd)
  26. {
  27. /* cmd[0] is actual command */
  28. cmd[1] = (addr & 0x00FF0000) >> 16;
  29. cmd[2] = (addr & 0x0000FF00) >> 8;
  30. cmd[3] = (addr & 0x000000FF) >> 0;
  31. }
  32. static int spi_flash_read_write(struct spi_slave *spi,
  33. u8 *cmd, u32 cmd_len,
  34. u8 *data_out, u8 *data_in,
  35. u32 data_len)
  36. {
  37. unsigned long flags = SPI_XFER_BEGIN;
  38. int ret;
  39. if (data_len == 0)
  40. flags |= SPI_XFER_END;
  41. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  42. if (ret)
  43. {
  44. //uart_printf("SF: Failed to send command (%d bytes): %d\n",
  45. //cmd_len, ret);
  46. }
  47. else if (data_len != 0)
  48. {
  49. ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END, SPI_DATAMODE_8);
  50. }
  51. return ret;
  52. }
  53. int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, u32 len)
  54. {
  55. return spi_flash_cmd_read(spi, &cmd, 1, response, len);
  56. }
  57. int spi_flash_cmd_read(struct spi_slave *spi, u8 *cmd,
  58. u32 cmd_len, void *data, u32 data_len)
  59. {
  60. return spi_flash_read_write(spi, cmd, cmd_len, NULL, data, data_len);
  61. }
  62. int spi_flash_cmd_write(struct spi_slave *spi, u8 *cmd, u32 cmd_len,
  63. void *data, u32 data_len)
  64. {
  65. return spi_flash_read_write(spi, cmd, cmd_len, data, NULL, data_len);
  66. }
  67. int spi_flash_cmd_write_enable(struct spi_flash *flash)
  68. {
  69. return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, (void*)NULL, 0);
  70. }
  71. int spi_flash_cmd_write_status_enable(struct spi_flash *flash)
  72. {
  73. return spi_flash_cmd(flash->spi, CMD_STATUS_ENABLE, (void*)NULL, 0);
  74. }
  75. int spi_flash_cmd_write_disable(struct spi_slave *spi)
  76. {
  77. return spi_flash_cmd(spi, CMD_WRITE_DISABLE, (void*)NULL, 0);
  78. }
  79. int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *cmd, u32 cmd_len, u8 *status)
  80. {
  81. struct spi_slave *spi = flash->spi;
  82. int ret;
  83. ret = spi_xfer(spi, 8*cmd_len, cmd, NULL, SPI_XFER_BEGIN, SPI_DATAMODE_8);
  84. if (ret) {
  85. //uart_printf("SF: Failed to send command %x: %d\n", (unsigned int)cmd, ret);
  86. return ret;
  87. }
  88. ret = spi_xfer(spi, 8*1, NULL, status, SPI_XFER_END, SPI_DATAMODE_8);
  89. //uart_printf("status = 0x%x\r\n", status[0]);
  90. if (ret)
  91. return ret;
  92. return 0;
  93. }
  94. int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout,
  95. u8 cmd, u8 poll_bit)
  96. {
  97. int ret;
  98. u8 status;
  99. u32 status_tmp = 0;
  100. u32 timebase_1 = 0;
  101. do {
  102. ret = spi_flash_cmd_read_status(flash, &cmd, 1, &status);
  103. //uart_printf("cmd = 0x%x, status = 0x%x\r\n", cmd, status);
  104. if (ret)
  105. return ret;
  106. if ((status & poll_bit) == 0)
  107. break;
  108. timebase_1++;//libo
  109. } while (timebase_1 < timeout);
  110. if ((status & poll_bit) == 0)
  111. return 0;
  112. /* Timed out */
  113. //uart_printf("SF: time out!\r\n");
  114. return -1;
  115. }
  116. int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
  117. {
  118. return spi_flash_cmd_poll_bit(flash, timeout,
  119. CMD_READ_STATUS, STATUS_WIP);
  120. }
  121. int spi_flash_cmd_poll_enable(struct spi_flash *flash, unsigned long timeout,
  122. u8 cmd, u32 poll_bit)
  123. {
  124. int ret;
  125. u8 status;
  126. u32 status_tmp = 0;
  127. u32 timebase_1 = 0;
  128. do {
  129. ret = spi_flash_cmd_read_status(flash, &cmd, 1, &status);
  130. if (ret)
  131. return ret;
  132. //uart_printf("read status = 0x%x\r\n", status);
  133. if ((status & poll_bit) == 1)
  134. break;
  135. timebase_1++;
  136. } while (timebase_1 < timeout);
  137. /* Timed out */
  138. //uart_printf("SF: time out!\r\n");
  139. return 0;
  140. }
  141. int spi_flash_cmd_status_poll_enable(struct spi_flash *flash, unsigned long timeout,
  142. u8 cmd, u32 poll_bit)
  143. {
  144. int ret;
  145. u8 status;
  146. u32 status_tmp = 0;
  147. u32 timebase_1 = 0;
  148. do {
  149. ret = spi_flash_cmd_read_status(flash, &cmd, 1, &status);
  150. if (ret)
  151. return ret;
  152. //uart_printf("read status = 0x%x\r\n", status);
  153. if ((status & poll_bit) == 0x2)
  154. break;
  155. timebase_1++;
  156. } while (timebase_1 < timeout);
  157. /* Timed out */
  158. //uart_printf("SF: time out!\r\n");
  159. return 0;
  160. }
  161. int spi_flash_cmd_wait_enable(struct spi_flash *flash, unsigned long timeout)
  162. {
  163. return spi_flash_cmd_status_poll_enable(flash, timeout,
  164. CMD_READ_STATUS, FLASH_ENABLE);
  165. }
  166. int spi_flash_write_status(struct spi_flash *flash, u8 *cmd, unsigned int cmd_len,void *data, unsigned int data_len)
  167. {
  168. int ret;
  169. ret = spi_flash_cmd_write_enable(flash);
  170. if (ret) {
  171. // uart_printf("SF: Unable to claim SPI bus\n");
  172. return ret;
  173. }
  174. ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, data, data_len);
  175. if (ret < 0) {
  176. //uart_printf("SF: write failed\n");
  177. return ret;
  178. }
  179. ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
  180. if (ret < 0) {
  181. //uart_printf("SF: wait ready failed\n");
  182. return ret;
  183. }
  184. ret = spi_flash_cmd_write_disable(flash->spi);
  185. if (ret < 0) {
  186. //uart_printf("SF: disable write failed\n");
  187. return ret;
  188. }
  189. return 0;
  190. }
  191. #ifdef ISP_BOARD
  192. int spi_flash_write_status_bit(struct spi_flash *flash, u8 status0, u8 bit0)
  193. {
  194. u8 status[2];
  195. int ret = 0;
  196. status[0] = CMD_WRITE_STATUS;
  197. status[1] = status0|bit0;
  198. spi_flash_write_status(flash, &status[0], 1, &status[1], 1);
  199. if (bit0)
  200. {
  201. ret &= spi_flash_cmd_poll_bit(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT, CMD_READ_STATUS, ~bit0);
  202. }
  203. return ret;
  204. delay(1000);
  205. return ret;
  206. }
  207. int spi_flash_protect(struct spi_flash *flash)
  208. {
  209. /* set PB=0 all can write */
  210. return spi_flash_write_status_bit(flash, 0x00, 0);
  211. }
  212. #else
  213. int spi_flash_write_status_bit(struct spi_flash *flash, u8 status1, u8 status2, u8 bit1, u8 bit2)
  214. {
  215. u8 status[3];
  216. int ret = 0;
  217. status[0] = CMD_WRITE_STATUS;
  218. status[1] = status1|bit1;
  219. status[2] = status2|bit2;
  220. spi_flash_write_status(flash, &status[0], 1, &status[1], 2);
  221. if (bit1)
  222. {
  223. ret &= spi_flash_cmd_poll_bit(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT, CMD_READ_STATUS, ~bit1);
  224. }
  225. if (bit2)
  226. {
  227. ret &= spi_flash_cmd_poll_bit(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT, CMD_READ_STATUS1, ~bit2);
  228. }
  229. return ret;
  230. delay(1000);
  231. return ret;
  232. }
  233. int spi_flash_protect(struct spi_flash *flash)
  234. {
  235. /* set PB=0 all can write */
  236. return spi_flash_write_status_bit(flash, 0x00, 0x00, 0, 0);
  237. }
  238. #endif
  239. int spi_flash_cmd_erase(struct spi_flash *flash, u8 erase_cmd,
  240. u32 offset, u32 len)
  241. {
  242. u32 start, end, erase_size;
  243. int ret;
  244. u8 cmd[4];
  245. //uart_printf("spi_flash_cmd_erase \r\n");
  246. switch(erase_cmd){
  247. case CMD_W25_SE:
  248. erase_size = flash->sector_size;
  249. break;
  250. case CMD_W25_BE_32:
  251. erase_size = flash->sector_size * 8;
  252. break;
  253. case CMD_W25_BE:
  254. erase_size = flash->block_size;
  255. break;
  256. default:
  257. erase_size = flash->sector_size;
  258. break;
  259. }
  260. if (offset % erase_size || len % erase_size) {
  261. //uart_printf("SF: Erase offset/length not multiple of erase size\n");
  262. return -1;
  263. }
  264. // spi_flash_cmd_write_status_enable(flash);
  265. spi_flash_protect(flash);
  266. cmd[0] = erase_cmd;
  267. start = offset;
  268. end = start + len;
  269. while (offset < end)
  270. {
  271. spi_flash_addr(offset, cmd);
  272. offset += erase_size;
  273. //uart_printf("SF: erase %x %x %x %x (%x)\n", cmd[0], cmd[1],
  274. // cmd[2], cmd[3], offset);
  275. ret = spi_flash_cmd_write_enable(flash);
  276. if (ret)
  277. goto out;
  278. //spi_flash_cmd_wait_enable(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
  279. ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), NULL, 0);
  280. if (ret)
  281. goto out;
  282. ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
  283. if (ret)
  284. goto out;
  285. ret = spi_flash_cmd_write_disable(flash->spi);
  286. if (ret)
  287. goto out;
  288. }
  289. //uart_printf("SF: Successfully erased %d bytes @ %x\n", len , start);
  290. out:
  291. return ret;
  292. }
  293. /* mode is 4, 32, 64*/
  294. int spi_flash_erase_mode(struct spi_flash *flash, u32 offset, u32 len, u32 mode)
  295. {
  296. int ret = 0;
  297. switch (mode)
  298. {
  299. case 4:
  300. ret = spi_flash_cmd_erase(flash, CMD_W25_SE, offset, len);
  301. break;
  302. case 32:
  303. ret = spi_flash_cmd_erase(flash, CMD_W25_BE_32, offset, len);
  304. break;
  305. case 64:
  306. ret = spi_flash_cmd_erase(flash, CMD_W25_BE, offset, len);
  307. break;
  308. default:
  309. ret = spi_flash_cmd_erase(flash, CMD_W25_BE, offset, len);
  310. break;
  311. }
  312. return ret;
  313. }
  314. int spi_flash_cmd_write_mode(struct spi_flash *flash, u32 offset,u32 len, void *buf, u32 mode)
  315. {
  316. struct spi_slave *spi = flash->spi;
  317. unsigned long byte_addr, page_size;
  318. u32 write_addr;
  319. u32 chunk_len, actual;
  320. int ret;
  321. u8 cmd[4];
  322. int write_data = 1;
  323. unsigned long flags = SPI_XFER_BEGIN;
  324. page_size = flash->page_size;
  325. switch (mode){
  326. case 1:
  327. cmd[0] = CMD_PAGE_PROGRAM;
  328. break;
  329. case 4:
  330. cmd[0] = CMD_PAGE_PROGRAM_QUAD;
  331. #ifdef ISP_BOARD
  332. spi_flash_write_status_bit(flash, 0x00, STATUS_QE);
  333. #else
  334. spi_flash_write_status_bit(flash, 0x00, 0x00, 0, STATUS_QE);
  335. #endif
  336. break;
  337. default:
  338. cmd[0] = CMD_PAGE_PROGRAM;
  339. break;
  340. }
  341. for (actual = 0; actual < len; actual += chunk_len)
  342. {
  343. write_addr = offset;
  344. byte_addr = offset % page_size;
  345. chunk_len = min(len - actual, page_size - byte_addr);
  346. spi_flash_addr(write_addr, cmd);
  347. ret = spi_flash_cmd_write_enable(flash);
  348. if (ret < 0) {
  349. //uart_printf("SF: enabling write failed\n");
  350. break;
  351. }
  352. spi_flash_cmd_wait_enable(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
  353. #if 1
  354. if (mode == 1)
  355. {
  356. ret = spi_flash_cmd_write(flash->spi, cmd, 4,
  357. (unsigned char*)buf + actual, chunk_len);
  358. if (ret < 0) {
  359. //uart_printf("SF: write failed\n");
  360. break;
  361. }
  362. }
  363. #endif
  364. if (mode == 4)
  365. {
  366. flags = SPI_XFER_BEGIN;
  367. if (chunk_len == 0)
  368. flags |= SPI_XFER_END;
  369. ret = spi_xfer(spi, 4 * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  370. if (ret < 0)
  371. {
  372. //uart_printf("xfer failed\n");
  373. return ret;
  374. }
  375. else if (chunk_len != 0)
  376. {
  377. //qspi_mode_ctl(SPI4_DATEMODE_4);
  378. ret = spi_xfer(spi, chunk_len * 8, (unsigned char*)buf + actual, NULL, SPI_XFER_END, SPI_DATAMODE_8);
  379. }
  380. }
  381. //qspi_mode_ctl(SPI4_DATEMODE_0);
  382. ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
  383. if (ret < 0)
  384. {
  385. //uart_printf("SF: spi_flash_cmd_wait_ready failed\n");
  386. break;
  387. }
  388. ret = spi_flash_cmd_write_disable(flash->spi);
  389. if (ret < 0)
  390. {
  391. //uart_printf("SF: disable write failed\n");
  392. break;
  393. }
  394. offset += chunk_len;
  395. //uart_printf("SF: program %s %d bytes @ %d\n", ret ? "failure" : "success", len, offset);
  396. }
  397. return ret;
  398. }
  399. int spi_flash_read_common(struct spi_flash *flash, u8 *cmd,
  400. u32 cmd_len, void *data, u32 data_len)
  401. {
  402. struct spi_slave *spi = flash->spi;
  403. int ret;
  404. ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
  405. return ret;
  406. }
  407. int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
  408. u32 len, void *data, u32 mode)
  409. {
  410. u8 cmd[5];
  411. cmd[0] = CMD_READ_ARRAY_FAST;
  412. spi_flash_addr(offset, cmd);
  413. cmd[4] = 0x00;
  414. return spi_flash_read_common(flash, cmd, sizeof(cmd), data, len);
  415. }
  416. int spi_flash_read_mode(struct spi_flash *flash, u32 offset,
  417. u32 len, void *data, u32 mode)
  418. {
  419. struct spi_slave *spi = flash->spi;
  420. u8 cmd[5];
  421. int ret;
  422. int write_data = 0;
  423. u8 status[2] = {2};
  424. int i = 0;
  425. switch (mode)
  426. {
  427. case 1:
  428. cmd[0] = CMD_READ_ARRAY_FAST;
  429. break;
  430. case 2:
  431. cmd[0] = CMD_READ_ARRAY_DUAL;
  432. break;
  433. case 4:
  434. #ifdef ISP_BOARD
  435. cmd[0] = CMD_READ_ARRAY_LEGACY;
  436. //spi_flash_cmd_write_reg_mode(flash, flash_reg_offset, 1, flash_reg);
  437. //flash_reg[0] = 0;
  438. //spi_flash_cmd_write_reg_mode(flash, flash_reg_offset, 1, flash_reg);
  439. //spi_flash_read_reg_mode(flash, flash_reg_offset, 1, flash_reg);
  440. #else
  441. cmd[0] = CMD_READ_ARRAY_QUAD;
  442. spi_flash_write_status_bit(flash, 0x00, 0x00, 0, STATUS_QE);
  443. #endif
  444. break;
  445. default:
  446. cmd[0] = CMD_READ_ARRAY_FAST;
  447. break;
  448. }
  449. //spi_flash_cmd_poll_bit(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT, CMD_READ_STATUS1, ~STATUS_QE);
  450. spi_flash_addr(offset, cmd);
  451. cmd[4] = 0x00;
  452. ret = spi_xfer(spi, 5*8, cmd, NULL, SPI_XFER_BEGIN, SPI_DATAMODE_8);
  453. if (ret < 0)
  454. {
  455. //uart_printf("xfer failed\n");
  456. return ret;
  457. }
  458. ret = spi_xfer(spi, len*8, NULL, data, SPI_XFER_END, SPI_DATAMODE_8);
  459. if (ret < 0)
  460. {
  461. //uart_printf("xfer failed\n");
  462. return ret;
  463. }
  464. return 0;
  465. }