syscon_iopad_ctrl_macro.h 65 KB

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  1. /**
  2. ******************************************************************************
  3. * @file syscon_iopad_ctrl_macro.h
  4. * @author StarFive Technology
  5. * @version V1.0
  6. * @date 06/25/2020
  7. * @brief
  8. ******************************************************************************
  9. * @copy
  10. *
  11. * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  12. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  13. * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
  14. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  15. * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  16. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  17. *
  18. * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
  19. */
  20. #ifndef _SYSCON_IOPAD_CTRL_MACRO_H_
  21. #define _SYSCON_IOPAD_CTRL_MACRO_H_
  22. //#define SYSCON_IOPAD_CTRL_BASE_ADDR 0x0
  23. #define syscon_iopad_ctrl_register0_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x0
  24. #define syscon_iopad_ctrl_register1_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x4
  25. #define syscon_iopad_ctrl_register2_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x8
  26. #define syscon_iopad_ctrl_register3_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xC
  27. #define syscon_iopad_ctrl_register4_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x10
  28. #define syscon_iopad_ctrl_register5_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x14
  29. #define syscon_iopad_ctrl_register6_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x18
  30. #define syscon_iopad_ctrl_register7_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x1C
  31. #define syscon_iopad_ctrl_register8_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x20
  32. #define syscon_iopad_ctrl_register9_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x24
  33. #define syscon_iopad_ctrl_register10_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x28
  34. #define syscon_iopad_ctrl_register11_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x2C
  35. #define syscon_iopad_ctrl_register12_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x30
  36. #define syscon_iopad_ctrl_register13_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x34
  37. #define syscon_iopad_ctrl_register14_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x38
  38. #define syscon_iopad_ctrl_register15_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x3C
  39. #define syscon_iopad_ctrl_register16_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x40
  40. #define syscon_iopad_ctrl_register17_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x44
  41. #define syscon_iopad_ctrl_register18_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x48
  42. #define syscon_iopad_ctrl_register19_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x4C
  43. #define syscon_iopad_ctrl_register20_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x50
  44. #define syscon_iopad_ctrl_register21_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x54
  45. #define syscon_iopad_ctrl_register22_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x58
  46. #define syscon_iopad_ctrl_register23_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x5C
  47. #define syscon_iopad_ctrl_register24_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x60
  48. #define syscon_iopad_ctrl_register25_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x64
  49. #define syscon_iopad_ctrl_register26_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x68
  50. #define syscon_iopad_ctrl_register27_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x6C
  51. #define syscon_iopad_ctrl_register28_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x70
  52. #define syscon_iopad_ctrl_register29_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x74
  53. #define syscon_iopad_ctrl_register30_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x78
  54. #define syscon_iopad_ctrl_register31_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x7C
  55. #define syscon_iopad_ctrl_register32_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x80
  56. #define syscon_iopad_ctrl_register33_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x84
  57. #define syscon_iopad_ctrl_register34_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x88
  58. #define syscon_iopad_ctrl_register35_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x8C
  59. #define syscon_iopad_ctrl_register36_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x90
  60. #define syscon_iopad_ctrl_register37_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x94
  61. #define syscon_iopad_ctrl_register38_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x98
  62. #define syscon_iopad_ctrl_register39_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x9C
  63. #define syscon_iopad_ctrl_register40_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xA0
  64. #define syscon_iopad_ctrl_register41_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xA4
  65. #define syscon_iopad_ctrl_register42_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xA8
  66. #define syscon_iopad_ctrl_register43_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xAC
  67. #define syscon_iopad_ctrl_register44_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xB0
  68. #define syscon_iopad_ctrl_register45_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xB4
  69. #define syscon_iopad_ctrl_register46_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xB8
  70. #define syscon_iopad_ctrl_register47_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xBC
  71. #define syscon_iopad_ctrl_register48_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xC0
  72. #define syscon_iopad_ctrl_register49_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xC4
  73. #define syscon_iopad_ctrl_register50_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xC8
  74. #define syscon_iopad_ctrl_register51_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xCC
  75. #define syscon_iopad_ctrl_register52_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xD0
  76. #define syscon_iopad_ctrl_register53_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xD4
  77. #define syscon_iopad_ctrl_register54_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xD8
  78. #define syscon_iopad_ctrl_register55_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xDC
  79. #define syscon_iopad_ctrl_register56_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xE0
  80. #define syscon_iopad_ctrl_register57_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xE4
  81. #define syscon_iopad_ctrl_register58_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xE8
  82. #define syscon_iopad_ctrl_register59_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xEC
  83. #define syscon_iopad_ctrl_register60_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xF0
  84. #define syscon_iopad_ctrl_register61_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xF4
  85. #define syscon_iopad_ctrl_register62_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xF8
  86. #define syscon_iopad_ctrl_register63_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xFC
  87. #define syscon_iopad_ctrl_register64_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x100
  88. #define syscon_iopad_ctrl_register65_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x104
  89. #define syscon_iopad_ctrl_register66_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x108
  90. #define syscon_iopad_ctrl_register67_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x10C
  91. #define syscon_iopad_ctrl_register68_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x110
  92. #define syscon_iopad_ctrl_register69_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x114
  93. #define syscon_iopad_ctrl_register70_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x118
  94. #define syscon_iopad_ctrl_register71_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x11C
  95. #define syscon_iopad_ctrl_register72_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x120
  96. #define syscon_iopad_ctrl_register73_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x124
  97. #define syscon_iopad_ctrl_register74_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x128
  98. #define syscon_iopad_ctrl_register75_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x12C
  99. #define syscon_iopad_ctrl_register76_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x130
  100. #define syscon_iopad_ctrl_register77_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x134
  101. #define syscon_iopad_ctrl_register78_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x138
  102. #define syscon_iopad_ctrl_register79_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x13C
  103. #define syscon_iopad_ctrl_register80_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x140
  104. #define syscon_iopad_ctrl_register81_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x144
  105. #define syscon_iopad_ctrl_register82_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x148
  106. #define syscon_iopad_ctrl_register83_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x14C
  107. #define syscon_iopad_ctrl_register84_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x150
  108. #define syscon_iopad_ctrl_register85_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x154
  109. #define syscon_iopad_ctrl_register86_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x158
  110. #define syscon_iopad_ctrl_register87_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x15C
  111. #define syscon_iopad_ctrl_register88_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x160
  112. #define syscon_iopad_ctrl_register89_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x164
  113. #define syscon_iopad_ctrl_register90_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x168
  114. #define syscon_iopad_ctrl_register91_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x16C
  115. #define syscon_iopad_ctrl_register92_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x170
  116. #define syscon_iopad_ctrl_register93_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x174
  117. #define syscon_iopad_ctrl_register94_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x178
  118. #define syscon_iopad_ctrl_register95_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x17C
  119. #define syscon_iopad_ctrl_register96_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x180
  120. #define syscon_iopad_ctrl_register97_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x184
  121. #define syscon_iopad_ctrl_register98_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x188
  122. #define syscon_iopad_ctrl_register99_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x18C
  123. #define syscon_iopad_ctrl_register100_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x190
  124. #define syscon_iopad_ctrl_register101_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x194
  125. #define syscon_iopad_ctrl_register102_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x198
  126. #define syscon_iopad_ctrl_register103_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x19C
  127. #define syscon_iopad_ctrl_register104_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x1A0
  128. #define _SET_SYSCON_REG_register0_SCFG_gpio_pad_ctrl_0(v) { \
  129. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register0_REG_ADDR); \
  130. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  131. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  132. MA_OUTW(syscon_iopad_ctrl_register0_REG_ADDR,_ezchip_macro_read_value_); \
  133. }
  134. #define _GET_SYSCON_REG_register0_SCFG_gpio_pad_ctrl_0(_ezchip_macro_read_value_) { \
  135. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register0_REG_ADDR); \
  136. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  137. }
  138. #define _SET_SYSCON_REG_register1_SCFG_gpio_pad_ctrl_1(v) { \
  139. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register1_REG_ADDR); \
  140. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  141. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  142. MA_OUTW(syscon_iopad_ctrl_register1_REG_ADDR,_ezchip_macro_read_value_); \
  143. }
  144. #define _GET_SYSCON_REG_register1_SCFG_gpio_pad_ctrl_1(_ezchip_macro_read_value_) { \
  145. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register1_REG_ADDR); \
  146. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  147. }
  148. #define _SET_SYSCON_REG_register2_SCFG_gpio_pad_ctrl_2(v) { \
  149. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register2_REG_ADDR); \
  150. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  151. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  152. MA_OUTW(syscon_iopad_ctrl_register2_REG_ADDR,_ezchip_macro_read_value_); \
  153. }
  154. #define _GET_SYSCON_REG_register2_SCFG_gpio_pad_ctrl_2(_ezchip_macro_read_value_) { \
  155. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register2_REG_ADDR); \
  156. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  157. }
  158. #define _SET_SYSCON_REG_register3_SCFG_gpio_pad_ctrl_3(v) { \
  159. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register3_REG_ADDR); \
  160. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  161. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  162. MA_OUTW(syscon_iopad_ctrl_register3_REG_ADDR,_ezchip_macro_read_value_); \
  163. }
  164. #define _GET_SYSCON_REG_register3_SCFG_gpio_pad_ctrl_3(_ezchip_macro_read_value_) { \
  165. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register3_REG_ADDR); \
  166. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  167. }
  168. #define _SET_SYSCON_REG_register4_SCFG_gpio_pad_ctrl_4(v) { \
  169. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register4_REG_ADDR); \
  170. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  171. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  172. MA_OUTW(syscon_iopad_ctrl_register4_REG_ADDR,_ezchip_macro_read_value_); \
  173. }
  174. #define _GET_SYSCON_REG_register4_SCFG_gpio_pad_ctrl_4(_ezchip_macro_read_value_) { \
  175. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register4_REG_ADDR); \
  176. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  177. }
  178. #define _SET_SYSCON_REG_register5_SCFG_gpio_pad_ctrl_5(v) { \
  179. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register5_REG_ADDR); \
  180. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  181. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  182. MA_OUTW(syscon_iopad_ctrl_register5_REG_ADDR,_ezchip_macro_read_value_); \
  183. }
  184. #define _GET_SYSCON_REG_register5_SCFG_gpio_pad_ctrl_5(_ezchip_macro_read_value_) { \
  185. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register5_REG_ADDR); \
  186. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  187. }
  188. #define _SET_SYSCON_REG_register6_SCFG_gpio_pad_ctrl_6(v) { \
  189. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register6_REG_ADDR); \
  190. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  191. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  192. MA_OUTW(syscon_iopad_ctrl_register6_REG_ADDR,_ezchip_macro_read_value_); \
  193. }
  194. #define _GET_SYSCON_REG_register6_SCFG_gpio_pad_ctrl_6(_ezchip_macro_read_value_) { \
  195. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register6_REG_ADDR); \
  196. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  197. }
  198. #define _SET_SYSCON_REG_register7_SCFG_gpio_pad_ctrl_7(v) { \
  199. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register7_REG_ADDR); \
  200. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  201. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  202. MA_OUTW(syscon_iopad_ctrl_register7_REG_ADDR,_ezchip_macro_read_value_); \
  203. }
  204. #define _GET_SYSCON_REG_register7_SCFG_gpio_pad_ctrl_7(_ezchip_macro_read_value_) { \
  205. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register7_REG_ADDR); \
  206. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  207. }
  208. #define _SET_SYSCON_REG_register8_SCFG_gpio_pad_ctrl_8(v) { \
  209. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register8_REG_ADDR); \
  210. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  211. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  212. MA_OUTW(syscon_iopad_ctrl_register8_REG_ADDR,_ezchip_macro_read_value_); \
  213. }
  214. #define _GET_SYSCON_REG_register8_SCFG_gpio_pad_ctrl_8(_ezchip_macro_read_value_) { \
  215. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register8_REG_ADDR); \
  216. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  217. }
  218. #define _SET_SYSCON_REG_register9_SCFG_gpio_pad_ctrl_9(v) { \
  219. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register9_REG_ADDR); \
  220. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  221. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  222. MA_OUTW(syscon_iopad_ctrl_register9_REG_ADDR,_ezchip_macro_read_value_); \
  223. }
  224. #define _GET_SYSCON_REG_register9_SCFG_gpio_pad_ctrl_9(_ezchip_macro_read_value_) { \
  225. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register9_REG_ADDR); \
  226. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  227. }
  228. #define _SET_SYSCON_REG_register10_SCFG_gpio_pad_ctrl_10(v) { \
  229. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register10_REG_ADDR); \
  230. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  231. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  232. MA_OUTW(syscon_iopad_ctrl_register10_REG_ADDR,_ezchip_macro_read_value_); \
  233. }
  234. #define _GET_SYSCON_REG_register10_SCFG_gpio_pad_ctrl_10(_ezchip_macro_read_value_) { \
  235. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register10_REG_ADDR); \
  236. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  237. }
  238. #define _SET_SYSCON_REG_register11_SCFG_gpio_pad_ctrl_11(v) { \
  239. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register11_REG_ADDR); \
  240. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  241. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  242. MA_OUTW(syscon_iopad_ctrl_register11_REG_ADDR,_ezchip_macro_read_value_); \
  243. }
  244. #define _GET_SYSCON_REG_register11_SCFG_gpio_pad_ctrl_11(_ezchip_macro_read_value_) { \
  245. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register11_REG_ADDR); \
  246. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  247. }
  248. #define _SET_SYSCON_REG_register12_SCFG_gpio_pad_ctrl_12(v) { \
  249. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register12_REG_ADDR); \
  250. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  251. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  252. MA_OUTW(syscon_iopad_ctrl_register12_REG_ADDR,_ezchip_macro_read_value_); \
  253. }
  254. #define _GET_SYSCON_REG_register12_SCFG_gpio_pad_ctrl_12(_ezchip_macro_read_value_) { \
  255. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register12_REG_ADDR); \
  256. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  257. }
  258. #define _SET_SYSCON_REG_register13_SCFG_gpio_pad_ctrl_13(v) { \
  259. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register13_REG_ADDR); \
  260. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  261. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  262. MA_OUTW(syscon_iopad_ctrl_register13_REG_ADDR,_ezchip_macro_read_value_); \
  263. }
  264. #define _GET_SYSCON_REG_register13_SCFG_gpio_pad_ctrl_13(_ezchip_macro_read_value_) { \
  265. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register13_REG_ADDR); \
  266. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  267. }
  268. #define _SET_SYSCON_REG_register14_SCFG_gpio_pad_ctrl_14(v) { \
  269. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register14_REG_ADDR); \
  270. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  271. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  272. MA_OUTW(syscon_iopad_ctrl_register14_REG_ADDR,_ezchip_macro_read_value_); \
  273. }
  274. #define _GET_SYSCON_REG_register14_SCFG_gpio_pad_ctrl_14(_ezchip_macro_read_value_) { \
  275. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register14_REG_ADDR); \
  276. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  277. }
  278. #define _SET_SYSCON_REG_register15_SCFG_gpio_pad_ctrl_15(v) { \
  279. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register15_REG_ADDR); \
  280. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  281. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  282. MA_OUTW(syscon_iopad_ctrl_register15_REG_ADDR,_ezchip_macro_read_value_); \
  283. }
  284. #define _GET_SYSCON_REG_register15_SCFG_gpio_pad_ctrl_15(_ezchip_macro_read_value_) { \
  285. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register15_REG_ADDR); \
  286. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  287. }
  288. #define _SET_SYSCON_REG_register16_SCFG_gpio_pad_ctrl_16(v) { \
  289. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register16_REG_ADDR); \
  290. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  291. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  292. MA_OUTW(syscon_iopad_ctrl_register16_REG_ADDR,_ezchip_macro_read_value_); \
  293. }
  294. #define _GET_SYSCON_REG_register16_SCFG_gpio_pad_ctrl_16(_ezchip_macro_read_value_) { \
  295. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register16_REG_ADDR); \
  296. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  297. }
  298. #define _SET_SYSCON_REG_register17_SCFG_gpio_pad_ctrl_17(v) { \
  299. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register17_REG_ADDR); \
  300. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  301. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  302. MA_OUTW(syscon_iopad_ctrl_register17_REG_ADDR,_ezchip_macro_read_value_); \
  303. }
  304. #define _GET_SYSCON_REG_register17_SCFG_gpio_pad_ctrl_17(_ezchip_macro_read_value_) { \
  305. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register17_REG_ADDR); \
  306. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  307. }
  308. #define _SET_SYSCON_REG_register18_SCFG_gpio_pad_ctrl_18(v) { \
  309. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register18_REG_ADDR); \
  310. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  311. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  312. MA_OUTW(syscon_iopad_ctrl_register18_REG_ADDR,_ezchip_macro_read_value_); \
  313. }
  314. #define _GET_SYSCON_REG_register18_SCFG_gpio_pad_ctrl_18(_ezchip_macro_read_value_) { \
  315. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register18_REG_ADDR); \
  316. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  317. }
  318. #define _SET_SYSCON_REG_register19_SCFG_gpio_pad_ctrl_19(v) { \
  319. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register19_REG_ADDR); \
  320. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  321. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  322. MA_OUTW(syscon_iopad_ctrl_register19_REG_ADDR,_ezchip_macro_read_value_); \
  323. }
  324. #define _GET_SYSCON_REG_register19_SCFG_gpio_pad_ctrl_19(_ezchip_macro_read_value_) { \
  325. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register19_REG_ADDR); \
  326. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  327. }
  328. #define _SET_SYSCON_REG_register20_SCFG_gpio_pad_ctrl_20(v) { \
  329. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register20_REG_ADDR); \
  330. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  331. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  332. MA_OUTW(syscon_iopad_ctrl_register20_REG_ADDR,_ezchip_macro_read_value_); \
  333. }
  334. #define _GET_SYSCON_REG_register20_SCFG_gpio_pad_ctrl_20(_ezchip_macro_read_value_) { \
  335. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register20_REG_ADDR); \
  336. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  337. }
  338. #define _SET_SYSCON_REG_register21_SCFG_gpio_pad_ctrl_21(v) { \
  339. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register21_REG_ADDR); \
  340. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  341. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  342. MA_OUTW(syscon_iopad_ctrl_register21_REG_ADDR,_ezchip_macro_read_value_); \
  343. }
  344. #define _GET_SYSCON_REG_register21_SCFG_gpio_pad_ctrl_21(_ezchip_macro_read_value_) { \
  345. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register21_REG_ADDR); \
  346. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  347. }
  348. #define _SET_SYSCON_REG_register22_SCFG_gpio_pad_ctrl_22(v) { \
  349. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register22_REG_ADDR); \
  350. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  351. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  352. MA_OUTW(syscon_iopad_ctrl_register22_REG_ADDR,_ezchip_macro_read_value_); \
  353. }
  354. #define _GET_SYSCON_REG_register22_SCFG_gpio_pad_ctrl_22(_ezchip_macro_read_value_) { \
  355. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register22_REG_ADDR); \
  356. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  357. }
  358. #define _SET_SYSCON_REG_register23_SCFG_gpio_pad_ctrl_23(v) { \
  359. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register23_REG_ADDR); \
  360. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  361. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  362. MA_OUTW(syscon_iopad_ctrl_register23_REG_ADDR,_ezchip_macro_read_value_); \
  363. }
  364. #define _GET_SYSCON_REG_register23_SCFG_gpio_pad_ctrl_23(_ezchip_macro_read_value_) { \
  365. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register23_REG_ADDR); \
  366. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  367. }
  368. #define _SET_SYSCON_REG_register24_SCFG_gpio_pad_ctrl_24(v) { \
  369. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register24_REG_ADDR); \
  370. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  371. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  372. MA_OUTW(syscon_iopad_ctrl_register24_REG_ADDR,_ezchip_macro_read_value_); \
  373. }
  374. #define _GET_SYSCON_REG_register24_SCFG_gpio_pad_ctrl_24(_ezchip_macro_read_value_) { \
  375. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register24_REG_ADDR); \
  376. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  377. }
  378. #define _SET_SYSCON_REG_register25_SCFG_gpio_pad_ctrl_25(v) { \
  379. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register25_REG_ADDR); \
  380. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  381. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  382. MA_OUTW(syscon_iopad_ctrl_register25_REG_ADDR,_ezchip_macro_read_value_); \
  383. }
  384. #define _GET_SYSCON_REG_register25_SCFG_gpio_pad_ctrl_25(_ezchip_macro_read_value_) { \
  385. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register25_REG_ADDR); \
  386. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  387. }
  388. #define _SET_SYSCON_REG_register26_SCFG_gpio_pad_ctrl_26(v) { \
  389. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register26_REG_ADDR); \
  390. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  391. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  392. MA_OUTW(syscon_iopad_ctrl_register26_REG_ADDR,_ezchip_macro_read_value_); \
  393. }
  394. #define _GET_SYSCON_REG_register26_SCFG_gpio_pad_ctrl_26(_ezchip_macro_read_value_) { \
  395. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register26_REG_ADDR); \
  396. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  397. }
  398. #define _SET_SYSCON_REG_register27_SCFG_gpio_pad_ctrl_27(v) { \
  399. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register27_REG_ADDR); \
  400. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  401. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  402. MA_OUTW(syscon_iopad_ctrl_register27_REG_ADDR,_ezchip_macro_read_value_); \
  403. }
  404. #define _GET_SYSCON_REG_register27_SCFG_gpio_pad_ctrl_27(_ezchip_macro_read_value_) { \
  405. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register27_REG_ADDR); \
  406. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  407. }
  408. #define _SET_SYSCON_REG_register28_SCFG_gpio_pad_ctrl_28(v) { \
  409. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register28_REG_ADDR); \
  410. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  411. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  412. MA_OUTW(syscon_iopad_ctrl_register28_REG_ADDR,_ezchip_macro_read_value_); \
  413. }
  414. #define _GET_SYSCON_REG_register28_SCFG_gpio_pad_ctrl_28(_ezchip_macro_read_value_) { \
  415. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register28_REG_ADDR); \
  416. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  417. }
  418. #define _SET_SYSCON_REG_register29_SCFG_gpio_pad_ctrl_29(v) { \
  419. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register29_REG_ADDR); \
  420. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  421. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  422. MA_OUTW(syscon_iopad_ctrl_register29_REG_ADDR,_ezchip_macro_read_value_); \
  423. }
  424. #define _GET_SYSCON_REG_register29_SCFG_gpio_pad_ctrl_29(_ezchip_macro_read_value_) { \
  425. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register29_REG_ADDR); \
  426. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  427. }
  428. #define _SET_SYSCON_REG_register30_SCFG_gpio_pad_ctrl_30(v) { \
  429. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register30_REG_ADDR); \
  430. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  431. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  432. MA_OUTW(syscon_iopad_ctrl_register30_REG_ADDR,_ezchip_macro_read_value_); \
  433. }
  434. #define _GET_SYSCON_REG_register30_SCFG_gpio_pad_ctrl_30(_ezchip_macro_read_value_) { \
  435. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register30_REG_ADDR); \
  436. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  437. }
  438. #define _SET_SYSCON_REG_register31_SCFG_gpio_pad_ctrl_31(v) { \
  439. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register31_REG_ADDR); \
  440. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  441. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  442. MA_OUTW(syscon_iopad_ctrl_register31_REG_ADDR,_ezchip_macro_read_value_); \
  443. }
  444. #define _GET_SYSCON_REG_register31_SCFG_gpio_pad_ctrl_31(_ezchip_macro_read_value_) { \
  445. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register31_REG_ADDR); \
  446. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  447. }
  448. #define _SET_SYSCON_REG_register32_SCFG_funcshare_pad_ctrl_0(v) { \
  449. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register32_REG_ADDR); \
  450. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  451. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  452. MA_OUTW(syscon_iopad_ctrl_register32_REG_ADDR,_ezchip_macro_read_value_); \
  453. }
  454. #define _GET_SYSCON_REG_register32_SCFG_funcshare_pad_ctrl_0(_ezchip_macro_read_value_) { \
  455. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register32_REG_ADDR); \
  456. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  457. }
  458. #define _SET_SYSCON_REG_register33_SCFG_funcshare_pad_ctrl_1(v) { \
  459. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register33_REG_ADDR); \
  460. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  461. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  462. MA_OUTW(syscon_iopad_ctrl_register33_REG_ADDR,_ezchip_macro_read_value_); \
  463. }
  464. #define _GET_SYSCON_REG_register33_SCFG_funcshare_pad_ctrl_1(_ezchip_macro_read_value_) { \
  465. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register33_REG_ADDR); \
  466. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  467. }
  468. #define _SET_SYSCON_REG_register34_SCFG_funcshare_pad_ctrl_2(v) { \
  469. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register34_REG_ADDR); \
  470. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  471. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  472. MA_OUTW(syscon_iopad_ctrl_register34_REG_ADDR,_ezchip_macro_read_value_); \
  473. }
  474. #define _GET_SYSCON_REG_register34_SCFG_funcshare_pad_ctrl_2(_ezchip_macro_read_value_) { \
  475. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register34_REG_ADDR); \
  476. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  477. }
  478. #define _SET_SYSCON_REG_register35_SCFG_funcshare_pad_ctrl_3(v) { \
  479. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register35_REG_ADDR); \
  480. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  481. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  482. MA_OUTW(syscon_iopad_ctrl_register35_REG_ADDR,_ezchip_macro_read_value_); \
  483. }
  484. #define _GET_SYSCON_REG_register35_SCFG_funcshare_pad_ctrl_3(_ezchip_macro_read_value_) { \
  485. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register35_REG_ADDR); \
  486. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  487. }
  488. #define _SET_SYSCON_REG_register36_SCFG_funcshare_pad_ctrl_4(v) { \
  489. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register36_REG_ADDR); \
  490. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  491. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  492. MA_OUTW(syscon_iopad_ctrl_register36_REG_ADDR,_ezchip_macro_read_value_); \
  493. }
  494. #define _GET_SYSCON_REG_register36_SCFG_funcshare_pad_ctrl_4(_ezchip_macro_read_value_) { \
  495. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register36_REG_ADDR); \
  496. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  497. }
  498. #define _SET_SYSCON_REG_register37_SCFG_funcshare_pad_ctrl_5(v) { \
  499. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register37_REG_ADDR); \
  500. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  501. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  502. MA_OUTW(syscon_iopad_ctrl_register37_REG_ADDR,_ezchip_macro_read_value_); \
  503. }
  504. #define _GET_SYSCON_REG_register37_SCFG_funcshare_pad_ctrl_5(_ezchip_macro_read_value_) { \
  505. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register37_REG_ADDR); \
  506. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  507. }
  508. #define _SET_SYSCON_REG_register38_SCFG_funcshare_pad_ctrl_6(v) { \
  509. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register38_REG_ADDR); \
  510. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  511. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  512. MA_OUTW(syscon_iopad_ctrl_register38_REG_ADDR,_ezchip_macro_read_value_); \
  513. }
  514. #define _GET_SYSCON_REG_register38_SCFG_funcshare_pad_ctrl_6(_ezchip_macro_read_value_) { \
  515. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register38_REG_ADDR); \
  516. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  517. }
  518. #define _SET_SYSCON_REG_register39_SCFG_funcshare_pad_ctrl_7(v) { \
  519. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register39_REG_ADDR); \
  520. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  521. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  522. MA_OUTW(syscon_iopad_ctrl_register39_REG_ADDR,_ezchip_macro_read_value_); \
  523. }
  524. #define _GET_SYSCON_REG_register39_SCFG_funcshare_pad_ctrl_7(_ezchip_macro_read_value_) { \
  525. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register39_REG_ADDR); \
  526. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  527. }
  528. #define _SET_SYSCON_REG_register40_SCFG_funcshare_pad_ctrl_8(v) { \
  529. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register40_REG_ADDR); \
  530. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  531. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  532. MA_OUTW(syscon_iopad_ctrl_register40_REG_ADDR,_ezchip_macro_read_value_); \
  533. }
  534. #define _GET_SYSCON_REG_register40_SCFG_funcshare_pad_ctrl_8(_ezchip_macro_read_value_) { \
  535. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register40_REG_ADDR); \
  536. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  537. }
  538. #define _SET_SYSCON_REG_register41_SCFG_funcshare_pad_ctrl_9(v) { \
  539. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register41_REG_ADDR); \
  540. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  541. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  542. MA_OUTW(syscon_iopad_ctrl_register41_REG_ADDR,_ezchip_macro_read_value_); \
  543. }
  544. #define _GET_SYSCON_REG_register41_SCFG_funcshare_pad_ctrl_9(_ezchip_macro_read_value_) { \
  545. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register41_REG_ADDR); \
  546. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  547. }
  548. #define _SET_SYSCON_REG_register42_SCFG_funcshare_pad_ctrl_10(v) { \
  549. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register42_REG_ADDR); \
  550. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  551. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  552. MA_OUTW(syscon_iopad_ctrl_register42_REG_ADDR,_ezchip_macro_read_value_); \
  553. }
  554. #define _GET_SYSCON_REG_register42_SCFG_funcshare_pad_ctrl_10(_ezchip_macro_read_value_) { \
  555. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register42_REG_ADDR); \
  556. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  557. }
  558. #define _SET_SYSCON_REG_register43_SCFG_funcshare_pad_ctrl_11(v) { \
  559. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register43_REG_ADDR); \
  560. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  561. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  562. MA_OUTW(syscon_iopad_ctrl_register43_REG_ADDR,_ezchip_macro_read_value_); \
  563. }
  564. #define _GET_SYSCON_REG_register43_SCFG_funcshare_pad_ctrl_11(_ezchip_macro_read_value_) { \
  565. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register43_REG_ADDR); \
  566. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  567. }
  568. #define _SET_SYSCON_REG_register44_SCFG_funcshare_pad_ctrl_12(v) { \
  569. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register44_REG_ADDR); \
  570. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  571. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  572. MA_OUTW(syscon_iopad_ctrl_register44_REG_ADDR,_ezchip_macro_read_value_); \
  573. }
  574. #define _GET_SYSCON_REG_register44_SCFG_funcshare_pad_ctrl_12(_ezchip_macro_read_value_) { \
  575. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register44_REG_ADDR); \
  576. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  577. }
  578. #define _SET_SYSCON_REG_register45_SCFG_funcshare_pad_ctrl_13(v) { \
  579. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register45_REG_ADDR); \
  580. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  581. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  582. MA_OUTW(syscon_iopad_ctrl_register45_REG_ADDR,_ezchip_macro_read_value_); \
  583. }
  584. #define _GET_SYSCON_REG_register45_SCFG_funcshare_pad_ctrl_13(_ezchip_macro_read_value_) { \
  585. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register45_REG_ADDR); \
  586. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  587. }
  588. #define _SET_SYSCON_REG_register46_SCFG_funcshare_pad_ctrl_14(v) { \
  589. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register46_REG_ADDR); \
  590. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  591. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  592. MA_OUTW(syscon_iopad_ctrl_register46_REG_ADDR,_ezchip_macro_read_value_); \
  593. }
  594. #define _GET_SYSCON_REG_register46_SCFG_funcshare_pad_ctrl_14(_ezchip_macro_read_value_) { \
  595. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register46_REG_ADDR); \
  596. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  597. }
  598. #define _SET_SYSCON_REG_register47_SCFG_funcshare_pad_ctrl_15(v) { \
  599. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register47_REG_ADDR); \
  600. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  601. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  602. MA_OUTW(syscon_iopad_ctrl_register47_REG_ADDR,_ezchip_macro_read_value_); \
  603. }
  604. #define _GET_SYSCON_REG_register47_SCFG_funcshare_pad_ctrl_15(_ezchip_macro_read_value_) { \
  605. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register47_REG_ADDR); \
  606. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  607. }
  608. #define _SET_SYSCON_REG_register48_SCFG_funcshare_pad_ctrl_16(v) { \
  609. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register48_REG_ADDR); \
  610. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  611. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  612. MA_OUTW(syscon_iopad_ctrl_register48_REG_ADDR,_ezchip_macro_read_value_); \
  613. }
  614. #define _GET_SYSCON_REG_register48_SCFG_funcshare_pad_ctrl_16(_ezchip_macro_read_value_) { \
  615. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register48_REG_ADDR); \
  616. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  617. }
  618. #define _SET_SYSCON_REG_register49_SCFG_funcshare_pad_ctrl_17(v) { \
  619. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register49_REG_ADDR); \
  620. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  621. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  622. MA_OUTW(syscon_iopad_ctrl_register49_REG_ADDR,_ezchip_macro_read_value_); \
  623. }
  624. #define _GET_SYSCON_REG_register49_SCFG_funcshare_pad_ctrl_17(_ezchip_macro_read_value_) { \
  625. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register49_REG_ADDR); \
  626. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  627. }
  628. #define _SET_SYSCON_REG_register50_SCFG_funcshare_pad_ctrl_18(v) { \
  629. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register50_REG_ADDR); \
  630. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  631. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  632. MA_OUTW(syscon_iopad_ctrl_register50_REG_ADDR,_ezchip_macro_read_value_); \
  633. }
  634. #define _GET_SYSCON_REG_register50_SCFG_funcshare_pad_ctrl_18(_ezchip_macro_read_value_) { \
  635. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register50_REG_ADDR); \
  636. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  637. }
  638. #define _SET_SYSCON_REG_register51_SCFG_funcshare_pad_ctrl_19(v) { \
  639. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register51_REG_ADDR); \
  640. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  641. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  642. MA_OUTW(syscon_iopad_ctrl_register51_REG_ADDR,_ezchip_macro_read_value_); \
  643. }
  644. #define _GET_SYSCON_REG_register51_SCFG_funcshare_pad_ctrl_19(_ezchip_macro_read_value_) { \
  645. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register51_REG_ADDR); \
  646. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  647. }
  648. #define _SET_SYSCON_REG_register52_SCFG_funcshare_pad_ctrl_20(v) { \
  649. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register52_REG_ADDR); \
  650. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  651. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  652. MA_OUTW(syscon_iopad_ctrl_register52_REG_ADDR,_ezchip_macro_read_value_); \
  653. }
  654. #define _GET_SYSCON_REG_register52_SCFG_funcshare_pad_ctrl_20(_ezchip_macro_read_value_) { \
  655. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register52_REG_ADDR); \
  656. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  657. }
  658. #define _SET_SYSCON_REG_register53_SCFG_funcshare_pad_ctrl_21(v) { \
  659. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register53_REG_ADDR); \
  660. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  661. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  662. MA_OUTW(syscon_iopad_ctrl_register53_REG_ADDR,_ezchip_macro_read_value_); \
  663. }
  664. #define _GET_SYSCON_REG_register53_SCFG_funcshare_pad_ctrl_21(_ezchip_macro_read_value_) { \
  665. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register53_REG_ADDR); \
  666. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  667. }
  668. #define _SET_SYSCON_REG_register54_SCFG_funcshare_pad_ctrl_22(v) { \
  669. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register54_REG_ADDR); \
  670. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  671. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  672. MA_OUTW(syscon_iopad_ctrl_register54_REG_ADDR,_ezchip_macro_read_value_); \
  673. }
  674. #define _GET_SYSCON_REG_register54_SCFG_funcshare_pad_ctrl_22(_ezchip_macro_read_value_) { \
  675. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register54_REG_ADDR); \
  676. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  677. }
  678. #define _SET_SYSCON_REG_register55_SCFG_funcshare_pad_ctrl_23(v) { \
  679. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register55_REG_ADDR); \
  680. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  681. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  682. MA_OUTW(syscon_iopad_ctrl_register55_REG_ADDR,_ezchip_macro_read_value_); \
  683. }
  684. #define _GET_SYSCON_REG_register55_SCFG_funcshare_pad_ctrl_23(_ezchip_macro_read_value_) { \
  685. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register55_REG_ADDR); \
  686. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  687. }
  688. #define _SET_SYSCON_REG_register56_SCFG_funcshare_pad_ctrl_24(v) { \
  689. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register56_REG_ADDR); \
  690. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  691. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  692. MA_OUTW(syscon_iopad_ctrl_register56_REG_ADDR,_ezchip_macro_read_value_); \
  693. }
  694. #define _GET_SYSCON_REG_register56_SCFG_funcshare_pad_ctrl_24(_ezchip_macro_read_value_) { \
  695. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register56_REG_ADDR); \
  696. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  697. }
  698. #define _SET_SYSCON_REG_register57_SCFG_funcshare_pad_ctrl_25(v) { \
  699. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register57_REG_ADDR); \
  700. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  701. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  702. MA_OUTW(syscon_iopad_ctrl_register57_REG_ADDR,_ezchip_macro_read_value_); \
  703. }
  704. #define _GET_SYSCON_REG_register57_SCFG_funcshare_pad_ctrl_25(_ezchip_macro_read_value_) { \
  705. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register57_REG_ADDR); \
  706. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  707. }
  708. #define _SET_SYSCON_REG_register58_SCFG_funcshare_pad_ctrl_26(v) { \
  709. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register58_REG_ADDR); \
  710. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  711. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  712. MA_OUTW(syscon_iopad_ctrl_register58_REG_ADDR,_ezchip_macro_read_value_); \
  713. }
  714. #define _GET_SYSCON_REG_register58_SCFG_funcshare_pad_ctrl_26(_ezchip_macro_read_value_) { \
  715. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register58_REG_ADDR); \
  716. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  717. }
  718. #define _SET_SYSCON_REG_register59_SCFG_funcshare_pad_ctrl_27(v) { \
  719. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register59_REG_ADDR); \
  720. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  721. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  722. MA_OUTW(syscon_iopad_ctrl_register59_REG_ADDR,_ezchip_macro_read_value_); \
  723. }
  724. #define _GET_SYSCON_REG_register59_SCFG_funcshare_pad_ctrl_27(_ezchip_macro_read_value_) { \
  725. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register59_REG_ADDR); \
  726. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  727. }
  728. #define _SET_SYSCON_REG_register60_SCFG_funcshare_pad_ctrl_28(v) { \
  729. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register60_REG_ADDR); \
  730. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  731. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  732. MA_OUTW(syscon_iopad_ctrl_register60_REG_ADDR,_ezchip_macro_read_value_); \
  733. }
  734. #define _GET_SYSCON_REG_register60_SCFG_funcshare_pad_ctrl_28(_ezchip_macro_read_value_) { \
  735. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register60_REG_ADDR); \
  736. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  737. }
  738. #define _SET_SYSCON_REG_register61_SCFG_funcshare_pad_ctrl_29(v) { \
  739. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register61_REG_ADDR); \
  740. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  741. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  742. MA_OUTW(syscon_iopad_ctrl_register61_REG_ADDR,_ezchip_macro_read_value_); \
  743. }
  744. #define _GET_SYSCON_REG_register61_SCFG_funcshare_pad_ctrl_29(_ezchip_macro_read_value_) { \
  745. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register61_REG_ADDR); \
  746. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  747. }
  748. #define _SET_SYSCON_REG_register62_SCFG_funcshare_pad_ctrl_30(v) { \
  749. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register62_REG_ADDR); \
  750. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  751. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  752. MA_OUTW(syscon_iopad_ctrl_register62_REG_ADDR,_ezchip_macro_read_value_); \
  753. }
  754. #define _GET_SYSCON_REG_register62_SCFG_funcshare_pad_ctrl_30(_ezchip_macro_read_value_) { \
  755. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register62_REG_ADDR); \
  756. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  757. }
  758. #define _SET_SYSCON_REG_register63_SCFG_funcshare_pad_ctrl_31(v) { \
  759. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register63_REG_ADDR); \
  760. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  761. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  762. MA_OUTW(syscon_iopad_ctrl_register63_REG_ADDR,_ezchip_macro_read_value_); \
  763. }
  764. #define _GET_SYSCON_REG_register63_SCFG_funcshare_pad_ctrl_31(_ezchip_macro_read_value_) { \
  765. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register63_REG_ADDR); \
  766. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  767. }
  768. #define _SET_SYSCON_REG_register64_SCFG_funcshare_pad_ctrl_32(v) { \
  769. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register64_REG_ADDR); \
  770. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  771. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  772. MA_OUTW(syscon_iopad_ctrl_register64_REG_ADDR,_ezchip_macro_read_value_); \
  773. }
  774. #define _GET_SYSCON_REG_register64_SCFG_funcshare_pad_ctrl_32(_ezchip_macro_read_value_) { \
  775. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register64_REG_ADDR); \
  776. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  777. }
  778. #define _SET_SYSCON_REG_register65_SCFG_funcshare_pad_ctrl_33(v) { \
  779. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register65_REG_ADDR); \
  780. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  781. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  782. MA_OUTW(syscon_iopad_ctrl_register65_REG_ADDR,_ezchip_macro_read_value_); \
  783. }
  784. #define _GET_SYSCON_REG_register65_SCFG_funcshare_pad_ctrl_33(_ezchip_macro_read_value_) { \
  785. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register65_REG_ADDR); \
  786. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  787. }
  788. #define _SET_SYSCON_REG_register66_SCFG_funcshare_pad_ctrl_34(v) { \
  789. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register66_REG_ADDR); \
  790. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  791. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  792. MA_OUTW(syscon_iopad_ctrl_register66_REG_ADDR,_ezchip_macro_read_value_); \
  793. }
  794. #define _GET_SYSCON_REG_register66_SCFG_funcshare_pad_ctrl_34(_ezchip_macro_read_value_) { \
  795. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register66_REG_ADDR); \
  796. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  797. }
  798. #define _SET_SYSCON_REG_register67_SCFG_funcshare_pad_ctrl_35(v) { \
  799. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register67_REG_ADDR); \
  800. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  801. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  802. MA_OUTW(syscon_iopad_ctrl_register67_REG_ADDR,_ezchip_macro_read_value_); \
  803. }
  804. #define _GET_SYSCON_REG_register67_SCFG_funcshare_pad_ctrl_35(_ezchip_macro_read_value_) { \
  805. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register67_REG_ADDR); \
  806. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  807. }
  808. #define _SET_SYSCON_REG_register68_SCFG_funcshare_pad_ctrl_36(v) { \
  809. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register68_REG_ADDR); \
  810. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  811. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  812. MA_OUTW(syscon_iopad_ctrl_register68_REG_ADDR,_ezchip_macro_read_value_); \
  813. }
  814. #define _GET_SYSCON_REG_register68_SCFG_funcshare_pad_ctrl_36(_ezchip_macro_read_value_) { \
  815. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register68_REG_ADDR); \
  816. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  817. }
  818. #define _SET_SYSCON_REG_register69_SCFG_funcshare_pad_ctrl_37(v) { \
  819. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register69_REG_ADDR); \
  820. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  821. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  822. MA_OUTW(syscon_iopad_ctrl_register69_REG_ADDR,_ezchip_macro_read_value_); \
  823. }
  824. #define _GET_SYSCON_REG_register69_SCFG_funcshare_pad_ctrl_37(_ezchip_macro_read_value_) { \
  825. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register69_REG_ADDR); \
  826. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  827. }
  828. #define _SET_SYSCON_REG_register70_SCFG_funcshare_pad_ctrl_38(v) { \
  829. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register70_REG_ADDR); \
  830. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  831. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  832. MA_OUTW(syscon_iopad_ctrl_register70_REG_ADDR,_ezchip_macro_read_value_); \
  833. }
  834. #define _GET_SYSCON_REG_register70_SCFG_funcshare_pad_ctrl_38(_ezchip_macro_read_value_) { \
  835. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register70_REG_ADDR); \
  836. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  837. }
  838. #define _SET_SYSCON_REG_register71_SCFG_funcshare_pad_ctrl_39(v) { \
  839. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register71_REG_ADDR); \
  840. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  841. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  842. MA_OUTW(syscon_iopad_ctrl_register71_REG_ADDR,_ezchip_macro_read_value_); \
  843. }
  844. #define _GET_SYSCON_REG_register71_SCFG_funcshare_pad_ctrl_39(_ezchip_macro_read_value_) { \
  845. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register71_REG_ADDR); \
  846. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  847. }
  848. #define _SET_SYSCON_REG_register72_SCFG_funcshare_pad_ctrl_40(v) { \
  849. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register72_REG_ADDR); \
  850. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  851. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  852. MA_OUTW(syscon_iopad_ctrl_register72_REG_ADDR,_ezchip_macro_read_value_); \
  853. }
  854. #define _GET_SYSCON_REG_register72_SCFG_funcshare_pad_ctrl_40(_ezchip_macro_read_value_) { \
  855. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register72_REG_ADDR); \
  856. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  857. }
  858. #define _SET_SYSCON_REG_register73_SCFG_funcshare_pad_ctrl_41(v) { \
  859. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register73_REG_ADDR); \
  860. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  861. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  862. MA_OUTW(syscon_iopad_ctrl_register73_REG_ADDR,_ezchip_macro_read_value_); \
  863. }
  864. #define _GET_SYSCON_REG_register73_SCFG_funcshare_pad_ctrl_41(_ezchip_macro_read_value_) { \
  865. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register73_REG_ADDR); \
  866. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  867. }
  868. #define _SET_SYSCON_REG_register74_SCFG_funcshare_pad_ctrl_42(v) { \
  869. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register74_REG_ADDR); \
  870. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  871. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  872. MA_OUTW(syscon_iopad_ctrl_register74_REG_ADDR,_ezchip_macro_read_value_); \
  873. }
  874. #define _GET_SYSCON_REG_register74_SCFG_funcshare_pad_ctrl_42(_ezchip_macro_read_value_) { \
  875. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register74_REG_ADDR); \
  876. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  877. }
  878. #define _SET_SYSCON_REG_register75_SCFG_funcshare_pad_ctrl_43(v) { \
  879. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register75_REG_ADDR); \
  880. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  881. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  882. MA_OUTW(syscon_iopad_ctrl_register75_REG_ADDR,_ezchip_macro_read_value_); \
  883. }
  884. #define _GET_SYSCON_REG_register75_SCFG_funcshare_pad_ctrl_43(_ezchip_macro_read_value_) { \
  885. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register75_REG_ADDR); \
  886. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  887. }
  888. #define _SET_SYSCON_REG_register76_SCFG_funcshare_pad_ctrl_44(v) { \
  889. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register76_REG_ADDR); \
  890. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  891. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  892. MA_OUTW(syscon_iopad_ctrl_register76_REG_ADDR,_ezchip_macro_read_value_); \
  893. }
  894. #define _GET_SYSCON_REG_register76_SCFG_funcshare_pad_ctrl_44(_ezchip_macro_read_value_) { \
  895. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register76_REG_ADDR); \
  896. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  897. }
  898. #define _SET_SYSCON_REG_register77_SCFG_funcshare_pad_ctrl_45(v) { \
  899. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register77_REG_ADDR); \
  900. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  901. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  902. MA_OUTW(syscon_iopad_ctrl_register77_REG_ADDR,_ezchip_macro_read_value_); \
  903. }
  904. #define _GET_SYSCON_REG_register77_SCFG_funcshare_pad_ctrl_45(_ezchip_macro_read_value_) { \
  905. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register77_REG_ADDR); \
  906. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  907. }
  908. #define _SET_SYSCON_REG_register78_SCFG_funcshare_pad_ctrl_46(v) { \
  909. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register78_REG_ADDR); \
  910. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  911. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  912. MA_OUTW(syscon_iopad_ctrl_register78_REG_ADDR,_ezchip_macro_read_value_); \
  913. }
  914. #define _GET_SYSCON_REG_register78_SCFG_funcshare_pad_ctrl_46(_ezchip_macro_read_value_) { \
  915. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register78_REG_ADDR); \
  916. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  917. }
  918. #define _SET_SYSCON_REG_register79_SCFG_funcshare_pad_ctrl_47(v) { \
  919. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register79_REG_ADDR); \
  920. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  921. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  922. MA_OUTW(syscon_iopad_ctrl_register79_REG_ADDR,_ezchip_macro_read_value_); \
  923. }
  924. #define _GET_SYSCON_REG_register79_SCFG_funcshare_pad_ctrl_47(_ezchip_macro_read_value_) { \
  925. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register79_REG_ADDR); \
  926. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  927. }
  928. #define _SET_SYSCON_REG_register80_SCFG_funcshare_pad_ctrl_48(v) { \
  929. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register80_REG_ADDR); \
  930. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  931. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  932. MA_OUTW(syscon_iopad_ctrl_register80_REG_ADDR,_ezchip_macro_read_value_); \
  933. }
  934. #define _GET_SYSCON_REG_register80_SCFG_funcshare_pad_ctrl_48(_ezchip_macro_read_value_) { \
  935. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register80_REG_ADDR); \
  936. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  937. }
  938. #define _SET_SYSCON_REG_register81_SCFG_funcshare_pad_ctrl_49(v) { \
  939. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register81_REG_ADDR); \
  940. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  941. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  942. MA_OUTW(syscon_iopad_ctrl_register81_REG_ADDR,_ezchip_macro_read_value_); \
  943. }
  944. #define _GET_SYSCON_REG_register81_SCFG_funcshare_pad_ctrl_49(_ezchip_macro_read_value_) { \
  945. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register81_REG_ADDR); \
  946. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  947. }
  948. #define _SET_SYSCON_REG_register82_SCFG_funcshare_pad_ctrl_50(v) { \
  949. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register82_REG_ADDR); \
  950. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  951. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  952. MA_OUTW(syscon_iopad_ctrl_register82_REG_ADDR,_ezchip_macro_read_value_); \
  953. }
  954. #define _GET_SYSCON_REG_register82_SCFG_funcshare_pad_ctrl_50(_ezchip_macro_read_value_) { \
  955. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register82_REG_ADDR); \
  956. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  957. }
  958. #define _SET_SYSCON_REG_register83_SCFG_funcshare_pad_ctrl_51(v) { \
  959. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register83_REG_ADDR); \
  960. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  961. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  962. MA_OUTW(syscon_iopad_ctrl_register83_REG_ADDR,_ezchip_macro_read_value_); \
  963. }
  964. #define _GET_SYSCON_REG_register83_SCFG_funcshare_pad_ctrl_51(_ezchip_macro_read_value_) { \
  965. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register83_REG_ADDR); \
  966. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  967. }
  968. #define _SET_SYSCON_REG_register84_SCFG_funcshare_pad_ctrl_52(v) { \
  969. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register84_REG_ADDR); \
  970. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  971. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  972. MA_OUTW(syscon_iopad_ctrl_register84_REG_ADDR,_ezchip_macro_read_value_); \
  973. }
  974. #define _GET_SYSCON_REG_register84_SCFG_funcshare_pad_ctrl_52(_ezchip_macro_read_value_) { \
  975. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register84_REG_ADDR); \
  976. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  977. }
  978. #define _SET_SYSCON_REG_register85_SCFG_funcshare_pad_ctrl_53(v) { \
  979. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register85_REG_ADDR); \
  980. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  981. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  982. MA_OUTW(syscon_iopad_ctrl_register85_REG_ADDR,_ezchip_macro_read_value_); \
  983. }
  984. #define _GET_SYSCON_REG_register85_SCFG_funcshare_pad_ctrl_53(_ezchip_macro_read_value_) { \
  985. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register85_REG_ADDR); \
  986. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  987. }
  988. #define _SET_SYSCON_REG_register86_SCFG_funcshare_pad_ctrl_54(v) { \
  989. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register86_REG_ADDR); \
  990. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  991. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  992. MA_OUTW(syscon_iopad_ctrl_register86_REG_ADDR,_ezchip_macro_read_value_); \
  993. }
  994. #define _GET_SYSCON_REG_register86_SCFG_funcshare_pad_ctrl_54(_ezchip_macro_read_value_) { \
  995. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register86_REG_ADDR); \
  996. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  997. }
  998. #define _SET_SYSCON_REG_register87_SCFG_funcshare_pad_ctrl_55(v) { \
  999. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register87_REG_ADDR); \
  1000. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1001. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1002. MA_OUTW(syscon_iopad_ctrl_register87_REG_ADDR,_ezchip_macro_read_value_); \
  1003. }
  1004. #define _GET_SYSCON_REG_register87_SCFG_funcshare_pad_ctrl_55(_ezchip_macro_read_value_) { \
  1005. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register87_REG_ADDR); \
  1006. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1007. }
  1008. #define _SET_SYSCON_REG_register88_SCFG_funcshare_pad_ctrl_56(v) { \
  1009. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register88_REG_ADDR); \
  1010. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1011. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1012. MA_OUTW(syscon_iopad_ctrl_register88_REG_ADDR,_ezchip_macro_read_value_); \
  1013. }
  1014. #define _GET_SYSCON_REG_register88_SCFG_funcshare_pad_ctrl_56(_ezchip_macro_read_value_) { \
  1015. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register88_REG_ADDR); \
  1016. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1017. }
  1018. #define _SET_SYSCON_REG_register89_SCFG_funcshare_pad_ctrl_57(v) { \
  1019. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register89_REG_ADDR); \
  1020. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1021. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1022. MA_OUTW(syscon_iopad_ctrl_register89_REG_ADDR,_ezchip_macro_read_value_); \
  1023. }
  1024. #define _GET_SYSCON_REG_register89_SCFG_funcshare_pad_ctrl_57(_ezchip_macro_read_value_) { \
  1025. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register89_REG_ADDR); \
  1026. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1027. }
  1028. #define _SET_SYSCON_REG_register90_SCFG_funcshare_pad_ctrl_58(v) { \
  1029. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register90_REG_ADDR); \
  1030. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1031. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1032. MA_OUTW(syscon_iopad_ctrl_register90_REG_ADDR,_ezchip_macro_read_value_); \
  1033. }
  1034. #define _GET_SYSCON_REG_register90_SCFG_funcshare_pad_ctrl_58(_ezchip_macro_read_value_) { \
  1035. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register90_REG_ADDR); \
  1036. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1037. }
  1038. #define _SET_SYSCON_REG_register91_SCFG_funcshare_pad_ctrl_59(v) { \
  1039. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register91_REG_ADDR); \
  1040. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1041. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1042. MA_OUTW(syscon_iopad_ctrl_register91_REG_ADDR,_ezchip_macro_read_value_); \
  1043. }
  1044. #define _GET_SYSCON_REG_register91_SCFG_funcshare_pad_ctrl_59(_ezchip_macro_read_value_) { \
  1045. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register91_REG_ADDR); \
  1046. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1047. }
  1048. #define _SET_SYSCON_REG_register92_SCFG_funcshare_pad_ctrl_60(v) { \
  1049. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register92_REG_ADDR); \
  1050. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1051. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1052. MA_OUTW(syscon_iopad_ctrl_register92_REG_ADDR,_ezchip_macro_read_value_); \
  1053. }
  1054. #define _GET_SYSCON_REG_register92_SCFG_funcshare_pad_ctrl_60(_ezchip_macro_read_value_) { \
  1055. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register92_REG_ADDR); \
  1056. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1057. }
  1058. #define _SET_SYSCON_REG_register93_SCFG_funcshare_pad_ctrl_61(v) { \
  1059. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register93_REG_ADDR); \
  1060. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1061. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1062. MA_OUTW(syscon_iopad_ctrl_register93_REG_ADDR,_ezchip_macro_read_value_); \
  1063. }
  1064. #define _GET_SYSCON_REG_register93_SCFG_funcshare_pad_ctrl_61(_ezchip_macro_read_value_) { \
  1065. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register93_REG_ADDR); \
  1066. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1067. }
  1068. #define _SET_SYSCON_REG_register94_SCFG_funcshare_pad_ctrl_62(v) { \
  1069. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register94_REG_ADDR); \
  1070. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1071. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1072. MA_OUTW(syscon_iopad_ctrl_register94_REG_ADDR,_ezchip_macro_read_value_); \
  1073. }
  1074. #define _GET_SYSCON_REG_register94_SCFG_funcshare_pad_ctrl_62(_ezchip_macro_read_value_) { \
  1075. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register94_REG_ADDR); \
  1076. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1077. }
  1078. #define _SET_SYSCON_REG_register95_SCFG_funcshare_pad_ctrl_63(v) { \
  1079. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register95_REG_ADDR); \
  1080. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1081. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1082. MA_OUTW(syscon_iopad_ctrl_register95_REG_ADDR,_ezchip_macro_read_value_); \
  1083. }
  1084. #define _GET_SYSCON_REG_register95_SCFG_funcshare_pad_ctrl_63(_ezchip_macro_read_value_) { \
  1085. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register95_REG_ADDR); \
  1086. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1087. }
  1088. #define _SET_SYSCON_REG_register96_SCFG_funcshare_pad_ctrl_64(v) { \
  1089. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register96_REG_ADDR); \
  1090. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1091. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1092. MA_OUTW(syscon_iopad_ctrl_register96_REG_ADDR,_ezchip_macro_read_value_); \
  1093. }
  1094. #define _GET_SYSCON_REG_register96_SCFG_funcshare_pad_ctrl_64(_ezchip_macro_read_value_) { \
  1095. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register96_REG_ADDR); \
  1096. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1097. }
  1098. #define _SET_SYSCON_REG_register97_SCFG_funcshare_pad_ctrl_65(v) { \
  1099. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register97_REG_ADDR); \
  1100. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1101. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1102. MA_OUTW(syscon_iopad_ctrl_register97_REG_ADDR,_ezchip_macro_read_value_); \
  1103. }
  1104. #define _GET_SYSCON_REG_register97_SCFG_funcshare_pad_ctrl_65(_ezchip_macro_read_value_) { \
  1105. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register97_REG_ADDR); \
  1106. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1107. }
  1108. #define _SET_SYSCON_REG_register98_SCFG_funcshare_pad_ctrl_66(v) { \
  1109. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register98_REG_ADDR); \
  1110. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1111. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1112. MA_OUTW(syscon_iopad_ctrl_register98_REG_ADDR,_ezchip_macro_read_value_); \
  1113. }
  1114. #define _GET_SYSCON_REG_register98_SCFG_funcshare_pad_ctrl_66(_ezchip_macro_read_value_) { \
  1115. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register98_REG_ADDR); \
  1116. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1117. }
  1118. #define _SET_SYSCON_REG_register99_SCFG_funcshare_pad_ctrl_67(v) { \
  1119. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register99_REG_ADDR); \
  1120. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1121. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1122. MA_OUTW(syscon_iopad_ctrl_register99_REG_ADDR,_ezchip_macro_read_value_); \
  1123. }
  1124. #define _GET_SYSCON_REG_register99_SCFG_funcshare_pad_ctrl_67(_ezchip_macro_read_value_) { \
  1125. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register99_REG_ADDR); \
  1126. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1127. }
  1128. #define _SET_SYSCON_REG_register100_SCFG_funcshare_pad_ctrl_68(v) { \
  1129. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register100_REG_ADDR); \
  1130. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1131. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1132. MA_OUTW(syscon_iopad_ctrl_register100_REG_ADDR,_ezchip_macro_read_value_); \
  1133. }
  1134. #define _GET_SYSCON_REG_register100_SCFG_funcshare_pad_ctrl_68(_ezchip_macro_read_value_) { \
  1135. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register100_REG_ADDR); \
  1136. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1137. }
  1138. #define _SET_SYSCON_REG_register101_SCFG_funcshare_pad_ctrl_69(v) { \
  1139. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register101_REG_ADDR); \
  1140. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1141. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1142. MA_OUTW(syscon_iopad_ctrl_register101_REG_ADDR,_ezchip_macro_read_value_); \
  1143. }
  1144. #define _GET_SYSCON_REG_register101_SCFG_funcshare_pad_ctrl_69(_ezchip_macro_read_value_) { \
  1145. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register101_REG_ADDR); \
  1146. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1147. }
  1148. #define _SET_SYSCON_REG_register102_SCFG_funcshare_pad_ctrl_70(v) { \
  1149. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register102_REG_ADDR); \
  1150. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1151. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1152. MA_OUTW(syscon_iopad_ctrl_register102_REG_ADDR,_ezchip_macro_read_value_); \
  1153. }
  1154. #define _GET_SYSCON_REG_register102_SCFG_funcshare_pad_ctrl_70(_ezchip_macro_read_value_) { \
  1155. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register102_REG_ADDR); \
  1156. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1157. }
  1158. #define _SET_SYSCON_REG_register103_SCFG_qspi_ioctrl(v) { \
  1159. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register103_REG_ADDR); \
  1160. _ezchip_macro_read_value_ &= ~(0x7F); \
  1161. _ezchip_macro_read_value_ |= (v&0x7F); \
  1162. MA_OUTW(syscon_iopad_ctrl_register103_REG_ADDR,_ezchip_macro_read_value_); \
  1163. }
  1164. #define _GET_SYSCON_REG_register103_SCFG_qspi_ioctrl(_ezchip_macro_read_value_) { \
  1165. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register103_REG_ADDR); \
  1166. _ezchip_macro_read_value_ &= 0x7f;\
  1167. }
  1168. #define _SET_SYSCON_REG_register104_SCFG_io_padshare_sel(v) { \
  1169. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register104_REG_ADDR); \
  1170. _ezchip_macro_read_value_ &= ~(0x7); \
  1171. _ezchip_macro_read_value_ |= (v&0x7); \
  1172. MA_OUTW(syscon_iopad_ctrl_register104_REG_ADDR,_ezchip_macro_read_value_); \
  1173. }
  1174. #define _GET_SYSCON_REG_register104_SCFG_io_padshare_sel(_ezchip_macro_read_value_) { \
  1175. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register104_REG_ADDR); \
  1176. _ezchip_macro_read_value_ &= 0x7;\
  1177. }
  1178. #endif //_SYSCON_IOPAD_CTRL_MACRO_H_