bootmain.c 4.9 KB

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  1. /**
  2. ******************************************************************************
  3. * @file bootmain.c
  4. * @author StarFive Technology
  5. * @version V1.0
  6. * @date 06/25/2020
  7. * @brief
  8. ******************************************************************************
  9. * @copy
  10. *
  11. * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  12. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  13. * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
  14. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  15. * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  16. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  17. *
  18. * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
  19. */
  20. #include "sys.h"
  21. #include "spi_flash.h"
  22. #include "spi.h"
  23. #include "encoding.h"
  24. #include <clkgen_ctrl_macro.h>
  25. #include <syscon_sysmain_ctrl_macro.h>
  26. #include <ezGPIO_fullMux_ctrl_macro.h>
  27. #include <rstgen_ctrl_macro.h>
  28. #include <syscon_iopad_ctrl_macro.h>
  29. typedef void ( *STARTRUNNING )( unsigned int par1 );
  30. /*
  31. To run a procedure from the address:start
  32. start: start address of runing in armmode, not do address align checking
  33. */
  34. void start2run32(unsigned int start)
  35. {
  36. (( STARTRUNNING )(start))(0);
  37. }
  38. #define SPIBOOT_LOAD_ADDR_OFFSET 252
  39. /*read data from flash to the destination address
  40. *
  41. *spi_flash: flash device informations
  42. *des_addr: store the data read from flash
  43. *page_offset:Offset of data stored in flash
  44. *mode:flash work mode
  45. */
  46. static int load_data(struct spi_flash* spi_flash,unsigned int des_addr,unsigned int page_offset,int mode)
  47. {
  48. u8 dataBuf[260];
  49. u32 startPage,endPage;
  50. u32 pageSize;
  51. u32 fileSize;
  52. u8 *addr;
  53. int ret;
  54. int i;
  55. u32 offset;
  56. pageSize = spi_flash->page_size;
  57. addr = (u8 *)des_addr;
  58. offset = page_offset*pageSize;
  59. /*read first page,get the file size*/
  60. ret = spi_flash->read(spi_flash,offset,pageSize,dataBuf,mode);
  61. if(ret != 0)
  62. {
  63. printk("read fail#\r\n");
  64. return -1;
  65. }
  66. /*calculate file size*/
  67. fileSize = (dataBuf[3] << 24) | (dataBuf[2] << 16) | (dataBuf[1] << 8) | (dataBuf[0]) ;
  68. if(fileSize == 0)
  69. return -1;
  70. endPage = ((fileSize + 255) >> 8);//page align
  71. /*copy the first page data*/
  72. sys_memcpy(addr, &dataBuf[4], SPIBOOT_LOAD_ADDR_OFFSET);
  73. offset += pageSize;
  74. addr += SPIBOOT_LOAD_ADDR_OFFSET;
  75. /*read Remaining pages data*/
  76. for(i=1; i<=endPage; i++)
  77. {
  78. ret = spi_flash->read(spi_flash,offset,pageSize, addr, mode);
  79. if(ret != 0)
  80. {
  81. printk("read fail##\r\n");
  82. return -1;
  83. }
  84. offset += pageSize;
  85. addr +=pageSize;
  86. }
  87. return 0;
  88. }
  89. void load_and_run_ddr(struct spi_flash* spi_flash,int mode)
  90. {
  91. unsigned int addr;
  92. int ret;
  93. addr = DEFAULT_DDR_ADDR;
  94. ret = load_data(spi_flash,addr,DEFAULT_DDR_OFFSET,mode);
  95. printk("\r\nbootloader version:%s\r\n",VERSION);
  96. if(!ret)
  97. {
  98. writel(0x1, 0x2000004);
  99. start2run32(addr);
  100. }
  101. else
  102. printk("\nload ddr bin fail.\n");
  103. /*never run to here*/
  104. while(1);
  105. }
  106. void boot_from_spi(int mode)
  107. {
  108. struct spi_flash* spi_flash;
  109. int ret;
  110. u32 *addr;
  111. u32 val;
  112. cadence_qspi_init(0, mode);
  113. spi_flash = spi_flash_probe(0, 0, 31250000, 0, (u32)SPI_DATAMODE_8);
  114. /*init ddr*/
  115. load_and_run_ddr(spi_flash,mode);
  116. }
  117. static void chip_clk_init()
  118. {
  119. _SWITCH_CLOCK_clk_cpundbus_root_SOURCE_clk_pll0_out_;
  120. _SWITCH_CLOCK_clk_dla_root_SOURCE_clk_pll1_out_;
  121. _SWITCH_CLOCK_clk_dsp_root_SOURCE_clk_pll2_out_;
  122. _SWITCH_CLOCK_clk_perh0_root_SOURCE_clk_pll0_out_;
  123. // slow down nne bus can fix nne50 & vp6 ram scan issue,
  124. // as well as vin_subsys reg scan issue.
  125. // _SWITCH_CLOCK_clk_nne_bus_SOURCE_clk_cpu_axi_;
  126. }
  127. /*only hartid 0 call this function*/
  128. void BootMain(void)
  129. {
  130. int boot_mode = 0;
  131. /*switch to pll mode*/
  132. chip_clk_init();
  133. //for illegal instruction exception
  134. _SET_SYSCON_REG_register50_SCFG_funcshare_pad_ctrl_18(0x00c000c0);
  135. _CLEAR_RESET_rstgen_rstn_usbnoc_axi_;
  136. _CLEAR_RESET_rstgen_rstn_hifi4noc_axi_;
  137. _ENABLE_CLOCK_clk_x2c_axi_;
  138. _CLEAR_RESET_rstgen_rstn_x2c_axi_;
  139. _CLEAR_RESET_rstgen_rstn_dspx2c_axi_;
  140. _CLEAR_RESET_rstgen_rstn_dma1p_axi_;
  141. _ENABLE_CLOCK_clk_msi_apb_;
  142. _CLEAR_RESET_rstgen_rstn_msi_apb_;
  143. _ASSERT_RESET_rstgen_rstn_x2c_axi_;
  144. _CLEAR_RESET_rstgen_rstn_x2c_axi_;
  145. //end for illegal instruction exception
  146. _SET_SYSCON_REG_register69_core1_en(1);
  147. _SET_SYSCON_REG_register104_SCFG_io_padshare_sel(6);
  148. _SET_SYSCON_REG_register32_SCFG_funcshare_pad_ctrl_0(0x00c00000);
  149. _SET_SYSCON_REG_register33_SCFG_funcshare_pad_ctrl_1(0x00c000c0);
  150. _SET_SYSCON_REG_register34_SCFG_funcshare_pad_ctrl_2(0x00c000c0);
  151. _SET_SYSCON_REG_register35_SCFG_funcshare_pad_ctrl_3(0x00c000c0);
  152. _SET_SYSCON_REG_register39_SCFG_funcshare_pad_ctrl_7(0x00c300c3);
  153. _SET_SYSCON_REG_register38_SCFG_funcshare_pad_ctrl_6(0x00c00000);
  154. uart_init(3);
  155. writel(0x18000000, 0x1801fffc);
  156. writel(0x1, 0x2000004); /*从bootrom中恢复hart1*/
  157. boot_from_spi(1);
  158. /*never run to heare*/
  159. }