start.S 2.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /**
  3. ******************************************************************************
  4. * @file start.S
  5. * @author StarFive Technology
  6. * @version V1.0
  7. * @date 06/25/2020
  8. * @brief
  9. ******************************************************************************
  10. * @copy
  11. *
  12. * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  13. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  14. * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
  15. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  16. * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  17. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  18. *
  19. * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
  20. */
  21. #include "encoding.h"
  22. #include "platform.h"
  23. #include "sys.h"
  24. /* This is defined in sifive/platform.h, but that can't be included from
  25. * assembly. */
  26. .section .init
  27. .globl _start
  28. _start:
  29. csrwi 0x7c1, 0
  30. la t0, trap_entry
  31. csrw mtvec, t0
  32. csrwi mstatus, 0
  33. csrwi mie, 0
  34. // Allocate 4 KiB stack for each hart
  35. csrr t0, mhartid
  36. slli t0, t0, 12
  37. la sp, _sp
  38. sub sp, sp, t0
  39. li a1, NONSMP_HART;
  40. csrr a0, mhartid;
  41. bne a0, a1, .LbootOtherHart //other hart
  42. // Load data section
  43. la t0, _data_lma
  44. la t1, _data
  45. beq t0, t1, 2f
  46. la t2, _edata
  47. bgeu t1, t2, 2f
  48. 1:
  49. ld t3, 0(t0)
  50. sd t3, 0(t1)
  51. addi t0, t0, 8
  52. addi t1, t1, 8
  53. bltu t1, t2, 1b
  54. 2:
  55. /* Clear bss section */
  56. la t1, _bss_start
  57. la t2, _bss_end
  58. bgeu t1, t2, 4f
  59. 3:
  60. sd x0, 0(t1)
  61. addi t1, t1, 8
  62. blt t1, t2, 3b
  63. 4:
  64. /*only hart 0*/
  65. call BootMain
  66. j .enter_uboot
  67. .LbootOtherHart:
  68. li s1, CLINT_CTRL_ADDR
  69. csrr a0, mhartid
  70. slli s2, a0, 2
  71. add s2, s2, s1
  72. sw zero, 0(s2)
  73. fence
  74. csrw mip, 0
  75. # core 1 jumps to main_other_hart
  76. # Set MSIE bit to receive IPI
  77. li a2, MIP_MSIP
  78. csrw mie, a2
  79. .LwaitOtherHart:
  80. # Wait for an IPI to signal that its safe to boot
  81. // call second_hart
  82. wfi
  83. # Only start if MIP_MSIP is set
  84. csrr a2, mip
  85. andi a2, a2, MIP_MSIP
  86. beqz a2, .LwaitOtherHart
  87. li s1, CLINT_CTRL_ADDR
  88. csrr a0, mhartid
  89. slli s2, a0, 2
  90. add s2, s2, s1
  91. sw zero, 0(s2)
  92. fence
  93. csrw mip, 0
  94. li a2, NUM_CORES
  95. bltu a0, a2, .enter_uboot
  96. j .LwaitOtherHart
  97. .enter_uboot:
  98. li t0, DEFAULT_DDR_ADDR
  99. csrr a0, mhartid
  100. la a1, 0
  101. jr t0