spi_flash.c 12 KB

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  1. #include <comdef.h>
  2. #include "spi.h"
  3. #include "spi_flash.h"
  4. #include "spi_flash_internal.h"
  5. #include <cadence_qspi.h>
  6. static void spi_flash_addr(u32 addr, u8 *cmd)
  7. {
  8. /* cmd[0] is actual command */
  9. cmd[1] = (addr & 0x00FF0000) >> 16;
  10. cmd[2] = (addr & 0x0000FF00) >> 8;
  11. cmd[3] = (addr & 0x000000FF) >> 0;
  12. }
  13. static int spi_flash_read_write(struct spi_slave *spi,
  14. u8 *cmd, u32 cmd_len,
  15. u8 *data_out, u8 *data_in,
  16. u32 data_len)
  17. {
  18. unsigned long flags = SPI_XFER_BEGIN;
  19. int ret;
  20. if (data_len == 0)
  21. flags |= SPI_XFER_END;
  22. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  23. if (ret)
  24. {
  25. //uart_printf("SF: Failed to send command (%d bytes): %d\n",
  26. //cmd_len, ret);
  27. }
  28. else if (data_len != 0)
  29. {
  30. ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END, SPI_DATAMODE_8);
  31. }
  32. return ret;
  33. }
  34. int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, u32 len)
  35. {
  36. return spi_flash_cmd_read(spi, &cmd, 1, response, len);
  37. }
  38. int spi_flash_cmd_read(struct spi_slave *spi, u8 *cmd,
  39. u32 cmd_len, void *data, u32 data_len)
  40. {
  41. return spi_flash_read_write(spi, cmd, cmd_len, NULL, data, data_len);
  42. }
  43. int spi_flash_cmd_write(struct spi_slave *spi, u8 *cmd, u32 cmd_len,
  44. void *data, u32 data_len)
  45. {
  46. return spi_flash_read_write(spi, cmd, cmd_len, data, NULL, data_len);
  47. }
  48. int spi_flash_cmd_write_enable(struct spi_flash *flash)
  49. {
  50. return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, (void*)NULL, 0);
  51. }
  52. int spi_flash_cmd_write_status_enable(struct spi_flash *flash)
  53. {
  54. return spi_flash_cmd(flash->spi, CMD_STATUS_ENABLE, (void*)NULL, 0);
  55. }
  56. int spi_flash_cmd_write_disable(struct spi_slave *spi)
  57. {
  58. return spi_flash_cmd(spi, CMD_WRITE_DISABLE, (void*)NULL, 0);
  59. }
  60. int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *cmd, u32 cmd_len, u8 *status)
  61. {
  62. struct spi_slave *spi = flash->spi;
  63. int ret;
  64. ret = spi_xfer(spi, 8*cmd_len, cmd, NULL, SPI_XFER_BEGIN, SPI_DATAMODE_8);
  65. if (ret) {
  66. //uart_printf("SF: Failed to send command %x: %d\n", (unsigned int)cmd, ret);
  67. return ret;
  68. }
  69. ret = spi_xfer(spi, 8*1, NULL, status, SPI_XFER_END, SPI_DATAMODE_8);
  70. //uart_printf("status = 0x%x\r\n", status[0]);
  71. if (ret)
  72. return ret;
  73. return 0;
  74. }
  75. int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout,
  76. u8 cmd, u8 poll_bit)
  77. {
  78. int ret;
  79. u8 status;
  80. u32 status_tmp = 0;
  81. u32 timebase_1 = 0;
  82. do {
  83. ret = spi_flash_cmd_read_status(flash, &cmd, 1, &status);
  84. //uart_printf("cmd = 0x%x, status = 0x%x\r\n", cmd, status);
  85. if (ret)
  86. return ret;
  87. if ((status & poll_bit) == 0)
  88. break;
  89. timebase_1++;//libo
  90. } while (timebase_1 < timeout);
  91. if ((status & poll_bit) == 0)
  92. return 0;
  93. /* Timed out */
  94. //uart_printf("SF: time out!\r\n");
  95. return -1;
  96. }
  97. int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
  98. {
  99. return spi_flash_cmd_poll_bit(flash, timeout,
  100. CMD_READ_STATUS, STATUS_WIP);
  101. }
  102. int spi_flash_cmd_poll_enable(struct spi_flash *flash, unsigned long timeout,
  103. u8 cmd, u32 poll_bit)
  104. {
  105. int ret;
  106. u8 status;
  107. u32 status_tmp = 0;
  108. u32 timebase_1 = 0;
  109. do {
  110. ret = spi_flash_cmd_read_status(flash, &cmd, 1, &status);
  111. if (ret)
  112. return ret;
  113. //uart_printf("read status = 0x%x\r\n", status);
  114. if ((status & poll_bit) == 1)
  115. break;
  116. timebase_1++;
  117. } while (timebase_1 < timeout);
  118. /* Timed out */
  119. //uart_printf("SF: time out!\r\n");
  120. return 0;
  121. }
  122. int spi_flash_cmd_status_poll_enable(struct spi_flash *flash, unsigned long timeout,
  123. u8 cmd, u32 poll_bit)
  124. {
  125. int ret;
  126. u8 status;
  127. u32 status_tmp = 0;
  128. u32 timebase_1 = 0;
  129. do {
  130. ret = spi_flash_cmd_read_status(flash, &cmd, 1, &status);
  131. if (ret)
  132. return ret;
  133. //uart_printf("read status = 0x%x\r\n", status);
  134. if ((status & poll_bit) == 0x2)
  135. break;
  136. timebase_1++;
  137. } while (timebase_1 < timeout);
  138. /* Timed out */
  139. //uart_printf("SF: time out!\r\n");
  140. return 0;
  141. }
  142. int spi_flash_cmd_wait_enable(struct spi_flash *flash, unsigned long timeout)
  143. {
  144. return spi_flash_cmd_status_poll_enable(flash, timeout,
  145. CMD_READ_STATUS, FLASH_ENABLE);
  146. }
  147. int spi_flash_write_status(struct spi_flash *flash, u8 *cmd, unsigned int cmd_len,void *data, unsigned int data_len)
  148. {
  149. int ret;
  150. ret = spi_flash_cmd_write_enable(flash);
  151. if (ret) {
  152. // uart_printf("SF: Unable to claim SPI bus\n");
  153. return ret;
  154. }
  155. ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, data, data_len);
  156. if (ret < 0) {
  157. //uart_printf("SF: write failed\n");
  158. return ret;
  159. }
  160. ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
  161. if (ret < 0) {
  162. //uart_printf("SF: wait ready failed\n");
  163. return ret;
  164. }
  165. ret = spi_flash_cmd_write_disable(flash->spi);
  166. if (ret < 0) {
  167. //uart_printf("SF: disable write failed\n");
  168. return ret;
  169. }
  170. return 0;
  171. }
  172. #ifdef ISP_BOARD
  173. int spi_flash_write_status_bit(struct spi_flash *flash, u8 status0, u8 bit0)
  174. {
  175. u8 status[2];
  176. int ret = 0;
  177. status[0] = CMD_WRITE_STATUS;
  178. status[1] = status0|bit0;
  179. spi_flash_write_status(flash, &status[0], 1, &status[1], 1);
  180. if (bit0)
  181. {
  182. ret &= spi_flash_cmd_poll_bit(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT, CMD_READ_STATUS, ~bit0);
  183. }
  184. return ret;
  185. delay(1000);
  186. return ret;
  187. }
  188. int spi_flash_protect(struct spi_flash *flash)
  189. {
  190. /* set PB=0 all can write */
  191. return spi_flash_write_status_bit(flash, 0x00, 0);
  192. }
  193. #else
  194. int spi_flash_write_status_bit(struct spi_flash *flash, u8 status1, u8 status2, u8 bit1, u8 bit2)
  195. {
  196. u8 status[3];
  197. int ret = 0;
  198. status[0] = CMD_WRITE_STATUS;
  199. status[1] = status1|bit1;
  200. status[2] = status2|bit2;
  201. spi_flash_write_status(flash, &status[0], 1, &status[1], 2);
  202. if (bit1)
  203. {
  204. ret &= spi_flash_cmd_poll_bit(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT, CMD_READ_STATUS, ~bit1);
  205. }
  206. if (bit2)
  207. {
  208. ret &= spi_flash_cmd_poll_bit(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT, CMD_READ_STATUS1, ~bit2);
  209. }
  210. return ret;
  211. delay(1000);
  212. return ret;
  213. }
  214. int spi_flash_protect(struct spi_flash *flash)
  215. {
  216. /* set PB=0 all can write */
  217. return spi_flash_write_status_bit(flash, 0x00, 0x00, 0, 0);
  218. }
  219. #endif
  220. int spi_flash_cmd_erase(struct spi_flash *flash, u8 erase_cmd,
  221. u32 offset, u32 len)
  222. {
  223. u32 start, end, erase_size;
  224. int ret;
  225. u8 cmd[4];
  226. //uart_printf("spi_flash_cmd_erase \r\n");
  227. switch(erase_cmd){
  228. case CMD_W25_SE:
  229. erase_size = flash->sector_size;
  230. break;
  231. case CMD_W25_BE_32:
  232. erase_size = flash->sector_size * 8;
  233. break;
  234. case CMD_W25_BE:
  235. erase_size = flash->block_size;
  236. break;
  237. default:
  238. erase_size = flash->sector_size;
  239. break;
  240. }
  241. if (offset % erase_size || len % erase_size) {
  242. //uart_printf("SF: Erase offset/length not multiple of erase size\n");
  243. return -1;
  244. }
  245. // spi_flash_cmd_write_status_enable(flash);
  246. spi_flash_protect(flash);
  247. cmd[0] = erase_cmd;
  248. start = offset;
  249. end = start + len;
  250. while (offset < end)
  251. {
  252. spi_flash_addr(offset, cmd);
  253. offset += erase_size;
  254. //uart_printf("SF: erase %x %x %x %x (%x)\n", cmd[0], cmd[1],
  255. // cmd[2], cmd[3], offset);
  256. ret = spi_flash_cmd_write_enable(flash);
  257. if (ret)
  258. goto out;
  259. //spi_flash_cmd_wait_enable(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
  260. ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), NULL, 0);
  261. if (ret)
  262. goto out;
  263. ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
  264. if (ret)
  265. goto out;
  266. ret = spi_flash_cmd_write_disable(flash->spi);
  267. if (ret)
  268. goto out;
  269. }
  270. //uart_printf("SF: Successfully erased %d bytes @ %x\n", len , start);
  271. out:
  272. return ret;
  273. }
  274. /* mode is 4, 32, 64*/
  275. int spi_flash_erase_mode(struct spi_flash *flash, u32 offset, u32 len, u32 mode)
  276. {
  277. int ret = 0;
  278. switch (mode)
  279. {
  280. case 4:
  281. ret = spi_flash_cmd_erase(flash, CMD_W25_SE, offset, len);
  282. break;
  283. case 32:
  284. ret = spi_flash_cmd_erase(flash, CMD_W25_BE_32, offset, len);
  285. break;
  286. case 64:
  287. ret = spi_flash_cmd_erase(flash, CMD_W25_BE, offset, len);
  288. break;
  289. default:
  290. ret = spi_flash_cmd_erase(flash, CMD_W25_BE, offset, len);
  291. break;
  292. }
  293. return ret;
  294. }
  295. int spi_flash_cmd_write_mode(struct spi_flash *flash, u32 offset,u32 len, void *buf, u32 mode)
  296. {
  297. struct spi_slave *spi = flash->spi;
  298. unsigned long byte_addr, page_size;
  299. u32 write_addr;
  300. u32 chunk_len, actual;
  301. int ret;
  302. u8 cmd[4];
  303. int write_data = 1;
  304. unsigned long flags = SPI_XFER_BEGIN;
  305. page_size = flash->page_size;
  306. switch (mode){
  307. case 1:
  308. cmd[0] = CMD_PAGE_PROGRAM;
  309. break;
  310. case 4:
  311. cmd[0] = CMD_PAGE_PROGRAM_QUAD;
  312. #ifdef ISP_BOARD
  313. spi_flash_write_status_bit(flash, 0x00, STATUS_QE);
  314. #else
  315. spi_flash_write_status_bit(flash, 0x00, 0x00, 0, STATUS_QE);
  316. #endif
  317. break;
  318. default:
  319. cmd[0] = CMD_PAGE_PROGRAM;
  320. break;
  321. }
  322. for (actual = 0; actual < len; actual += chunk_len)
  323. {
  324. write_addr = offset;
  325. byte_addr = offset % page_size;
  326. chunk_len = min(len - actual, page_size - byte_addr);
  327. spi_flash_addr(write_addr, cmd);
  328. ret = spi_flash_cmd_write_enable(flash);
  329. if (ret < 0) {
  330. //uart_printf("SF: enabling write failed\n");
  331. break;
  332. }
  333. spi_flash_cmd_wait_enable(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
  334. #if 1
  335. if (mode == 1)
  336. {
  337. ret = spi_flash_cmd_write(flash->spi, cmd, 4,
  338. (unsigned char*)buf + actual, chunk_len);
  339. if (ret < 0) {
  340. //uart_printf("SF: write failed\n");
  341. break;
  342. }
  343. }
  344. #endif
  345. if (mode == 4)
  346. {
  347. flags = SPI_XFER_BEGIN;
  348. if (chunk_len == 0)
  349. flags |= SPI_XFER_END;
  350. ret = spi_xfer(spi, 4 * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  351. if (ret < 0)
  352. {
  353. //uart_printf("xfer failed\n");
  354. return ret;
  355. }
  356. else if (chunk_len != 0)
  357. {
  358. //qspi_mode_ctl(SPI4_DATEMODE_4);
  359. ret = spi_xfer(spi, chunk_len * 8, (unsigned char*)buf + actual, NULL, SPI_XFER_END, SPI_DATAMODE_8);
  360. }
  361. }
  362. //qspi_mode_ctl(SPI4_DATEMODE_0);
  363. ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
  364. if (ret < 0)
  365. {
  366. //uart_printf("SF: spi_flash_cmd_wait_ready failed\n");
  367. break;
  368. }
  369. ret = spi_flash_cmd_write_disable(flash->spi);
  370. if (ret < 0)
  371. {
  372. //uart_printf("SF: disable write failed\n");
  373. break;
  374. }
  375. offset += chunk_len;
  376. //uart_printf("SF: program %s %d bytes @ %d\n", ret ? "failure" : "success", len, offset);
  377. }
  378. return ret;
  379. }
  380. int spi_flash_read_common(struct spi_flash *flash, u8 *cmd,
  381. u32 cmd_len, void *data, u32 data_len)
  382. {
  383. struct spi_slave *spi = flash->spi;
  384. int ret;
  385. ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
  386. return ret;
  387. }
  388. int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
  389. u32 len, void *data, u32 mode)
  390. {
  391. u8 cmd[5];
  392. cmd[0] = CMD_READ_ARRAY_FAST;
  393. spi_flash_addr(offset, cmd);
  394. cmd[4] = 0x00;
  395. return spi_flash_read_common(flash, cmd, sizeof(cmd), data, len);
  396. }
  397. int spi_flash_read_mode(struct spi_flash *flash, u32 offset,
  398. u32 len, void *data, u32 mode)
  399. {
  400. struct spi_slave *spi = flash->spi;
  401. u8 cmd[5];
  402. int ret;
  403. int write_data = 0;
  404. u8 status[2] = {2};
  405. int i = 0;
  406. switch (mode)
  407. {
  408. case 1:
  409. cmd[0] = CMD_READ_ARRAY_FAST;
  410. break;
  411. case 2:
  412. cmd[0] = CMD_READ_ARRAY_DUAL;
  413. break;
  414. case 4:
  415. #ifdef ISP_BOARD
  416. cmd[0] = CMD_READ_ARRAY_LEGACY;
  417. //spi_flash_cmd_write_reg_mode(flash, flash_reg_offset, 1, flash_reg);
  418. //flash_reg[0] = 0;
  419. //spi_flash_cmd_write_reg_mode(flash, flash_reg_offset, 1, flash_reg);
  420. //spi_flash_read_reg_mode(flash, flash_reg_offset, 1, flash_reg);
  421. #else
  422. cmd[0] = CMD_READ_ARRAY_QUAD;
  423. spi_flash_write_status_bit(flash, 0x00, 0x00, 0, STATUS_QE);
  424. #endif
  425. break;
  426. default:
  427. cmd[0] = CMD_READ_ARRAY_FAST;
  428. break;
  429. }
  430. //spi_flash_cmd_poll_bit(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT, CMD_READ_STATUS1, ~STATUS_QE);
  431. spi_flash_addr(offset, cmd);
  432. cmd[4] = 0x00;
  433. ret = spi_xfer(spi, 5*8, cmd, NULL, SPI_XFER_BEGIN, SPI_DATAMODE_8);
  434. if (ret < 0)
  435. {
  436. //uart_printf("xfer failed\n");
  437. return ret;
  438. }
  439. ret = spi_xfer(spi, len*8, NULL, data, SPI_XFER_END, SPI_DATAMODE_8);
  440. if (ret < 0)
  441. {
  442. //uart_printf("xfer failed\n");
  443. return ret;
  444. }
  445. return 0;
  446. }