syscon_iopad_ctrl_macro.h 64 KB

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  1. /******************************************************************
  2. *
  3. * syscon_iopad_ctrl_top C MACRO generated by ezchip
  4. *
  5. ******************************************************************/
  6. #ifndef _SYSCON_IOPAD_CTRL_MACRO_H_
  7. #define _SYSCON_IOPAD_CTRL_MACRO_H_
  8. //#define SYSCON_IOPAD_CTRL_BASE_ADDR 0x0
  9. #define syscon_iopad_ctrl_register0_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x0
  10. #define syscon_iopad_ctrl_register1_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x4
  11. #define syscon_iopad_ctrl_register2_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x8
  12. #define syscon_iopad_ctrl_register3_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xC
  13. #define syscon_iopad_ctrl_register4_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x10
  14. #define syscon_iopad_ctrl_register5_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x14
  15. #define syscon_iopad_ctrl_register6_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x18
  16. #define syscon_iopad_ctrl_register7_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x1C
  17. #define syscon_iopad_ctrl_register8_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x20
  18. #define syscon_iopad_ctrl_register9_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x24
  19. #define syscon_iopad_ctrl_register10_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x28
  20. #define syscon_iopad_ctrl_register11_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x2C
  21. #define syscon_iopad_ctrl_register12_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x30
  22. #define syscon_iopad_ctrl_register13_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x34
  23. #define syscon_iopad_ctrl_register14_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x38
  24. #define syscon_iopad_ctrl_register15_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x3C
  25. #define syscon_iopad_ctrl_register16_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x40
  26. #define syscon_iopad_ctrl_register17_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x44
  27. #define syscon_iopad_ctrl_register18_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x48
  28. #define syscon_iopad_ctrl_register19_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x4C
  29. #define syscon_iopad_ctrl_register20_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x50
  30. #define syscon_iopad_ctrl_register21_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x54
  31. #define syscon_iopad_ctrl_register22_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x58
  32. #define syscon_iopad_ctrl_register23_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x5C
  33. #define syscon_iopad_ctrl_register24_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x60
  34. #define syscon_iopad_ctrl_register25_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x64
  35. #define syscon_iopad_ctrl_register26_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x68
  36. #define syscon_iopad_ctrl_register27_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x6C
  37. #define syscon_iopad_ctrl_register28_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x70
  38. #define syscon_iopad_ctrl_register29_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x74
  39. #define syscon_iopad_ctrl_register30_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x78
  40. #define syscon_iopad_ctrl_register31_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x7C
  41. #define syscon_iopad_ctrl_register32_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x80
  42. #define syscon_iopad_ctrl_register33_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x84
  43. #define syscon_iopad_ctrl_register34_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x88
  44. #define syscon_iopad_ctrl_register35_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x8C
  45. #define syscon_iopad_ctrl_register36_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x90
  46. #define syscon_iopad_ctrl_register37_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x94
  47. #define syscon_iopad_ctrl_register38_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x98
  48. #define syscon_iopad_ctrl_register39_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x9C
  49. #define syscon_iopad_ctrl_register40_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xA0
  50. #define syscon_iopad_ctrl_register41_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xA4
  51. #define syscon_iopad_ctrl_register42_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xA8
  52. #define syscon_iopad_ctrl_register43_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xAC
  53. #define syscon_iopad_ctrl_register44_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xB0
  54. #define syscon_iopad_ctrl_register45_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xB4
  55. #define syscon_iopad_ctrl_register46_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xB8
  56. #define syscon_iopad_ctrl_register47_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xBC
  57. #define syscon_iopad_ctrl_register48_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xC0
  58. #define syscon_iopad_ctrl_register49_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xC4
  59. #define syscon_iopad_ctrl_register50_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xC8
  60. #define syscon_iopad_ctrl_register51_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xCC
  61. #define syscon_iopad_ctrl_register52_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xD0
  62. #define syscon_iopad_ctrl_register53_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xD4
  63. #define syscon_iopad_ctrl_register54_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xD8
  64. #define syscon_iopad_ctrl_register55_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xDC
  65. #define syscon_iopad_ctrl_register56_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xE0
  66. #define syscon_iopad_ctrl_register57_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xE4
  67. #define syscon_iopad_ctrl_register58_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xE8
  68. #define syscon_iopad_ctrl_register59_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xEC
  69. #define syscon_iopad_ctrl_register60_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xF0
  70. #define syscon_iopad_ctrl_register61_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xF4
  71. #define syscon_iopad_ctrl_register62_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xF8
  72. #define syscon_iopad_ctrl_register63_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0xFC
  73. #define syscon_iopad_ctrl_register64_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x100
  74. #define syscon_iopad_ctrl_register65_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x104
  75. #define syscon_iopad_ctrl_register66_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x108
  76. #define syscon_iopad_ctrl_register67_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x10C
  77. #define syscon_iopad_ctrl_register68_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x110
  78. #define syscon_iopad_ctrl_register69_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x114
  79. #define syscon_iopad_ctrl_register70_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x118
  80. #define syscon_iopad_ctrl_register71_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x11C
  81. #define syscon_iopad_ctrl_register72_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x120
  82. #define syscon_iopad_ctrl_register73_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x124
  83. #define syscon_iopad_ctrl_register74_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x128
  84. #define syscon_iopad_ctrl_register75_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x12C
  85. #define syscon_iopad_ctrl_register76_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x130
  86. #define syscon_iopad_ctrl_register77_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x134
  87. #define syscon_iopad_ctrl_register78_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x138
  88. #define syscon_iopad_ctrl_register79_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x13C
  89. #define syscon_iopad_ctrl_register80_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x140
  90. #define syscon_iopad_ctrl_register81_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x144
  91. #define syscon_iopad_ctrl_register82_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x148
  92. #define syscon_iopad_ctrl_register83_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x14C
  93. #define syscon_iopad_ctrl_register84_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x150
  94. #define syscon_iopad_ctrl_register85_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x154
  95. #define syscon_iopad_ctrl_register86_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x158
  96. #define syscon_iopad_ctrl_register87_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x15C
  97. #define syscon_iopad_ctrl_register88_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x160
  98. #define syscon_iopad_ctrl_register89_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x164
  99. #define syscon_iopad_ctrl_register90_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x168
  100. #define syscon_iopad_ctrl_register91_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x16C
  101. #define syscon_iopad_ctrl_register92_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x170
  102. #define syscon_iopad_ctrl_register93_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x174
  103. #define syscon_iopad_ctrl_register94_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x178
  104. #define syscon_iopad_ctrl_register95_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x17C
  105. #define syscon_iopad_ctrl_register96_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x180
  106. #define syscon_iopad_ctrl_register97_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x184
  107. #define syscon_iopad_ctrl_register98_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x188
  108. #define syscon_iopad_ctrl_register99_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x18C
  109. #define syscon_iopad_ctrl_register100_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x190
  110. #define syscon_iopad_ctrl_register101_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x194
  111. #define syscon_iopad_ctrl_register102_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x198
  112. #define syscon_iopad_ctrl_register103_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x19C
  113. #define syscon_iopad_ctrl_register104_REG_ADDR SYSCON_IOPAD_CTRL_BASE_ADDR + 0x1A0
  114. #define _SET_SYSCON_REG_register0_SCFG_gpio_pad_ctrl_0(v) { \
  115. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register0_REG_ADDR); \
  116. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  117. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  118. MA_OUTW(syscon_iopad_ctrl_register0_REG_ADDR,_ezchip_macro_read_value_); \
  119. }
  120. #define _GET_SYSCON_REG_register0_SCFG_gpio_pad_ctrl_0(_ezchip_macro_read_value_) { \
  121. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register0_REG_ADDR); \
  122. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  123. }
  124. #define _SET_SYSCON_REG_register1_SCFG_gpio_pad_ctrl_1(v) { \
  125. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register1_REG_ADDR); \
  126. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  127. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  128. MA_OUTW(syscon_iopad_ctrl_register1_REG_ADDR,_ezchip_macro_read_value_); \
  129. }
  130. #define _GET_SYSCON_REG_register1_SCFG_gpio_pad_ctrl_1(_ezchip_macro_read_value_) { \
  131. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register1_REG_ADDR); \
  132. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  133. }
  134. #define _SET_SYSCON_REG_register2_SCFG_gpio_pad_ctrl_2(v) { \
  135. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register2_REG_ADDR); \
  136. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  137. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  138. MA_OUTW(syscon_iopad_ctrl_register2_REG_ADDR,_ezchip_macro_read_value_); \
  139. }
  140. #define _GET_SYSCON_REG_register2_SCFG_gpio_pad_ctrl_2(_ezchip_macro_read_value_) { \
  141. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register2_REG_ADDR); \
  142. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  143. }
  144. #define _SET_SYSCON_REG_register3_SCFG_gpio_pad_ctrl_3(v) { \
  145. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register3_REG_ADDR); \
  146. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  147. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  148. MA_OUTW(syscon_iopad_ctrl_register3_REG_ADDR,_ezchip_macro_read_value_); \
  149. }
  150. #define _GET_SYSCON_REG_register3_SCFG_gpio_pad_ctrl_3(_ezchip_macro_read_value_) { \
  151. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register3_REG_ADDR); \
  152. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  153. }
  154. #define _SET_SYSCON_REG_register4_SCFG_gpio_pad_ctrl_4(v) { \
  155. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register4_REG_ADDR); \
  156. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  157. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  158. MA_OUTW(syscon_iopad_ctrl_register4_REG_ADDR,_ezchip_macro_read_value_); \
  159. }
  160. #define _GET_SYSCON_REG_register4_SCFG_gpio_pad_ctrl_4(_ezchip_macro_read_value_) { \
  161. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register4_REG_ADDR); \
  162. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  163. }
  164. #define _SET_SYSCON_REG_register5_SCFG_gpio_pad_ctrl_5(v) { \
  165. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register5_REG_ADDR); \
  166. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  167. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  168. MA_OUTW(syscon_iopad_ctrl_register5_REG_ADDR,_ezchip_macro_read_value_); \
  169. }
  170. #define _GET_SYSCON_REG_register5_SCFG_gpio_pad_ctrl_5(_ezchip_macro_read_value_) { \
  171. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register5_REG_ADDR); \
  172. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  173. }
  174. #define _SET_SYSCON_REG_register6_SCFG_gpio_pad_ctrl_6(v) { \
  175. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register6_REG_ADDR); \
  176. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  177. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  178. MA_OUTW(syscon_iopad_ctrl_register6_REG_ADDR,_ezchip_macro_read_value_); \
  179. }
  180. #define _GET_SYSCON_REG_register6_SCFG_gpio_pad_ctrl_6(_ezchip_macro_read_value_) { \
  181. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register6_REG_ADDR); \
  182. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  183. }
  184. #define _SET_SYSCON_REG_register7_SCFG_gpio_pad_ctrl_7(v) { \
  185. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register7_REG_ADDR); \
  186. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  187. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  188. MA_OUTW(syscon_iopad_ctrl_register7_REG_ADDR,_ezchip_macro_read_value_); \
  189. }
  190. #define _GET_SYSCON_REG_register7_SCFG_gpio_pad_ctrl_7(_ezchip_macro_read_value_) { \
  191. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register7_REG_ADDR); \
  192. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  193. }
  194. #define _SET_SYSCON_REG_register8_SCFG_gpio_pad_ctrl_8(v) { \
  195. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register8_REG_ADDR); \
  196. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  197. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  198. MA_OUTW(syscon_iopad_ctrl_register8_REG_ADDR,_ezchip_macro_read_value_); \
  199. }
  200. #define _GET_SYSCON_REG_register8_SCFG_gpio_pad_ctrl_8(_ezchip_macro_read_value_) { \
  201. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register8_REG_ADDR); \
  202. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  203. }
  204. #define _SET_SYSCON_REG_register9_SCFG_gpio_pad_ctrl_9(v) { \
  205. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register9_REG_ADDR); \
  206. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  207. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  208. MA_OUTW(syscon_iopad_ctrl_register9_REG_ADDR,_ezchip_macro_read_value_); \
  209. }
  210. #define _GET_SYSCON_REG_register9_SCFG_gpio_pad_ctrl_9(_ezchip_macro_read_value_) { \
  211. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register9_REG_ADDR); \
  212. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  213. }
  214. #define _SET_SYSCON_REG_register10_SCFG_gpio_pad_ctrl_10(v) { \
  215. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register10_REG_ADDR); \
  216. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  217. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  218. MA_OUTW(syscon_iopad_ctrl_register10_REG_ADDR,_ezchip_macro_read_value_); \
  219. }
  220. #define _GET_SYSCON_REG_register10_SCFG_gpio_pad_ctrl_10(_ezchip_macro_read_value_) { \
  221. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register10_REG_ADDR); \
  222. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  223. }
  224. #define _SET_SYSCON_REG_register11_SCFG_gpio_pad_ctrl_11(v) { \
  225. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register11_REG_ADDR); \
  226. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  227. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  228. MA_OUTW(syscon_iopad_ctrl_register11_REG_ADDR,_ezchip_macro_read_value_); \
  229. }
  230. #define _GET_SYSCON_REG_register11_SCFG_gpio_pad_ctrl_11(_ezchip_macro_read_value_) { \
  231. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register11_REG_ADDR); \
  232. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  233. }
  234. #define _SET_SYSCON_REG_register12_SCFG_gpio_pad_ctrl_12(v) { \
  235. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register12_REG_ADDR); \
  236. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  237. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  238. MA_OUTW(syscon_iopad_ctrl_register12_REG_ADDR,_ezchip_macro_read_value_); \
  239. }
  240. #define _GET_SYSCON_REG_register12_SCFG_gpio_pad_ctrl_12(_ezchip_macro_read_value_) { \
  241. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register12_REG_ADDR); \
  242. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  243. }
  244. #define _SET_SYSCON_REG_register13_SCFG_gpio_pad_ctrl_13(v) { \
  245. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register13_REG_ADDR); \
  246. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  247. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  248. MA_OUTW(syscon_iopad_ctrl_register13_REG_ADDR,_ezchip_macro_read_value_); \
  249. }
  250. #define _GET_SYSCON_REG_register13_SCFG_gpio_pad_ctrl_13(_ezchip_macro_read_value_) { \
  251. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register13_REG_ADDR); \
  252. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  253. }
  254. #define _SET_SYSCON_REG_register14_SCFG_gpio_pad_ctrl_14(v) { \
  255. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register14_REG_ADDR); \
  256. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  257. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  258. MA_OUTW(syscon_iopad_ctrl_register14_REG_ADDR,_ezchip_macro_read_value_); \
  259. }
  260. #define _GET_SYSCON_REG_register14_SCFG_gpio_pad_ctrl_14(_ezchip_macro_read_value_) { \
  261. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register14_REG_ADDR); \
  262. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  263. }
  264. #define _SET_SYSCON_REG_register15_SCFG_gpio_pad_ctrl_15(v) { \
  265. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register15_REG_ADDR); \
  266. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  267. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  268. MA_OUTW(syscon_iopad_ctrl_register15_REG_ADDR,_ezchip_macro_read_value_); \
  269. }
  270. #define _GET_SYSCON_REG_register15_SCFG_gpio_pad_ctrl_15(_ezchip_macro_read_value_) { \
  271. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register15_REG_ADDR); \
  272. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  273. }
  274. #define _SET_SYSCON_REG_register16_SCFG_gpio_pad_ctrl_16(v) { \
  275. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register16_REG_ADDR); \
  276. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  277. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  278. MA_OUTW(syscon_iopad_ctrl_register16_REG_ADDR,_ezchip_macro_read_value_); \
  279. }
  280. #define _GET_SYSCON_REG_register16_SCFG_gpio_pad_ctrl_16(_ezchip_macro_read_value_) { \
  281. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register16_REG_ADDR); \
  282. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  283. }
  284. #define _SET_SYSCON_REG_register17_SCFG_gpio_pad_ctrl_17(v) { \
  285. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register17_REG_ADDR); \
  286. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  287. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  288. MA_OUTW(syscon_iopad_ctrl_register17_REG_ADDR,_ezchip_macro_read_value_); \
  289. }
  290. #define _GET_SYSCON_REG_register17_SCFG_gpio_pad_ctrl_17(_ezchip_macro_read_value_) { \
  291. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register17_REG_ADDR); \
  292. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  293. }
  294. #define _SET_SYSCON_REG_register18_SCFG_gpio_pad_ctrl_18(v) { \
  295. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register18_REG_ADDR); \
  296. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  297. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  298. MA_OUTW(syscon_iopad_ctrl_register18_REG_ADDR,_ezchip_macro_read_value_); \
  299. }
  300. #define _GET_SYSCON_REG_register18_SCFG_gpio_pad_ctrl_18(_ezchip_macro_read_value_) { \
  301. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register18_REG_ADDR); \
  302. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  303. }
  304. #define _SET_SYSCON_REG_register19_SCFG_gpio_pad_ctrl_19(v) { \
  305. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register19_REG_ADDR); \
  306. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  307. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  308. MA_OUTW(syscon_iopad_ctrl_register19_REG_ADDR,_ezchip_macro_read_value_); \
  309. }
  310. #define _GET_SYSCON_REG_register19_SCFG_gpio_pad_ctrl_19(_ezchip_macro_read_value_) { \
  311. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register19_REG_ADDR); \
  312. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  313. }
  314. #define _SET_SYSCON_REG_register20_SCFG_gpio_pad_ctrl_20(v) { \
  315. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register20_REG_ADDR); \
  316. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  317. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  318. MA_OUTW(syscon_iopad_ctrl_register20_REG_ADDR,_ezchip_macro_read_value_); \
  319. }
  320. #define _GET_SYSCON_REG_register20_SCFG_gpio_pad_ctrl_20(_ezchip_macro_read_value_) { \
  321. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register20_REG_ADDR); \
  322. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  323. }
  324. #define _SET_SYSCON_REG_register21_SCFG_gpio_pad_ctrl_21(v) { \
  325. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register21_REG_ADDR); \
  326. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  327. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  328. MA_OUTW(syscon_iopad_ctrl_register21_REG_ADDR,_ezchip_macro_read_value_); \
  329. }
  330. #define _GET_SYSCON_REG_register21_SCFG_gpio_pad_ctrl_21(_ezchip_macro_read_value_) { \
  331. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register21_REG_ADDR); \
  332. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  333. }
  334. #define _SET_SYSCON_REG_register22_SCFG_gpio_pad_ctrl_22(v) { \
  335. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register22_REG_ADDR); \
  336. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  337. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  338. MA_OUTW(syscon_iopad_ctrl_register22_REG_ADDR,_ezchip_macro_read_value_); \
  339. }
  340. #define _GET_SYSCON_REG_register22_SCFG_gpio_pad_ctrl_22(_ezchip_macro_read_value_) { \
  341. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register22_REG_ADDR); \
  342. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  343. }
  344. #define _SET_SYSCON_REG_register23_SCFG_gpio_pad_ctrl_23(v) { \
  345. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register23_REG_ADDR); \
  346. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  347. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  348. MA_OUTW(syscon_iopad_ctrl_register23_REG_ADDR,_ezchip_macro_read_value_); \
  349. }
  350. #define _GET_SYSCON_REG_register23_SCFG_gpio_pad_ctrl_23(_ezchip_macro_read_value_) { \
  351. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register23_REG_ADDR); \
  352. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  353. }
  354. #define _SET_SYSCON_REG_register24_SCFG_gpio_pad_ctrl_24(v) { \
  355. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register24_REG_ADDR); \
  356. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  357. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  358. MA_OUTW(syscon_iopad_ctrl_register24_REG_ADDR,_ezchip_macro_read_value_); \
  359. }
  360. #define _GET_SYSCON_REG_register24_SCFG_gpio_pad_ctrl_24(_ezchip_macro_read_value_) { \
  361. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register24_REG_ADDR); \
  362. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  363. }
  364. #define _SET_SYSCON_REG_register25_SCFG_gpio_pad_ctrl_25(v) { \
  365. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register25_REG_ADDR); \
  366. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  367. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  368. MA_OUTW(syscon_iopad_ctrl_register25_REG_ADDR,_ezchip_macro_read_value_); \
  369. }
  370. #define _GET_SYSCON_REG_register25_SCFG_gpio_pad_ctrl_25(_ezchip_macro_read_value_) { \
  371. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register25_REG_ADDR); \
  372. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  373. }
  374. #define _SET_SYSCON_REG_register26_SCFG_gpio_pad_ctrl_26(v) { \
  375. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register26_REG_ADDR); \
  376. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  377. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  378. MA_OUTW(syscon_iopad_ctrl_register26_REG_ADDR,_ezchip_macro_read_value_); \
  379. }
  380. #define _GET_SYSCON_REG_register26_SCFG_gpio_pad_ctrl_26(_ezchip_macro_read_value_) { \
  381. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register26_REG_ADDR); \
  382. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  383. }
  384. #define _SET_SYSCON_REG_register27_SCFG_gpio_pad_ctrl_27(v) { \
  385. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register27_REG_ADDR); \
  386. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  387. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  388. MA_OUTW(syscon_iopad_ctrl_register27_REG_ADDR,_ezchip_macro_read_value_); \
  389. }
  390. #define _GET_SYSCON_REG_register27_SCFG_gpio_pad_ctrl_27(_ezchip_macro_read_value_) { \
  391. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register27_REG_ADDR); \
  392. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  393. }
  394. #define _SET_SYSCON_REG_register28_SCFG_gpio_pad_ctrl_28(v) { \
  395. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register28_REG_ADDR); \
  396. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  397. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  398. MA_OUTW(syscon_iopad_ctrl_register28_REG_ADDR,_ezchip_macro_read_value_); \
  399. }
  400. #define _GET_SYSCON_REG_register28_SCFG_gpio_pad_ctrl_28(_ezchip_macro_read_value_) { \
  401. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register28_REG_ADDR); \
  402. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  403. }
  404. #define _SET_SYSCON_REG_register29_SCFG_gpio_pad_ctrl_29(v) { \
  405. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register29_REG_ADDR); \
  406. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  407. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  408. MA_OUTW(syscon_iopad_ctrl_register29_REG_ADDR,_ezchip_macro_read_value_); \
  409. }
  410. #define _GET_SYSCON_REG_register29_SCFG_gpio_pad_ctrl_29(_ezchip_macro_read_value_) { \
  411. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register29_REG_ADDR); \
  412. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  413. }
  414. #define _SET_SYSCON_REG_register30_SCFG_gpio_pad_ctrl_30(v) { \
  415. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register30_REG_ADDR); \
  416. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  417. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  418. MA_OUTW(syscon_iopad_ctrl_register30_REG_ADDR,_ezchip_macro_read_value_); \
  419. }
  420. #define _GET_SYSCON_REG_register30_SCFG_gpio_pad_ctrl_30(_ezchip_macro_read_value_) { \
  421. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register30_REG_ADDR); \
  422. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  423. }
  424. #define _SET_SYSCON_REG_register31_SCFG_gpio_pad_ctrl_31(v) { \
  425. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register31_REG_ADDR); \
  426. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  427. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  428. MA_OUTW(syscon_iopad_ctrl_register31_REG_ADDR,_ezchip_macro_read_value_); \
  429. }
  430. #define _GET_SYSCON_REG_register31_SCFG_gpio_pad_ctrl_31(_ezchip_macro_read_value_) { \
  431. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register31_REG_ADDR); \
  432. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  433. }
  434. #define _SET_SYSCON_REG_register32_SCFG_funcshare_pad_ctrl_0(v) { \
  435. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register32_REG_ADDR); \
  436. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  437. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  438. MA_OUTW(syscon_iopad_ctrl_register32_REG_ADDR,_ezchip_macro_read_value_); \
  439. }
  440. #define _GET_SYSCON_REG_register32_SCFG_funcshare_pad_ctrl_0(_ezchip_macro_read_value_) { \
  441. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register32_REG_ADDR); \
  442. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  443. }
  444. #define _SET_SYSCON_REG_register33_SCFG_funcshare_pad_ctrl_1(v) { \
  445. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register33_REG_ADDR); \
  446. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  447. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  448. MA_OUTW(syscon_iopad_ctrl_register33_REG_ADDR,_ezchip_macro_read_value_); \
  449. }
  450. #define _GET_SYSCON_REG_register33_SCFG_funcshare_pad_ctrl_1(_ezchip_macro_read_value_) { \
  451. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register33_REG_ADDR); \
  452. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  453. }
  454. #define _SET_SYSCON_REG_register34_SCFG_funcshare_pad_ctrl_2(v) { \
  455. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register34_REG_ADDR); \
  456. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  457. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  458. MA_OUTW(syscon_iopad_ctrl_register34_REG_ADDR,_ezchip_macro_read_value_); \
  459. }
  460. #define _GET_SYSCON_REG_register34_SCFG_funcshare_pad_ctrl_2(_ezchip_macro_read_value_) { \
  461. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register34_REG_ADDR); \
  462. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  463. }
  464. #define _SET_SYSCON_REG_register35_SCFG_funcshare_pad_ctrl_3(v) { \
  465. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register35_REG_ADDR); \
  466. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  467. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  468. MA_OUTW(syscon_iopad_ctrl_register35_REG_ADDR,_ezchip_macro_read_value_); \
  469. }
  470. #define _GET_SYSCON_REG_register35_SCFG_funcshare_pad_ctrl_3(_ezchip_macro_read_value_) { \
  471. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register35_REG_ADDR); \
  472. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  473. }
  474. #define _SET_SYSCON_REG_register36_SCFG_funcshare_pad_ctrl_4(v) { \
  475. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register36_REG_ADDR); \
  476. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  477. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  478. MA_OUTW(syscon_iopad_ctrl_register36_REG_ADDR,_ezchip_macro_read_value_); \
  479. }
  480. #define _GET_SYSCON_REG_register36_SCFG_funcshare_pad_ctrl_4(_ezchip_macro_read_value_) { \
  481. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register36_REG_ADDR); \
  482. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  483. }
  484. #define _SET_SYSCON_REG_register37_SCFG_funcshare_pad_ctrl_5(v) { \
  485. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register37_REG_ADDR); \
  486. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  487. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  488. MA_OUTW(syscon_iopad_ctrl_register37_REG_ADDR,_ezchip_macro_read_value_); \
  489. }
  490. #define _GET_SYSCON_REG_register37_SCFG_funcshare_pad_ctrl_5(_ezchip_macro_read_value_) { \
  491. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register37_REG_ADDR); \
  492. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  493. }
  494. #define _SET_SYSCON_REG_register38_SCFG_funcshare_pad_ctrl_6(v) { \
  495. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register38_REG_ADDR); \
  496. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  497. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  498. MA_OUTW(syscon_iopad_ctrl_register38_REG_ADDR,_ezchip_macro_read_value_); \
  499. }
  500. #define _GET_SYSCON_REG_register38_SCFG_funcshare_pad_ctrl_6(_ezchip_macro_read_value_) { \
  501. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register38_REG_ADDR); \
  502. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  503. }
  504. #define _SET_SYSCON_REG_register39_SCFG_funcshare_pad_ctrl_7(v) { \
  505. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register39_REG_ADDR); \
  506. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  507. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  508. MA_OUTW(syscon_iopad_ctrl_register39_REG_ADDR,_ezchip_macro_read_value_); \
  509. }
  510. #define _GET_SYSCON_REG_register39_SCFG_funcshare_pad_ctrl_7(_ezchip_macro_read_value_) { \
  511. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register39_REG_ADDR); \
  512. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  513. }
  514. #define _SET_SYSCON_REG_register40_SCFG_funcshare_pad_ctrl_8(v) { \
  515. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register40_REG_ADDR); \
  516. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  517. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  518. MA_OUTW(syscon_iopad_ctrl_register40_REG_ADDR,_ezchip_macro_read_value_); \
  519. }
  520. #define _GET_SYSCON_REG_register40_SCFG_funcshare_pad_ctrl_8(_ezchip_macro_read_value_) { \
  521. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register40_REG_ADDR); \
  522. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  523. }
  524. #define _SET_SYSCON_REG_register41_SCFG_funcshare_pad_ctrl_9(v) { \
  525. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register41_REG_ADDR); \
  526. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  527. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  528. MA_OUTW(syscon_iopad_ctrl_register41_REG_ADDR,_ezchip_macro_read_value_); \
  529. }
  530. #define _GET_SYSCON_REG_register41_SCFG_funcshare_pad_ctrl_9(_ezchip_macro_read_value_) { \
  531. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register41_REG_ADDR); \
  532. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  533. }
  534. #define _SET_SYSCON_REG_register42_SCFG_funcshare_pad_ctrl_10(v) { \
  535. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register42_REG_ADDR); \
  536. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  537. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  538. MA_OUTW(syscon_iopad_ctrl_register42_REG_ADDR,_ezchip_macro_read_value_); \
  539. }
  540. #define _GET_SYSCON_REG_register42_SCFG_funcshare_pad_ctrl_10(_ezchip_macro_read_value_) { \
  541. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register42_REG_ADDR); \
  542. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  543. }
  544. #define _SET_SYSCON_REG_register43_SCFG_funcshare_pad_ctrl_11(v) { \
  545. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register43_REG_ADDR); \
  546. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  547. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  548. MA_OUTW(syscon_iopad_ctrl_register43_REG_ADDR,_ezchip_macro_read_value_); \
  549. }
  550. #define _GET_SYSCON_REG_register43_SCFG_funcshare_pad_ctrl_11(_ezchip_macro_read_value_) { \
  551. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register43_REG_ADDR); \
  552. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  553. }
  554. #define _SET_SYSCON_REG_register44_SCFG_funcshare_pad_ctrl_12(v) { \
  555. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register44_REG_ADDR); \
  556. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  557. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  558. MA_OUTW(syscon_iopad_ctrl_register44_REG_ADDR,_ezchip_macro_read_value_); \
  559. }
  560. #define _GET_SYSCON_REG_register44_SCFG_funcshare_pad_ctrl_12(_ezchip_macro_read_value_) { \
  561. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register44_REG_ADDR); \
  562. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  563. }
  564. #define _SET_SYSCON_REG_register45_SCFG_funcshare_pad_ctrl_13(v) { \
  565. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register45_REG_ADDR); \
  566. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  567. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  568. MA_OUTW(syscon_iopad_ctrl_register45_REG_ADDR,_ezchip_macro_read_value_); \
  569. }
  570. #define _GET_SYSCON_REG_register45_SCFG_funcshare_pad_ctrl_13(_ezchip_macro_read_value_) { \
  571. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register45_REG_ADDR); \
  572. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  573. }
  574. #define _SET_SYSCON_REG_register46_SCFG_funcshare_pad_ctrl_14(v) { \
  575. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register46_REG_ADDR); \
  576. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  577. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  578. MA_OUTW(syscon_iopad_ctrl_register46_REG_ADDR,_ezchip_macro_read_value_); \
  579. }
  580. #define _GET_SYSCON_REG_register46_SCFG_funcshare_pad_ctrl_14(_ezchip_macro_read_value_) { \
  581. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register46_REG_ADDR); \
  582. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  583. }
  584. #define _SET_SYSCON_REG_register47_SCFG_funcshare_pad_ctrl_15(v) { \
  585. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register47_REG_ADDR); \
  586. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  587. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  588. MA_OUTW(syscon_iopad_ctrl_register47_REG_ADDR,_ezchip_macro_read_value_); \
  589. }
  590. #define _GET_SYSCON_REG_register47_SCFG_funcshare_pad_ctrl_15(_ezchip_macro_read_value_) { \
  591. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register47_REG_ADDR); \
  592. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  593. }
  594. #define _SET_SYSCON_REG_register48_SCFG_funcshare_pad_ctrl_16(v) { \
  595. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register48_REG_ADDR); \
  596. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  597. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  598. MA_OUTW(syscon_iopad_ctrl_register48_REG_ADDR,_ezchip_macro_read_value_); \
  599. }
  600. #define _GET_SYSCON_REG_register48_SCFG_funcshare_pad_ctrl_16(_ezchip_macro_read_value_) { \
  601. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register48_REG_ADDR); \
  602. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  603. }
  604. #define _SET_SYSCON_REG_register49_SCFG_funcshare_pad_ctrl_17(v) { \
  605. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register49_REG_ADDR); \
  606. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  607. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  608. MA_OUTW(syscon_iopad_ctrl_register49_REG_ADDR,_ezchip_macro_read_value_); \
  609. }
  610. #define _GET_SYSCON_REG_register49_SCFG_funcshare_pad_ctrl_17(_ezchip_macro_read_value_) { \
  611. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register49_REG_ADDR); \
  612. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  613. }
  614. #define _SET_SYSCON_REG_register50_SCFG_funcshare_pad_ctrl_18(v) { \
  615. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register50_REG_ADDR); \
  616. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  617. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  618. MA_OUTW(syscon_iopad_ctrl_register50_REG_ADDR,_ezchip_macro_read_value_); \
  619. }
  620. #define _GET_SYSCON_REG_register50_SCFG_funcshare_pad_ctrl_18(_ezchip_macro_read_value_) { \
  621. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register50_REG_ADDR); \
  622. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  623. }
  624. #define _SET_SYSCON_REG_register51_SCFG_funcshare_pad_ctrl_19(v) { \
  625. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register51_REG_ADDR); \
  626. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  627. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  628. MA_OUTW(syscon_iopad_ctrl_register51_REG_ADDR,_ezchip_macro_read_value_); \
  629. }
  630. #define _GET_SYSCON_REG_register51_SCFG_funcshare_pad_ctrl_19(_ezchip_macro_read_value_) { \
  631. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register51_REG_ADDR); \
  632. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  633. }
  634. #define _SET_SYSCON_REG_register52_SCFG_funcshare_pad_ctrl_20(v) { \
  635. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register52_REG_ADDR); \
  636. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  637. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  638. MA_OUTW(syscon_iopad_ctrl_register52_REG_ADDR,_ezchip_macro_read_value_); \
  639. }
  640. #define _GET_SYSCON_REG_register52_SCFG_funcshare_pad_ctrl_20(_ezchip_macro_read_value_) { \
  641. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register52_REG_ADDR); \
  642. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  643. }
  644. #define _SET_SYSCON_REG_register53_SCFG_funcshare_pad_ctrl_21(v) { \
  645. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register53_REG_ADDR); \
  646. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  647. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  648. MA_OUTW(syscon_iopad_ctrl_register53_REG_ADDR,_ezchip_macro_read_value_); \
  649. }
  650. #define _GET_SYSCON_REG_register53_SCFG_funcshare_pad_ctrl_21(_ezchip_macro_read_value_) { \
  651. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register53_REG_ADDR); \
  652. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  653. }
  654. #define _SET_SYSCON_REG_register54_SCFG_funcshare_pad_ctrl_22(v) { \
  655. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register54_REG_ADDR); \
  656. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  657. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  658. MA_OUTW(syscon_iopad_ctrl_register54_REG_ADDR,_ezchip_macro_read_value_); \
  659. }
  660. #define _GET_SYSCON_REG_register54_SCFG_funcshare_pad_ctrl_22(_ezchip_macro_read_value_) { \
  661. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register54_REG_ADDR); \
  662. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  663. }
  664. #define _SET_SYSCON_REG_register55_SCFG_funcshare_pad_ctrl_23(v) { \
  665. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register55_REG_ADDR); \
  666. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  667. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  668. MA_OUTW(syscon_iopad_ctrl_register55_REG_ADDR,_ezchip_macro_read_value_); \
  669. }
  670. #define _GET_SYSCON_REG_register55_SCFG_funcshare_pad_ctrl_23(_ezchip_macro_read_value_) { \
  671. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register55_REG_ADDR); \
  672. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  673. }
  674. #define _SET_SYSCON_REG_register56_SCFG_funcshare_pad_ctrl_24(v) { \
  675. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register56_REG_ADDR); \
  676. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  677. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  678. MA_OUTW(syscon_iopad_ctrl_register56_REG_ADDR,_ezchip_macro_read_value_); \
  679. }
  680. #define _GET_SYSCON_REG_register56_SCFG_funcshare_pad_ctrl_24(_ezchip_macro_read_value_) { \
  681. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register56_REG_ADDR); \
  682. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  683. }
  684. #define _SET_SYSCON_REG_register57_SCFG_funcshare_pad_ctrl_25(v) { \
  685. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register57_REG_ADDR); \
  686. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  687. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  688. MA_OUTW(syscon_iopad_ctrl_register57_REG_ADDR,_ezchip_macro_read_value_); \
  689. }
  690. #define _GET_SYSCON_REG_register57_SCFG_funcshare_pad_ctrl_25(_ezchip_macro_read_value_) { \
  691. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register57_REG_ADDR); \
  692. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  693. }
  694. #define _SET_SYSCON_REG_register58_SCFG_funcshare_pad_ctrl_26(v) { \
  695. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register58_REG_ADDR); \
  696. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  697. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  698. MA_OUTW(syscon_iopad_ctrl_register58_REG_ADDR,_ezchip_macro_read_value_); \
  699. }
  700. #define _GET_SYSCON_REG_register58_SCFG_funcshare_pad_ctrl_26(_ezchip_macro_read_value_) { \
  701. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register58_REG_ADDR); \
  702. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  703. }
  704. #define _SET_SYSCON_REG_register59_SCFG_funcshare_pad_ctrl_27(v) { \
  705. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register59_REG_ADDR); \
  706. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  707. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  708. MA_OUTW(syscon_iopad_ctrl_register59_REG_ADDR,_ezchip_macro_read_value_); \
  709. }
  710. #define _GET_SYSCON_REG_register59_SCFG_funcshare_pad_ctrl_27(_ezchip_macro_read_value_) { \
  711. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register59_REG_ADDR); \
  712. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  713. }
  714. #define _SET_SYSCON_REG_register60_SCFG_funcshare_pad_ctrl_28(v) { \
  715. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register60_REG_ADDR); \
  716. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  717. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  718. MA_OUTW(syscon_iopad_ctrl_register60_REG_ADDR,_ezchip_macro_read_value_); \
  719. }
  720. #define _GET_SYSCON_REG_register60_SCFG_funcshare_pad_ctrl_28(_ezchip_macro_read_value_) { \
  721. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register60_REG_ADDR); \
  722. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  723. }
  724. #define _SET_SYSCON_REG_register61_SCFG_funcshare_pad_ctrl_29(v) { \
  725. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register61_REG_ADDR); \
  726. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  727. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  728. MA_OUTW(syscon_iopad_ctrl_register61_REG_ADDR,_ezchip_macro_read_value_); \
  729. }
  730. #define _GET_SYSCON_REG_register61_SCFG_funcshare_pad_ctrl_29(_ezchip_macro_read_value_) { \
  731. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register61_REG_ADDR); \
  732. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  733. }
  734. #define _SET_SYSCON_REG_register62_SCFG_funcshare_pad_ctrl_30(v) { \
  735. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register62_REG_ADDR); \
  736. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  737. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  738. MA_OUTW(syscon_iopad_ctrl_register62_REG_ADDR,_ezchip_macro_read_value_); \
  739. }
  740. #define _GET_SYSCON_REG_register62_SCFG_funcshare_pad_ctrl_30(_ezchip_macro_read_value_) { \
  741. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register62_REG_ADDR); \
  742. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  743. }
  744. #define _SET_SYSCON_REG_register63_SCFG_funcshare_pad_ctrl_31(v) { \
  745. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register63_REG_ADDR); \
  746. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  747. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  748. MA_OUTW(syscon_iopad_ctrl_register63_REG_ADDR,_ezchip_macro_read_value_); \
  749. }
  750. #define _GET_SYSCON_REG_register63_SCFG_funcshare_pad_ctrl_31(_ezchip_macro_read_value_) { \
  751. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register63_REG_ADDR); \
  752. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  753. }
  754. #define _SET_SYSCON_REG_register64_SCFG_funcshare_pad_ctrl_32(v) { \
  755. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register64_REG_ADDR); \
  756. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  757. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  758. MA_OUTW(syscon_iopad_ctrl_register64_REG_ADDR,_ezchip_macro_read_value_); \
  759. }
  760. #define _GET_SYSCON_REG_register64_SCFG_funcshare_pad_ctrl_32(_ezchip_macro_read_value_) { \
  761. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register64_REG_ADDR); \
  762. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  763. }
  764. #define _SET_SYSCON_REG_register65_SCFG_funcshare_pad_ctrl_33(v) { \
  765. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register65_REG_ADDR); \
  766. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  767. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  768. MA_OUTW(syscon_iopad_ctrl_register65_REG_ADDR,_ezchip_macro_read_value_); \
  769. }
  770. #define _GET_SYSCON_REG_register65_SCFG_funcshare_pad_ctrl_33(_ezchip_macro_read_value_) { \
  771. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register65_REG_ADDR); \
  772. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  773. }
  774. #define _SET_SYSCON_REG_register66_SCFG_funcshare_pad_ctrl_34(v) { \
  775. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register66_REG_ADDR); \
  776. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  777. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  778. MA_OUTW(syscon_iopad_ctrl_register66_REG_ADDR,_ezchip_macro_read_value_); \
  779. }
  780. #define _GET_SYSCON_REG_register66_SCFG_funcshare_pad_ctrl_34(_ezchip_macro_read_value_) { \
  781. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register66_REG_ADDR); \
  782. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  783. }
  784. #define _SET_SYSCON_REG_register67_SCFG_funcshare_pad_ctrl_35(v) { \
  785. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register67_REG_ADDR); \
  786. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  787. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  788. MA_OUTW(syscon_iopad_ctrl_register67_REG_ADDR,_ezchip_macro_read_value_); \
  789. }
  790. #define _GET_SYSCON_REG_register67_SCFG_funcshare_pad_ctrl_35(_ezchip_macro_read_value_) { \
  791. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register67_REG_ADDR); \
  792. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  793. }
  794. #define _SET_SYSCON_REG_register68_SCFG_funcshare_pad_ctrl_36(v) { \
  795. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register68_REG_ADDR); \
  796. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  797. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  798. MA_OUTW(syscon_iopad_ctrl_register68_REG_ADDR,_ezchip_macro_read_value_); \
  799. }
  800. #define _GET_SYSCON_REG_register68_SCFG_funcshare_pad_ctrl_36(_ezchip_macro_read_value_) { \
  801. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register68_REG_ADDR); \
  802. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  803. }
  804. #define _SET_SYSCON_REG_register69_SCFG_funcshare_pad_ctrl_37(v) { \
  805. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register69_REG_ADDR); \
  806. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  807. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  808. MA_OUTW(syscon_iopad_ctrl_register69_REG_ADDR,_ezchip_macro_read_value_); \
  809. }
  810. #define _GET_SYSCON_REG_register69_SCFG_funcshare_pad_ctrl_37(_ezchip_macro_read_value_) { \
  811. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register69_REG_ADDR); \
  812. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  813. }
  814. #define _SET_SYSCON_REG_register70_SCFG_funcshare_pad_ctrl_38(v) { \
  815. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register70_REG_ADDR); \
  816. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  817. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  818. MA_OUTW(syscon_iopad_ctrl_register70_REG_ADDR,_ezchip_macro_read_value_); \
  819. }
  820. #define _GET_SYSCON_REG_register70_SCFG_funcshare_pad_ctrl_38(_ezchip_macro_read_value_) { \
  821. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register70_REG_ADDR); \
  822. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  823. }
  824. #define _SET_SYSCON_REG_register71_SCFG_funcshare_pad_ctrl_39(v) { \
  825. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register71_REG_ADDR); \
  826. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  827. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  828. MA_OUTW(syscon_iopad_ctrl_register71_REG_ADDR,_ezchip_macro_read_value_); \
  829. }
  830. #define _GET_SYSCON_REG_register71_SCFG_funcshare_pad_ctrl_39(_ezchip_macro_read_value_) { \
  831. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register71_REG_ADDR); \
  832. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  833. }
  834. #define _SET_SYSCON_REG_register72_SCFG_funcshare_pad_ctrl_40(v) { \
  835. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register72_REG_ADDR); \
  836. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  837. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  838. MA_OUTW(syscon_iopad_ctrl_register72_REG_ADDR,_ezchip_macro_read_value_); \
  839. }
  840. #define _GET_SYSCON_REG_register72_SCFG_funcshare_pad_ctrl_40(_ezchip_macro_read_value_) { \
  841. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register72_REG_ADDR); \
  842. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  843. }
  844. #define _SET_SYSCON_REG_register73_SCFG_funcshare_pad_ctrl_41(v) { \
  845. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register73_REG_ADDR); \
  846. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  847. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  848. MA_OUTW(syscon_iopad_ctrl_register73_REG_ADDR,_ezchip_macro_read_value_); \
  849. }
  850. #define _GET_SYSCON_REG_register73_SCFG_funcshare_pad_ctrl_41(_ezchip_macro_read_value_) { \
  851. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register73_REG_ADDR); \
  852. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  853. }
  854. #define _SET_SYSCON_REG_register74_SCFG_funcshare_pad_ctrl_42(v) { \
  855. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register74_REG_ADDR); \
  856. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  857. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  858. MA_OUTW(syscon_iopad_ctrl_register74_REG_ADDR,_ezchip_macro_read_value_); \
  859. }
  860. #define _GET_SYSCON_REG_register74_SCFG_funcshare_pad_ctrl_42(_ezchip_macro_read_value_) { \
  861. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register74_REG_ADDR); \
  862. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  863. }
  864. #define _SET_SYSCON_REG_register75_SCFG_funcshare_pad_ctrl_43(v) { \
  865. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register75_REG_ADDR); \
  866. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  867. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  868. MA_OUTW(syscon_iopad_ctrl_register75_REG_ADDR,_ezchip_macro_read_value_); \
  869. }
  870. #define _GET_SYSCON_REG_register75_SCFG_funcshare_pad_ctrl_43(_ezchip_macro_read_value_) { \
  871. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register75_REG_ADDR); \
  872. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  873. }
  874. #define _SET_SYSCON_REG_register76_SCFG_funcshare_pad_ctrl_44(v) { \
  875. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register76_REG_ADDR); \
  876. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  877. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  878. MA_OUTW(syscon_iopad_ctrl_register76_REG_ADDR,_ezchip_macro_read_value_); \
  879. }
  880. #define _GET_SYSCON_REG_register76_SCFG_funcshare_pad_ctrl_44(_ezchip_macro_read_value_) { \
  881. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register76_REG_ADDR); \
  882. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  883. }
  884. #define _SET_SYSCON_REG_register77_SCFG_funcshare_pad_ctrl_45(v) { \
  885. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register77_REG_ADDR); \
  886. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  887. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  888. MA_OUTW(syscon_iopad_ctrl_register77_REG_ADDR,_ezchip_macro_read_value_); \
  889. }
  890. #define _GET_SYSCON_REG_register77_SCFG_funcshare_pad_ctrl_45(_ezchip_macro_read_value_) { \
  891. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register77_REG_ADDR); \
  892. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  893. }
  894. #define _SET_SYSCON_REG_register78_SCFG_funcshare_pad_ctrl_46(v) { \
  895. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register78_REG_ADDR); \
  896. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  897. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  898. MA_OUTW(syscon_iopad_ctrl_register78_REG_ADDR,_ezchip_macro_read_value_); \
  899. }
  900. #define _GET_SYSCON_REG_register78_SCFG_funcshare_pad_ctrl_46(_ezchip_macro_read_value_) { \
  901. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register78_REG_ADDR); \
  902. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  903. }
  904. #define _SET_SYSCON_REG_register79_SCFG_funcshare_pad_ctrl_47(v) { \
  905. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register79_REG_ADDR); \
  906. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  907. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  908. MA_OUTW(syscon_iopad_ctrl_register79_REG_ADDR,_ezchip_macro_read_value_); \
  909. }
  910. #define _GET_SYSCON_REG_register79_SCFG_funcshare_pad_ctrl_47(_ezchip_macro_read_value_) { \
  911. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register79_REG_ADDR); \
  912. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  913. }
  914. #define _SET_SYSCON_REG_register80_SCFG_funcshare_pad_ctrl_48(v) { \
  915. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register80_REG_ADDR); \
  916. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  917. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  918. MA_OUTW(syscon_iopad_ctrl_register80_REG_ADDR,_ezchip_macro_read_value_); \
  919. }
  920. #define _GET_SYSCON_REG_register80_SCFG_funcshare_pad_ctrl_48(_ezchip_macro_read_value_) { \
  921. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register80_REG_ADDR); \
  922. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  923. }
  924. #define _SET_SYSCON_REG_register81_SCFG_funcshare_pad_ctrl_49(v) { \
  925. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register81_REG_ADDR); \
  926. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  927. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  928. MA_OUTW(syscon_iopad_ctrl_register81_REG_ADDR,_ezchip_macro_read_value_); \
  929. }
  930. #define _GET_SYSCON_REG_register81_SCFG_funcshare_pad_ctrl_49(_ezchip_macro_read_value_) { \
  931. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register81_REG_ADDR); \
  932. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  933. }
  934. #define _SET_SYSCON_REG_register82_SCFG_funcshare_pad_ctrl_50(v) { \
  935. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register82_REG_ADDR); \
  936. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  937. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  938. MA_OUTW(syscon_iopad_ctrl_register82_REG_ADDR,_ezchip_macro_read_value_); \
  939. }
  940. #define _GET_SYSCON_REG_register82_SCFG_funcshare_pad_ctrl_50(_ezchip_macro_read_value_) { \
  941. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register82_REG_ADDR); \
  942. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  943. }
  944. #define _SET_SYSCON_REG_register83_SCFG_funcshare_pad_ctrl_51(v) { \
  945. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register83_REG_ADDR); \
  946. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  947. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  948. MA_OUTW(syscon_iopad_ctrl_register83_REG_ADDR,_ezchip_macro_read_value_); \
  949. }
  950. #define _GET_SYSCON_REG_register83_SCFG_funcshare_pad_ctrl_51(_ezchip_macro_read_value_) { \
  951. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register83_REG_ADDR); \
  952. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  953. }
  954. #define _SET_SYSCON_REG_register84_SCFG_funcshare_pad_ctrl_52(v) { \
  955. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register84_REG_ADDR); \
  956. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  957. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  958. MA_OUTW(syscon_iopad_ctrl_register84_REG_ADDR,_ezchip_macro_read_value_); \
  959. }
  960. #define _GET_SYSCON_REG_register84_SCFG_funcshare_pad_ctrl_52(_ezchip_macro_read_value_) { \
  961. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register84_REG_ADDR); \
  962. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  963. }
  964. #define _SET_SYSCON_REG_register85_SCFG_funcshare_pad_ctrl_53(v) { \
  965. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register85_REG_ADDR); \
  966. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  967. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  968. MA_OUTW(syscon_iopad_ctrl_register85_REG_ADDR,_ezchip_macro_read_value_); \
  969. }
  970. #define _GET_SYSCON_REG_register85_SCFG_funcshare_pad_ctrl_53(_ezchip_macro_read_value_) { \
  971. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register85_REG_ADDR); \
  972. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  973. }
  974. #define _SET_SYSCON_REG_register86_SCFG_funcshare_pad_ctrl_54(v) { \
  975. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register86_REG_ADDR); \
  976. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  977. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  978. MA_OUTW(syscon_iopad_ctrl_register86_REG_ADDR,_ezchip_macro_read_value_); \
  979. }
  980. #define _GET_SYSCON_REG_register86_SCFG_funcshare_pad_ctrl_54(_ezchip_macro_read_value_) { \
  981. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register86_REG_ADDR); \
  982. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  983. }
  984. #define _SET_SYSCON_REG_register87_SCFG_funcshare_pad_ctrl_55(v) { \
  985. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register87_REG_ADDR); \
  986. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  987. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  988. MA_OUTW(syscon_iopad_ctrl_register87_REG_ADDR,_ezchip_macro_read_value_); \
  989. }
  990. #define _GET_SYSCON_REG_register87_SCFG_funcshare_pad_ctrl_55(_ezchip_macro_read_value_) { \
  991. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register87_REG_ADDR); \
  992. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  993. }
  994. #define _SET_SYSCON_REG_register88_SCFG_funcshare_pad_ctrl_56(v) { \
  995. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register88_REG_ADDR); \
  996. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  997. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  998. MA_OUTW(syscon_iopad_ctrl_register88_REG_ADDR,_ezchip_macro_read_value_); \
  999. }
  1000. #define _GET_SYSCON_REG_register88_SCFG_funcshare_pad_ctrl_56(_ezchip_macro_read_value_) { \
  1001. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register88_REG_ADDR); \
  1002. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1003. }
  1004. #define _SET_SYSCON_REG_register89_SCFG_funcshare_pad_ctrl_57(v) { \
  1005. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register89_REG_ADDR); \
  1006. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1007. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1008. MA_OUTW(syscon_iopad_ctrl_register89_REG_ADDR,_ezchip_macro_read_value_); \
  1009. }
  1010. #define _GET_SYSCON_REG_register89_SCFG_funcshare_pad_ctrl_57(_ezchip_macro_read_value_) { \
  1011. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register89_REG_ADDR); \
  1012. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1013. }
  1014. #define _SET_SYSCON_REG_register90_SCFG_funcshare_pad_ctrl_58(v) { \
  1015. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register90_REG_ADDR); \
  1016. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1017. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1018. MA_OUTW(syscon_iopad_ctrl_register90_REG_ADDR,_ezchip_macro_read_value_); \
  1019. }
  1020. #define _GET_SYSCON_REG_register90_SCFG_funcshare_pad_ctrl_58(_ezchip_macro_read_value_) { \
  1021. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register90_REG_ADDR); \
  1022. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1023. }
  1024. #define _SET_SYSCON_REG_register91_SCFG_funcshare_pad_ctrl_59(v) { \
  1025. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register91_REG_ADDR); \
  1026. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1027. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1028. MA_OUTW(syscon_iopad_ctrl_register91_REG_ADDR,_ezchip_macro_read_value_); \
  1029. }
  1030. #define _GET_SYSCON_REG_register91_SCFG_funcshare_pad_ctrl_59(_ezchip_macro_read_value_) { \
  1031. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register91_REG_ADDR); \
  1032. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1033. }
  1034. #define _SET_SYSCON_REG_register92_SCFG_funcshare_pad_ctrl_60(v) { \
  1035. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register92_REG_ADDR); \
  1036. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1037. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1038. MA_OUTW(syscon_iopad_ctrl_register92_REG_ADDR,_ezchip_macro_read_value_); \
  1039. }
  1040. #define _GET_SYSCON_REG_register92_SCFG_funcshare_pad_ctrl_60(_ezchip_macro_read_value_) { \
  1041. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register92_REG_ADDR); \
  1042. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1043. }
  1044. #define _SET_SYSCON_REG_register93_SCFG_funcshare_pad_ctrl_61(v) { \
  1045. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register93_REG_ADDR); \
  1046. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1047. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1048. MA_OUTW(syscon_iopad_ctrl_register93_REG_ADDR,_ezchip_macro_read_value_); \
  1049. }
  1050. #define _GET_SYSCON_REG_register93_SCFG_funcshare_pad_ctrl_61(_ezchip_macro_read_value_) { \
  1051. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register93_REG_ADDR); \
  1052. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1053. }
  1054. #define _SET_SYSCON_REG_register94_SCFG_funcshare_pad_ctrl_62(v) { \
  1055. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register94_REG_ADDR); \
  1056. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1057. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1058. MA_OUTW(syscon_iopad_ctrl_register94_REG_ADDR,_ezchip_macro_read_value_); \
  1059. }
  1060. #define _GET_SYSCON_REG_register94_SCFG_funcshare_pad_ctrl_62(_ezchip_macro_read_value_) { \
  1061. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register94_REG_ADDR); \
  1062. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1063. }
  1064. #define _SET_SYSCON_REG_register95_SCFG_funcshare_pad_ctrl_63(v) { \
  1065. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register95_REG_ADDR); \
  1066. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1067. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1068. MA_OUTW(syscon_iopad_ctrl_register95_REG_ADDR,_ezchip_macro_read_value_); \
  1069. }
  1070. #define _GET_SYSCON_REG_register95_SCFG_funcshare_pad_ctrl_63(_ezchip_macro_read_value_) { \
  1071. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register95_REG_ADDR); \
  1072. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1073. }
  1074. #define _SET_SYSCON_REG_register96_SCFG_funcshare_pad_ctrl_64(v) { \
  1075. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register96_REG_ADDR); \
  1076. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1077. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1078. MA_OUTW(syscon_iopad_ctrl_register96_REG_ADDR,_ezchip_macro_read_value_); \
  1079. }
  1080. #define _GET_SYSCON_REG_register96_SCFG_funcshare_pad_ctrl_64(_ezchip_macro_read_value_) { \
  1081. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register96_REG_ADDR); \
  1082. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1083. }
  1084. #define _SET_SYSCON_REG_register97_SCFG_funcshare_pad_ctrl_65(v) { \
  1085. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register97_REG_ADDR); \
  1086. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1087. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1088. MA_OUTW(syscon_iopad_ctrl_register97_REG_ADDR,_ezchip_macro_read_value_); \
  1089. }
  1090. #define _GET_SYSCON_REG_register97_SCFG_funcshare_pad_ctrl_65(_ezchip_macro_read_value_) { \
  1091. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register97_REG_ADDR); \
  1092. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1093. }
  1094. #define _SET_SYSCON_REG_register98_SCFG_funcshare_pad_ctrl_66(v) { \
  1095. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register98_REG_ADDR); \
  1096. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1097. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1098. MA_OUTW(syscon_iopad_ctrl_register98_REG_ADDR,_ezchip_macro_read_value_); \
  1099. }
  1100. #define _GET_SYSCON_REG_register98_SCFG_funcshare_pad_ctrl_66(_ezchip_macro_read_value_) { \
  1101. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register98_REG_ADDR); \
  1102. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1103. }
  1104. #define _SET_SYSCON_REG_register99_SCFG_funcshare_pad_ctrl_67(v) { \
  1105. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register99_REG_ADDR); \
  1106. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1107. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1108. MA_OUTW(syscon_iopad_ctrl_register99_REG_ADDR,_ezchip_macro_read_value_); \
  1109. }
  1110. #define _GET_SYSCON_REG_register99_SCFG_funcshare_pad_ctrl_67(_ezchip_macro_read_value_) { \
  1111. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register99_REG_ADDR); \
  1112. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1113. }
  1114. #define _SET_SYSCON_REG_register100_SCFG_funcshare_pad_ctrl_68(v) { \
  1115. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register100_REG_ADDR); \
  1116. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1117. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1118. MA_OUTW(syscon_iopad_ctrl_register100_REG_ADDR,_ezchip_macro_read_value_); \
  1119. }
  1120. #define _GET_SYSCON_REG_register100_SCFG_funcshare_pad_ctrl_68(_ezchip_macro_read_value_) { \
  1121. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register100_REG_ADDR); \
  1122. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1123. }
  1124. #define _SET_SYSCON_REG_register101_SCFG_funcshare_pad_ctrl_69(v) { \
  1125. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register101_REG_ADDR); \
  1126. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1127. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1128. MA_OUTW(syscon_iopad_ctrl_register101_REG_ADDR,_ezchip_macro_read_value_); \
  1129. }
  1130. #define _GET_SYSCON_REG_register101_SCFG_funcshare_pad_ctrl_69(_ezchip_macro_read_value_) { \
  1131. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register101_REG_ADDR); \
  1132. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1133. }
  1134. #define _SET_SYSCON_REG_register102_SCFG_funcshare_pad_ctrl_70(v) { \
  1135. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register102_REG_ADDR); \
  1136. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1137. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1138. MA_OUTW(syscon_iopad_ctrl_register102_REG_ADDR,_ezchip_macro_read_value_); \
  1139. }
  1140. #define _GET_SYSCON_REG_register102_SCFG_funcshare_pad_ctrl_70(_ezchip_macro_read_value_) { \
  1141. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register102_REG_ADDR); \
  1142. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1143. }
  1144. #define _SET_SYSCON_REG_register103_SCFG_qspi_ioctrl(v) { \
  1145. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register103_REG_ADDR); \
  1146. _ezchip_macro_read_value_ &= ~(0x7F); \
  1147. _ezchip_macro_read_value_ |= (v&0x7F); \
  1148. MA_OUTW(syscon_iopad_ctrl_register103_REG_ADDR,_ezchip_macro_read_value_); \
  1149. }
  1150. #define _GET_SYSCON_REG_register103_SCFG_qspi_ioctrl(_ezchip_macro_read_value_) { \
  1151. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register103_REG_ADDR); \
  1152. _ezchip_macro_read_value_ &= 0x7f;\
  1153. }
  1154. #define _SET_SYSCON_REG_register104_SCFG_io_padshare_sel(v) { \
  1155. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register104_REG_ADDR); \
  1156. _ezchip_macro_read_value_ &= ~(0x7); \
  1157. _ezchip_macro_read_value_ |= (v&0x7); \
  1158. MA_OUTW(syscon_iopad_ctrl_register104_REG_ADDR,_ezchip_macro_read_value_); \
  1159. }
  1160. #define _GET_SYSCON_REG_register104_SCFG_io_padshare_sel(_ezchip_macro_read_value_) { \
  1161. _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register104_REG_ADDR); \
  1162. _ezchip_macro_read_value_ &= 0x7;\
  1163. }
  1164. #endif //_SYSCON_IOPAD_CTRL_MACRO_H_