bootmain.c 3.6 KB

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  1. #include "sys.h"
  2. #include "spi_flash.h"
  3. #include "spi.h"
  4. #include "encoding.h"
  5. #include <clkgen_ctrl_macro.h>
  6. #include <syscon_sysmain_ctrl_macro.h>
  7. #include <ezGPIO_fullMux_ctrl_macro.h>
  8. #include <rstgen_ctrl_macro.h>
  9. #include <syscon_iopad_ctrl_macro.h>
  10. typedef void ( *STARTRUNNING )( unsigned int par1 );
  11. /*
  12. To run a procedure from the address:start
  13. start: start address of runing in armmode, not do address align checking
  14. */
  15. void start2run32(unsigned int start)
  16. {
  17. (( STARTRUNNING )(start))(0);
  18. }
  19. #define SPIBOOT_LOAD_ADDR_OFFSET 252
  20. /*read data from flash to the destination address
  21. *
  22. *spi_flash: flash device informations
  23. *des_addr: store the data read from flash
  24. *page_offset:Offset of data stored in flash
  25. *mode:flash work mode
  26. */
  27. static int load_data(struct spi_flash* spi_flash,unsigned int des_addr,unsigned int page_offset,int mode)
  28. {
  29. u8 dataBuf[260];
  30. u32 startPage,endPage;
  31. u32 pageSize;
  32. u32 fileSize;
  33. u8 *addr;
  34. int ret;
  35. int i;
  36. u32 offset;
  37. pageSize = spi_flash->page_size;
  38. addr = (u8 *)des_addr;
  39. offset = page_offset*pageSize;
  40. /*read first page,get the file size*/
  41. ret = spi_flash->read(spi_flash,offset,pageSize,dataBuf,mode);
  42. if(ret != 0)
  43. {
  44. printk("read fail#\r\n");
  45. return -1;
  46. }
  47. /*calculate file size*/
  48. fileSize = (dataBuf[3] << 24) | (dataBuf[2] << 16) | (dataBuf[1] << 8) | (dataBuf[0]) ;
  49. if(fileSize == 0)
  50. return -1;
  51. endPage = ((fileSize + 255) >> 8);//page align
  52. /*copy the first page data*/
  53. sys_memcpy(addr, &dataBuf[4], SPIBOOT_LOAD_ADDR_OFFSET);
  54. offset += pageSize;
  55. addr += SPIBOOT_LOAD_ADDR_OFFSET;
  56. /*read Remaining pages data*/
  57. for(i=1; i<=endPage; i++)
  58. {
  59. ret = spi_flash->read(spi_flash,offset,pageSize, addr, mode);
  60. if(ret != 0)
  61. {
  62. printk("read fail##\r\n");
  63. return -1;
  64. }
  65. offset += pageSize;
  66. addr +=pageSize;
  67. }
  68. return 0;
  69. }
  70. void load_and_run_ddr(struct spi_flash* spi_flash,int mode)
  71. {
  72. unsigned int addr;
  73. int ret;
  74. addr = DEFAULT_DDR_ADDR;
  75. ret = load_data(spi_flash,addr,DEFAULT_DDR_OFFSET,mode);
  76. printk("bootloader version:%s\n\n",VERSION);
  77. if(!ret)
  78. {
  79. writel(0x1, 0x2000004);
  80. start2run32(addr);
  81. }
  82. else
  83. printk("\nload ddr bin fail.\n");
  84. /*never run to here*/
  85. while(1);
  86. }
  87. void boot_from_spi(int mode)
  88. {
  89. struct spi_flash* spi_flash;
  90. int ret;
  91. u32 *addr;
  92. u32 val;
  93. cadence_qspi_init(0, mode);
  94. spi_flash = spi_flash_probe(0, 0, 31250000, 0, (u32)SPI_DATAMODE_8);
  95. /*init ddr*/
  96. load_and_run_ddr(spi_flash,mode);
  97. }
  98. static void chip_clk_init()
  99. {
  100. _SWITCH_CLOCK_clk_cpundbus_root_SOURCE_clk_pll0_out_;
  101. _SWITCH_CLOCK_clk_dla_root_SOURCE_clk_pll1_out_;
  102. _SWITCH_CLOCK_clk_dsp_root_SOURCE_clk_pll2_out_;
  103. _SWITCH_CLOCK_clk_perh0_root_SOURCE_clk_pll0_out_;
  104. // slow down nne bus can fix nne50 & vp6 ram scan issue,
  105. // as well as vin_subsys reg scan issue.
  106. // _SWITCH_CLOCK_clk_nne_bus_SOURCE_clk_cpu_axi_;
  107. }
  108. /*only hartid 0 call this function*/
  109. void BootMain(void)
  110. {
  111. int boot_mode = 0;
  112. /*switch to pll mode*/
  113. chip_clk_init();
  114. _SET_SYSCON_REG_register69_core1_en(1);
  115. _SET_SYSCON_REG_register104_SCFG_io_padshare_sel(6);
  116. _SET_SYSCON_REG_register32_SCFG_funcshare_pad_ctrl_0(0x00c00000);
  117. _SET_SYSCON_REG_register33_SCFG_funcshare_pad_ctrl_1(0x00c000c0);
  118. _SET_SYSCON_REG_register34_SCFG_funcshare_pad_ctrl_2(0x00c000c0);
  119. _SET_SYSCON_REG_register35_SCFG_funcshare_pad_ctrl_3(0x00c000c0);
  120. _SET_SYSCON_REG_register39_SCFG_funcshare_pad_ctrl_7(0x00c300c3);
  121. _SET_SYSCON_REG_register38_SCFG_funcshare_pad_ctrl_6(0x00c00000);
  122. uart_init(3);
  123. writel(0x18000000, 0x1801fffc);
  124. writel(0x1, 0x2000004); /*从bootrom中恢复hart1*/
  125. boot_from_spi(1);
  126. /*never run to heare*/
  127. }