syscon_sysmain_ctrl_macro.h 75 KB

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  1. /******************************************************************
  2. *
  3. * syscon_sysmain_ctrl_top C MACRO generated by ezchip
  4. *
  5. ******************************************************************/
  6. #ifndef _SYSCON_SYSMAIN_CTRL_MACRO_H_
  7. #define _SYSCON_SYSMAIN_CTRL_MACRO_H_
  8. //#define SYSCON_SYSMAIN_CTRL_BASE_ADDR 0x0
  9. #define syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x0
  10. #define syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x4
  11. #define syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x8
  12. #define syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xC
  13. #define syscon_sysmain_ctrl_register4_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x10
  14. #define syscon_sysmain_ctrl_SCFG_u74_boot_vect0_low_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x14
  15. #define syscon_sysmain_ctrl_SCFG_u74_boot_vect0_hi_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x18
  16. #define syscon_sysmain_ctrl_SCFG_u74_boot_vect1_low_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x1C
  17. #define syscon_sysmain_ctrl_SCFG_u74_boot_vect1_hi_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x20
  18. #define syscon_sysmain_ctrl_SCFG_u74_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x24
  19. #define syscon_sysmain_ctrl_register10_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x28
  20. #define syscon_sysmain_ctrl_register11_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x2C
  21. #define syscon_sysmain_ctrl_register12_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x30
  22. #define syscon_sysmain_ctrl_register13_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x34
  23. #define syscon_sysmain_ctrl_register14_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x38
  24. #define syscon_sysmain_ctrl_register15_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x3C
  25. #define syscon_sysmain_ctrl_register16_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x40
  26. #define syscon_sysmain_ctrl_register17_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x44
  27. #define syscon_sysmain_ctrl_register18_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x48
  28. #define syscon_sysmain_ctrl_register19_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x4C
  29. #define syscon_sysmain_ctrl_register20_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x50
  30. #define syscon_sysmain_ctrl_register21_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x54
  31. #define syscon_sysmain_ctrl_register22_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x58
  32. #define syscon_sysmain_ctrl_register23_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x5C
  33. #define syscon_sysmain_ctrl_qspi_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x60
  34. #define syscon_sysmain_ctrl_intmem_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x64
  35. #define syscon_sysmain_ctrl_register26_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x68
  36. #define syscon_sysmain_ctrl_register27_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x6C
  37. #define syscon_sysmain_ctrl_register28_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x70
  38. #define syscon_sysmain_ctrl_register29_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x74
  39. #define syscon_sysmain_ctrl_SCFG_gmac_timestamp0_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x78
  40. #define syscon_sysmain_ctrl_SCFG_gmac_timestamp1_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x7C
  41. #define syscon_sysmain_ctrl_register32_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x80
  42. #define syscon_sysmain_ctrl_register33_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x84
  43. #define syscon_sysmain_ctrl_register34_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x88
  44. #define syscon_sysmain_ctrl_register35_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x8C
  45. #define syscon_sysmain_ctrl_register36_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x90
  46. #define syscon_sysmain_ctrl_register37_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x94
  47. #define syscon_sysmain_ctrl_register38_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x98
  48. #define syscon_sysmain_ctrl_register39_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x9C
  49. #define syscon_sysmain_ctrl_register40_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xA0
  50. #define syscon_sysmain_ctrl_SCFG_intC1_7to0_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xA4
  51. #define syscon_sysmain_ctrl_SCFG_intC0_src15to8_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xA8
  52. #define syscon_sysmain_ctrl_SCFG_intC0_src23to16_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xAC
  53. #define syscon_sysmain_ctrl_SCFG_intC0_src31to24_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xB0
  54. #define syscon_sysmain_ctrl_register47_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xBC
  55. #define syscon_sysmain_ctrl_register48_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xC0
  56. #define syscon_sysmain_ctrl_register52_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xC4
  57. #define syscon_sysmain_ctrl_register49_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xC8
  58. #define syscon_sysmain_ctrl_register50_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xCC
  59. #define syscon_sysmain_ctrl_register51_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xD0
  60. #define syscon_sysmain_ctrl_register66_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xD8
  61. #define syscon_sysmain_ctrl_register53_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xDC
  62. #define syscon_sysmain_ctrl_register54_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xE0
  63. #define syscon_sysmain_ctrl_register55_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xE4
  64. #define syscon_sysmain_ctrl_register56_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xE8
  65. #define syscon_sysmain_ctrl_register57_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xEC
  66. #define syscon_sysmain_ctrl_register58_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xF0
  67. #define syscon_sysmain_ctrl_register59_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xF4
  68. #define syscon_sysmain_ctrl_register60_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xF8
  69. #define syscon_sysmain_ctrl_register61_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xFC
  70. #define syscon_sysmain_ctrl_register62_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x100
  71. #define syscon_sysmain_ctrl_register63_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x104
  72. #define syscon_sysmain_ctrl_register64_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x108
  73. #define syscon_sysmain_ctrl_register65_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x10C
  74. #define syscon_sysmain_ctrl_register68_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x110
  75. #define syscon_sysmain_ctrl_register67_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x114
  76. #define syscon_sysmain_ctrl_register69_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x118
  77. #define syscon_sysmain_ctrl_register70_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x11C
  78. #define syscon_sysmain_ctrl_register71_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x120
  79. #define syscon_sysmain_ctrl_register72_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x124
  80. #define _SET_SYSCON_REG_SCFG_pll0_reset(v) { \
  81. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR); \
  82. _ezchip_macro_read_value_ &= ~(0x1); \
  83. _ezchip_macro_read_value_ |= (v&0x1); \
  84. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR,_ezchip_macro_read_value_); \
  85. }
  86. #define _GET_SYSCON_REG_SCFG_pll0_reset(_ezchip_macro_read_value_) { \
  87. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR); \
  88. _ezchip_macro_read_value_ &= 0x1;\
  89. }
  90. #define _SET_SYSCON_REG_SCFG_pll0_pwrdn(v) { \
  91. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR); \
  92. _ezchip_macro_read_value_ &= ~(0x1<<1); \
  93. _ezchip_macro_read_value_ |= (v&0x1)<<1; \
  94. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR,_ezchip_macro_read_value_); \
  95. }
  96. #define _GET_SYSCON_REG_SCFG_pll0_pwrdn(_ezchip_macro_read_value_) { \
  97. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR) >> 1; \
  98. _ezchip_macro_read_value_ &= 0x1;\
  99. }
  100. #define _SET_SYSCON_REG_SCFG_pll0_intfb(v) { \
  101. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR); \
  102. _ezchip_macro_read_value_ &= ~(0x1<<2); \
  103. _ezchip_macro_read_value_ |= (v&0x1)<<2; \
  104. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR,_ezchip_macro_read_value_); \
  105. }
  106. #define _GET_SYSCON_REG_SCFG_pll0_intfb(_ezchip_macro_read_value_) { \
  107. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR) >> 2; \
  108. _ezchip_macro_read_value_ &= 0x1;\
  109. }
  110. #define _SET_SYSCON_REG_SCFG_pll0_bypass(v) { \
  111. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR); \
  112. _ezchip_macro_read_value_ &= ~(0x1<<3); \
  113. _ezchip_macro_read_value_ |= (v&0x1)<<3; \
  114. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR,_ezchip_macro_read_value_); \
  115. }
  116. #define _GET_SYSCON_REG_SCFG_pll0_bypass(_ezchip_macro_read_value_) { \
  117. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR) >> 3; \
  118. _ezchip_macro_read_value_ &= 0x1;\
  119. }
  120. #define _SET_SYSCON_REG_SCFG_pll0_clk_refdiv(v) { \
  121. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR); \
  122. _ezchip_macro_read_value_ &= ~(0xF<<4); \
  123. _ezchip_macro_read_value_ |= (v&0xF)<<4; \
  124. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR,_ezchip_macro_read_value_); \
  125. }
  126. #define _GET_SYSCON_REG_SCFG_pll0_clk_refdiv(_ezchip_macro_read_value_) { \
  127. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR) >> 4; \
  128. _ezchip_macro_read_value_ &= 0xf;\
  129. }
  130. #define _SET_SYSCON_REG_SCFG_pll0_clk_fbkdiv(v) { \
  131. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR); \
  132. _ezchip_macro_read_value_ &= ~(0x3F<<8); \
  133. _ezchip_macro_read_value_ |= (v&0x3F)<<8; \
  134. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR,_ezchip_macro_read_value_); \
  135. }
  136. #define _GET_SYSCON_REG_SCFG_pll0_clk_fbkdiv(_ezchip_macro_read_value_) { \
  137. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR) >> 8; \
  138. _ezchip_macro_read_value_ &= 0x3f;\
  139. }
  140. #define _SET_SYSCON_REG_SCFG_pll0_bw_adj(v) { \
  141. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR); \
  142. _ezchip_macro_read_value_ &= ~(0x3F<<16); \
  143. _ezchip_macro_read_value_ |= (v&0x3F)<<16; \
  144. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR,_ezchip_macro_read_value_); \
  145. }
  146. #define _GET_SYSCON_REG_SCFG_pll0_bw_adj(_ezchip_macro_read_value_) { \
  147. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR) >> 16; \
  148. _ezchip_macro_read_value_ &= 0x3f;\
  149. }
  150. #define _SET_SYSCON_REG_SCFG_pll0_clk_outdiv(v) { \
  151. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR); \
  152. _ezchip_macro_read_value_ &= ~(0xF<<24); \
  153. _ezchip_macro_read_value_ |= (v&0xF)<<24; \
  154. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR,_ezchip_macro_read_value_); \
  155. }
  156. #define _GET_SYSCON_REG_SCFG_pll0_clk_outdiv(_ezchip_macro_read_value_) { \
  157. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR) >> 24; \
  158. _ezchip_macro_read_value_ &= 0xf;\
  159. }
  160. #define _SET_SYSCON_REG_SCFG_pll1_reset(v) { \
  161. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR); \
  162. _ezchip_macro_read_value_ &= ~(0x1); \
  163. _ezchip_macro_read_value_ |= (v&0x1); \
  164. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,_ezchip_macro_read_value_); \
  165. }
  166. #define _GET_SYSCON_REG_SCFG_pll1_reset(_ezchip_macro_read_value_) { \
  167. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR); \
  168. _ezchip_macro_read_value_ &= 0x1;\
  169. }
  170. #define _SET_SYSCON_REG_SCFG_pll1_pwrdn(v) { \
  171. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR); \
  172. _ezchip_macro_read_value_ &= ~(0x1<<1); \
  173. _ezchip_macro_read_value_ |= (v&0x1)<<1; \
  174. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,_ezchip_macro_read_value_); \
  175. }
  176. #define _GET_SYSCON_REG_SCFG_pll1_pwrdn(_ezchip_macro_read_value_) { \
  177. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR) >> 1; \
  178. _ezchip_macro_read_value_ &= 0x1;\
  179. }
  180. #define _SET_SYSCON_REG_SCFG_pll1_intfb(v) { \
  181. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR); \
  182. _ezchip_macro_read_value_ &= ~(0x1<<2); \
  183. _ezchip_macro_read_value_ |= (v&0x1)<<2; \
  184. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,_ezchip_macro_read_value_); \
  185. }
  186. #define _GET_SYSCON_REG_SCFG_pll1_intfb(_ezchip_macro_read_value_) { \
  187. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR) >> 2; \
  188. _ezchip_macro_read_value_ &= 0x1;\
  189. }
  190. #define _SET_SYSCON_REG_SCFG_pll1_bypass(v) { \
  191. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR); \
  192. _ezchip_macro_read_value_ &= ~(0x1<<3); \
  193. _ezchip_macro_read_value_ |= (v&0x1)<<3; \
  194. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,_ezchip_macro_read_value_); \
  195. }
  196. #define _GET_SYSCON_REG_SCFG_pll1_bypass(_ezchip_macro_read_value_) { \
  197. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR) >> 3; \
  198. _ezchip_macro_read_value_ &= 0x1;\
  199. }
  200. #define _SET_SYSCON_REG_SCFG_pll1_clk_refdiv(v) { \
  201. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR); \
  202. _ezchip_macro_read_value_ &= ~(0xF<<4); \
  203. _ezchip_macro_read_value_ |= (v&0xF)<<4; \
  204. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,_ezchip_macro_read_value_); \
  205. }
  206. #define _GET_SYSCON_REG_SCFG_pll1_clk_refdiv(_ezchip_macro_read_value_) { \
  207. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR) >> 4; \
  208. _ezchip_macro_read_value_ &= 0xf;\
  209. }
  210. #define _SET_SYSCON_REG_SCFG_pll1_clk_fbkdiv(v) { \
  211. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR); \
  212. _ezchip_macro_read_value_ &= ~(0x3F<<8); \
  213. _ezchip_macro_read_value_ |= (v&0x3F)<<8; \
  214. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,_ezchip_macro_read_value_); \
  215. }
  216. #define _GET_SYSCON_REG_SCFG_pll1_clk_fbkdiv(_ezchip_macro_read_value_) { \
  217. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR) >> 8; \
  218. _ezchip_macro_read_value_ &= 0x3f;\
  219. }
  220. #define _SET_SYSCON_REG_SCFG_pll1_bw_adj(v) { \
  221. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR); \
  222. _ezchip_macro_read_value_ &= ~(0x3F<<16); \
  223. _ezchip_macro_read_value_ |= (v&0x3F)<<16; \
  224. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,_ezchip_macro_read_value_); \
  225. }
  226. #define _GET_SYSCON_REG_SCFG_pll1_bw_adj(_ezchip_macro_read_value_) { \
  227. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR) >> 16; \
  228. _ezchip_macro_read_value_ &= 0x3f;\
  229. }
  230. #define _SET_SYSCON_REG_SCFG_pll1_clk_outdiv(v) { \
  231. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR); \
  232. _ezchip_macro_read_value_ &= ~(0xF<<24); \
  233. _ezchip_macro_read_value_ |= (v&0xF)<<24; \
  234. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,_ezchip_macro_read_value_); \
  235. }
  236. #define _GET_SYSCON_REG_SCFG_pll1_clk_outdiv(_ezchip_macro_read_value_) { \
  237. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR) >> 24; \
  238. _ezchip_macro_read_value_ &= 0xf;\
  239. }
  240. #define _SET_SYSCON_REG_SCFG_pll2_reset(v) { \
  241. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR); \
  242. _ezchip_macro_read_value_ &= ~(0x1); \
  243. _ezchip_macro_read_value_ |= (v&0x1); \
  244. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR,_ezchip_macro_read_value_); \
  245. }
  246. #define _GET_SYSCON_REG_SCFG_pll2_reset(_ezchip_macro_read_value_) { \
  247. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR); \
  248. _ezchip_macro_read_value_ &= 0x1;\
  249. }
  250. #define _SET_SYSCON_REG_SCFG_pll2_pwrdn(v) { \
  251. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR); \
  252. _ezchip_macro_read_value_ &= ~(0x1<<1); \
  253. _ezchip_macro_read_value_ |= (v&0x1)<<1; \
  254. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR,_ezchip_macro_read_value_); \
  255. }
  256. #define _GET_SYSCON_REG_SCFG_pll2_pwrdn(_ezchip_macro_read_value_) { \
  257. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR) >> 1; \
  258. _ezchip_macro_read_value_ &= 0x1;\
  259. }
  260. #define _SET_SYSCON_REG_SCFG_pll2_intfb(v) { \
  261. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR); \
  262. _ezchip_macro_read_value_ &= ~(0x1<<2); \
  263. _ezchip_macro_read_value_ |= (v&0x1)<<2; \
  264. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR,_ezchip_macro_read_value_); \
  265. }
  266. #define _GET_SYSCON_REG_SCFG_pll2_intfb(_ezchip_macro_read_value_) { \
  267. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR) >> 2; \
  268. _ezchip_macro_read_value_ &= 0x1;\
  269. }
  270. #define _SET_SYSCON_REG_SCFG_pll2_bypass(v) { \
  271. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR); \
  272. _ezchip_macro_read_value_ &= ~(0x1<<3); \
  273. _ezchip_macro_read_value_ |= (v&0x1)<<3; \
  274. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR,_ezchip_macro_read_value_); \
  275. }
  276. #define _GET_SYSCON_REG_SCFG_pll2_bypass(_ezchip_macro_read_value_) { \
  277. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR) >> 3; \
  278. _ezchip_macro_read_value_ &= 0x1;\
  279. }
  280. #define _SET_SYSCON_REG_SCFG_pll2_clk_refdiv(v) { \
  281. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR); \
  282. _ezchip_macro_read_value_ &= ~(0xF<<4); \
  283. _ezchip_macro_read_value_ |= (v&0xF)<<4; \
  284. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR,_ezchip_macro_read_value_); \
  285. }
  286. #define _GET_SYSCON_REG_SCFG_pll2_clk_refdiv(_ezchip_macro_read_value_) { \
  287. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR) >> 4; \
  288. _ezchip_macro_read_value_ &= 0xf;\
  289. }
  290. #define _SET_SYSCON_REG_SCFG_pll2_clk_fbkdiv(v) { \
  291. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR); \
  292. _ezchip_macro_read_value_ &= ~(0x3F<<8); \
  293. _ezchip_macro_read_value_ |= (v&0x3F)<<8; \
  294. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR,_ezchip_macro_read_value_); \
  295. }
  296. #define _GET_SYSCON_REG_SCFG_pll2_clk_fbkdiv(_ezchip_macro_read_value_) { \
  297. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR) >> 8; \
  298. _ezchip_macro_read_value_ &= 0x3f;\
  299. }
  300. #define _SET_SYSCON_REG_SCFG_pll2_bw_adj(v) { \
  301. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR); \
  302. _ezchip_macro_read_value_ &= ~(0x3F<<16); \
  303. _ezchip_macro_read_value_ |= (v&0x3F)<<16; \
  304. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR,_ezchip_macro_read_value_); \
  305. }
  306. #define _GET_SYSCON_REG_SCFG_pll2_bw_adj(_ezchip_macro_read_value_) { \
  307. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR) >> 16; \
  308. _ezchip_macro_read_value_ &= 0x3f;\
  309. }
  310. #define _SET_SYSCON_REG_SCFG_pll2_clk_outdiv(v) { \
  311. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR); \
  312. _ezchip_macro_read_value_ &= ~(0xF<<24); \
  313. _ezchip_macro_read_value_ |= (v&0xF)<<24; \
  314. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR,_ezchip_macro_read_value_); \
  315. }
  316. #define _GET_SYSCON_REG_SCFG_pll2_clk_outdiv(_ezchip_macro_read_value_) { \
  317. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR) >> 24; \
  318. _ezchip_macro_read_value_ &= 0xf;\
  319. }
  320. #define _SET_SYSCON_REG_SCFG_plls_stat_pll0_test(v) { \
  321. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR); \
  322. _ezchip_macro_read_value_ &= ~(0x1); \
  323. _ezchip_macro_read_value_ |= (v&0x1); \
  324. MA_OUTW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR,_ezchip_macro_read_value_); \
  325. }
  326. #define _GET_SYSCON_REG_SCFG_plls_stat_pll0_test(_ezchip_macro_read_value_) { \
  327. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR); \
  328. _ezchip_macro_read_value_ &= 0x1;\
  329. }
  330. #define _SET_SYSCON_REG_SCFG_plls_stat_pll1_test(v) { \
  331. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR); \
  332. _ezchip_macro_read_value_ &= ~(0x1<<1); \
  333. _ezchip_macro_read_value_ |= (v&0x1)<<1; \
  334. MA_OUTW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR,_ezchip_macro_read_value_); \
  335. }
  336. #define _GET_SYSCON_REG_SCFG_plls_stat_pll1_test(_ezchip_macro_read_value_) { \
  337. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 1; \
  338. _ezchip_macro_read_value_ &= 0x1;\
  339. }
  340. #define _SET_SYSCON_REG_SCFG_plls_stat_pll2_test(v) { \
  341. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR); \
  342. _ezchip_macro_read_value_ &= ~(0x1<<2); \
  343. _ezchip_macro_read_value_ |= (v&0x1)<<2; \
  344. MA_OUTW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR,_ezchip_macro_read_value_); \
  345. }
  346. #define _GET_SYSCON_REG_SCFG_plls_stat_pll2_test(_ezchip_macro_read_value_) { \
  347. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 2; \
  348. _ezchip_macro_read_value_ &= 0x1;\
  349. }
  350. #define _GET_SYSCON_REG_SCFG_plls_stat_pll0_lock(_ezchip_macro_read_value_) { \
  351. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 4; \
  352. _ezchip_macro_read_value_ &= 0x1;\
  353. }
  354. #define _GET_SYSCON_REG_SCFG_plls_stat_pll0_ref_slip(_ezchip_macro_read_value_) { \
  355. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 5; \
  356. _ezchip_macro_read_value_ &= 0x1;\
  357. }
  358. #define _GET_SYSCON_REG_SCFG_plls_stat_pll0_fdbk_slip(_ezchip_macro_read_value_) { \
  359. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 6; \
  360. _ezchip_macro_read_value_ &= 0x1;\
  361. }
  362. #define _GET_SYSCON_REG_SCFG_plls_stat_pll1_lock(_ezchip_macro_read_value_) { \
  363. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 8; \
  364. _ezchip_macro_read_value_ &= 0x1;\
  365. }
  366. #define _GET_SYSCON_REG_SCFG_plls_stat_pll1_ref_slip(_ezchip_macro_read_value_) { \
  367. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 9; \
  368. _ezchip_macro_read_value_ &= 0x1;\
  369. }
  370. #define _GET_SYSCON_REG_SCFG_plls_stat_pll1_fdbk_slip(_ezchip_macro_read_value_) { \
  371. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 10; \
  372. _ezchip_macro_read_value_ &= 0x1;\
  373. }
  374. #define _GET_SYSCON_REG_SCFG_plls_stat_pll2_lock(_ezchip_macro_read_value_) { \
  375. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 12; \
  376. _ezchip_macro_read_value_ &= 0x1;\
  377. }
  378. #define _GET_SYSCON_REG_SCFG_plls_stat_pll2_ref_slip(_ezchip_macro_read_value_) { \
  379. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 13; \
  380. _ezchip_macro_read_value_ &= 0x1;\
  381. }
  382. #define _GET_SYSCON_REG_SCFG_plls_stat_pll2_fdbk_slip(_ezchip_macro_read_value_) { \
  383. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 14; \
  384. _ezchip_macro_read_value_ &= 0x1;\
  385. }
  386. #define _GET_SYSCON_REG_register4_SCFG_u74_halt_from_tile0(_ezchip_macro_read_value_) { \
  387. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register4_REG_ADDR); \
  388. _ezchip_macro_read_value_ &= 0x1;\
  389. }
  390. #define _GET_SYSCON_REG_register4_SCFG_u74_halt_from_tile1(_ezchip_macro_read_value_) { \
  391. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register4_REG_ADDR) >> 1; \
  392. _ezchip_macro_read_value_ &= 0x1;\
  393. }
  394. #define _GET_SYSCON_REG_register4_SCFG_u74_debug_ndreset(_ezchip_macro_read_value_) { \
  395. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register4_REG_ADDR) >> 2; \
  396. _ezchip_macro_read_value_ &= 0x1;\
  397. }
  398. #define _GET_SYSCON_REG_register4_SCFG_u74_debug_dmactive(_ezchip_macro_read_value_) { \
  399. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register4_REG_ADDR) >> 3; \
  400. _ezchip_macro_read_value_ &= 0x1;\
  401. }
  402. #define _SET_SYSCON_REG_SCFG_u74_boot_vect0_low_b32(v) { \
  403. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_boot_vect0_low_REG_ADDR); \
  404. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  405. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  406. MA_OUTW(syscon_sysmain_ctrl_SCFG_u74_boot_vect0_low_REG_ADDR,_ezchip_macro_read_value_); \
  407. }
  408. #define _GET_SYSCON_REG_SCFG_u74_boot_vect0_low_b32(_ezchip_macro_read_value_) { \
  409. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_boot_vect0_low_REG_ADDR); \
  410. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  411. }
  412. #define _SET_SYSCON_REG_SCFG_u74_boot_vect0_hi_b6(v) { \
  413. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_boot_vect0_hi_REG_ADDR); \
  414. _ezchip_macro_read_value_ &= ~(0x3F); \
  415. _ezchip_macro_read_value_ |= (v&0x3F); \
  416. MA_OUTW(syscon_sysmain_ctrl_SCFG_u74_boot_vect0_hi_REG_ADDR,_ezchip_macro_read_value_); \
  417. }
  418. #define _GET_SYSCON_REG_SCFG_u74_boot_vect0_hi_b6(_ezchip_macro_read_value_) { \
  419. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_boot_vect0_hi_REG_ADDR); \
  420. _ezchip_macro_read_value_ &= 0x3f;\
  421. }
  422. #define _SET_SYSCON_REG_SCFG_u74_boot_vect1_low_b32(v) { \
  423. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_boot_vect1_low_REG_ADDR); \
  424. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  425. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  426. MA_OUTW(syscon_sysmain_ctrl_SCFG_u74_boot_vect1_low_REG_ADDR,_ezchip_macro_read_value_); \
  427. }
  428. #define _GET_SYSCON_REG_SCFG_u74_boot_vect1_low_b32(_ezchip_macro_read_value_) { \
  429. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_boot_vect1_low_REG_ADDR); \
  430. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  431. }
  432. #define _SET_SYSCON_REG_SCFG_u74_boot_vect1_hi_b6(v) { \
  433. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_boot_vect1_hi_REG_ADDR); \
  434. _ezchip_macro_read_value_ &= ~(0x3F); \
  435. _ezchip_macro_read_value_ |= (v&0x3F); \
  436. MA_OUTW(syscon_sysmain_ctrl_SCFG_u74_boot_vect1_hi_REG_ADDR,_ezchip_macro_read_value_); \
  437. }
  438. #define _GET_SYSCON_REG_SCFG_u74_boot_vect1_hi_b6(_ezchip_macro_read_value_) { \
  439. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_boot_vect1_hi_REG_ADDR); \
  440. _ezchip_macro_read_value_ &= 0x3f;\
  441. }
  442. #define _SET_SYSCON_REG_SCFG_u74_PRID(v) { \
  443. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_REG_ADDR); \
  444. _ezchip_macro_read_value_ &= ~(0x7FF); \
  445. _ezchip_macro_read_value_ |= (v&0x7FF); \
  446. MA_OUTW(syscon_sysmain_ctrl_SCFG_u74_REG_ADDR,_ezchip_macro_read_value_); \
  447. }
  448. #define _GET_SYSCON_REG_SCFG_u74_PRID(_ezchip_macro_read_value_) { \
  449. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_REG_ADDR); \
  450. _ezchip_macro_read_value_ &= 0x7ff;\
  451. }
  452. #define _GET_SYSCON_REG_register10_e24_halt(_ezchip_macro_read_value_) { \
  453. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register10_REG_ADDR); \
  454. _ezchip_macro_read_value_ &= 0x1;\
  455. }
  456. #define _GET_SYSCON_REG_register10_e24_dbg_reset(_ezchip_macro_read_value_) { \
  457. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register10_REG_ADDR) >> 1; \
  458. _ezchip_macro_read_value_ &= 0x1;\
  459. }
  460. #define _GET_SYSCON_REG_register10_e24_dbg_active(_ezchip_macro_read_value_) { \
  461. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register10_REG_ADDR) >> 2; \
  462. _ezchip_macro_read_value_ &= 0x1;\
  463. }
  464. #define _SET_SYSCON_REG_register11_SCFG_nbdla_pwrbus_ram_a_pd(v) { \
  465. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register11_REG_ADDR); \
  466. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  467. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  468. MA_OUTW(syscon_sysmain_ctrl_register11_REG_ADDR,_ezchip_macro_read_value_); \
  469. }
  470. #define _GET_SYSCON_REG_register11_SCFG_nbdla_pwrbus_ram_a_pd(_ezchip_macro_read_value_) { \
  471. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register11_REG_ADDR); \
  472. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  473. }
  474. #define _SET_SYSCON_REG_register12_SCFG_nbdla_pwrbus_ram_c_pd(v) { \
  475. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register12_REG_ADDR); \
  476. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  477. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  478. MA_OUTW(syscon_sysmain_ctrl_register12_REG_ADDR,_ezchip_macro_read_value_); \
  479. }
  480. #define _GET_SYSCON_REG_register12_SCFG_nbdla_pwrbus_ram_c_pd(_ezchip_macro_read_value_) { \
  481. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register12_REG_ADDR); \
  482. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  483. }
  484. #define _SET_SYSCON_REG_register13_SCFG_nbdla_pwrbus_ram_o_pd(v) { \
  485. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register13_REG_ADDR); \
  486. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  487. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  488. MA_OUTW(syscon_sysmain_ctrl_register13_REG_ADDR,_ezchip_macro_read_value_); \
  489. }
  490. #define _GET_SYSCON_REG_register13_SCFG_nbdla_pwrbus_ram_o_pd(_ezchip_macro_read_value_) { \
  491. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register13_REG_ADDR); \
  492. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  493. }
  494. #define _SET_SYSCON_REG_register14_SCFG_nbdla_pwrbus_ram_p_pd(v) { \
  495. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register14_REG_ADDR); \
  496. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  497. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  498. MA_OUTW(syscon_sysmain_ctrl_register14_REG_ADDR,_ezchip_macro_read_value_); \
  499. }
  500. #define _GET_SYSCON_REG_register14_SCFG_nbdla_pwrbus_ram_p_pd(_ezchip_macro_read_value_) { \
  501. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register14_REG_ADDR); \
  502. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  503. }
  504. #define _SET_SYSCON_REG_register15_SCFG_nbdla_pwrbus_ram_x_pd(v) { \
  505. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register15_REG_ADDR); \
  506. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  507. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  508. MA_OUTW(syscon_sysmain_ctrl_register15_REG_ADDR,_ezchip_macro_read_value_); \
  509. }
  510. #define _GET_SYSCON_REG_register15_SCFG_nbdla_pwrbus_ram_x_pd(_ezchip_macro_read_value_) { \
  511. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register15_REG_ADDR); \
  512. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  513. }
  514. #define _SET_SYSCON_REG_register16_SCFG_nbdla_globclk_ovr_on(v) { \
  515. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register16_REG_ADDR); \
  516. _ezchip_macro_read_value_ &= ~(0x1); \
  517. _ezchip_macro_read_value_ |= (v&0x1); \
  518. MA_OUTW(syscon_sysmain_ctrl_register16_REG_ADDR,_ezchip_macro_read_value_); \
  519. }
  520. #define _GET_SYSCON_REG_register16_SCFG_nbdla_globclk_ovr_on(_ezchip_macro_read_value_) { \
  521. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register16_REG_ADDR); \
  522. _ezchip_macro_read_value_ &= 0x1;\
  523. }
  524. #define _SET_SYSCON_REG_register16_SCFG_nbdla_disable_clock_gating(v) { \
  525. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register16_REG_ADDR); \
  526. _ezchip_macro_read_value_ &= ~(0x1<<1); \
  527. _ezchip_macro_read_value_ |= (v&0x1)<<1; \
  528. MA_OUTW(syscon_sysmain_ctrl_register16_REG_ADDR,_ezchip_macro_read_value_); \
  529. }
  530. #define _GET_SYSCON_REG_register16_SCFG_nbdla_disable_clock_gating(_ezchip_macro_read_value_) { \
  531. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register16_REG_ADDR) >> 1; \
  532. _ezchip_macro_read_value_ &= 0x1;\
  533. }
  534. #define _SET_SYSCON_REG_register16_SCFG_nbdla_direct_reset(v) { \
  535. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register16_REG_ADDR); \
  536. _ezchip_macro_read_value_ &= ~(0x1<<2); \
  537. _ezchip_macro_read_value_ |= (v&0x1)<<2; \
  538. MA_OUTW(syscon_sysmain_ctrl_register16_REG_ADDR,_ezchip_macro_read_value_); \
  539. }
  540. #define _GET_SYSCON_REG_register16_SCFG_nbdla_direct_reset(_ezchip_macro_read_value_) { \
  541. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register16_REG_ADDR) >> 2; \
  542. _ezchip_macro_read_value_ &= 0x1;\
  543. }
  544. #define _SET_SYSCON_REG_register16_SCFG_nbdla_clkgating_en(v) { \
  545. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register16_REG_ADDR); \
  546. _ezchip_macro_read_value_ &= ~(0x1<<3); \
  547. _ezchip_macro_read_value_ |= (v&0x1)<<3; \
  548. MA_OUTW(syscon_sysmain_ctrl_register16_REG_ADDR,_ezchip_macro_read_value_); \
  549. }
  550. #define _GET_SYSCON_REG_register16_SCFG_nbdla_clkgating_en(_ezchip_macro_read_value_) { \
  551. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register16_REG_ADDR) >> 3; \
  552. _ezchip_macro_read_value_ &= 0x1;\
  553. }
  554. #define _GET_SYSCON_REG_register17_SCFG_jpegc_cur_inst_a(_ezchip_macro_read_value_) { \
  555. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register17_REG_ADDR); \
  556. _ezchip_macro_read_value_ &= 0x3;\
  557. }
  558. #define _GET_SYSCON_REG_register18_SCFG_wave511_vpu_idle(_ezchip_macro_read_value_) { \
  559. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register18_REG_ADDR); \
  560. _ezchip_macro_read_value_ &= 0x1;\
  561. }
  562. #define _GET_SYSCON_REG_register19_SCFG_wave521_vpu_idle(_ezchip_macro_read_value_) { \
  563. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register19_REG_ADDR); \
  564. _ezchip_macro_read_value_ &= 0x1;\
  565. }
  566. #define _SET_SYSCON_REG_register20_u0_syscon_162_SCFG_gc300_csys_req(v) { \
  567. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register20_REG_ADDR); \
  568. _ezchip_macro_read_value_ &= ~(0x1); \
  569. _ezchip_macro_read_value_ |= (v&0x1); \
  570. MA_OUTW(syscon_sysmain_ctrl_register20_REG_ADDR,_ezchip_macro_read_value_); \
  571. }
  572. #define _GET_SYSCON_REG_register20_u0_syscon_162_SCFG_gc300_csys_req(_ezchip_macro_read_value_) { \
  573. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register20_REG_ADDR); \
  574. _ezchip_macro_read_value_ &= 0x1;\
  575. }
  576. #define _GET_SYSCON_REG_register21_u0_syscon_162_SCFG_gc300_cactive(_ezchip_macro_read_value_) { \
  577. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register21_REG_ADDR); \
  578. _ezchip_macro_read_value_ &= 0x1;\
  579. }
  580. #define _GET_SYSCON_REG_register21_u0_syscon_162_SCFG_gc300_csys_ack(_ezchip_macro_read_value_) { \
  581. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register21_REG_ADDR) >> 1; \
  582. _ezchip_macro_read_value_ &= 0x1;\
  583. }
  584. #define _GET_SYSCON_REG_register22_u0_syscon_162_SCFG_gc300_debug_out(_ezchip_macro_read_value_) { \
  585. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register22_REG_ADDR); \
  586. _ezchip_macro_read_value_ &= 0xff;\
  587. }
  588. #define _SET_SYSCON_REG_register23_SCFG_cmsensor_rst0(v) { \
  589. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register23_REG_ADDR); \
  590. _ezchip_macro_read_value_ &= ~(0x1); \
  591. _ezchip_macro_read_value_ |= (v&0x1); \
  592. MA_OUTW(syscon_sysmain_ctrl_register23_REG_ADDR,_ezchip_macro_read_value_); \
  593. }
  594. #define _GET_SYSCON_REG_register23_SCFG_cmsensor_rst0(_ezchip_macro_read_value_) { \
  595. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register23_REG_ADDR); \
  596. _ezchip_macro_read_value_ &= 0x1;\
  597. }
  598. #define _SET_SYSCON_REG_register23_SCFG_cmsensor_rst1(v) { \
  599. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register23_REG_ADDR); \
  600. _ezchip_macro_read_value_ &= ~(0x1<<1); \
  601. _ezchip_macro_read_value_ |= (v&0x1)<<1; \
  602. MA_OUTW(syscon_sysmain_ctrl_register23_REG_ADDR,_ezchip_macro_read_value_); \
  603. }
  604. #define _GET_SYSCON_REG_register23_SCFG_cmsensor_rst1(_ezchip_macro_read_value_) { \
  605. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register23_REG_ADDR) >> 1; \
  606. _ezchip_macro_read_value_ &= 0x1;\
  607. }
  608. #define _SET_SYSCON_REG_qspi_SCFG_sram_config(v) { \
  609. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_qspi_REG_ADDR); \
  610. _ezchip_macro_read_value_ &= ~(0xFF); \
  611. _ezchip_macro_read_value_ |= (v&0xFF); \
  612. MA_OUTW(syscon_sysmain_ctrl_qspi_REG_ADDR,_ezchip_macro_read_value_); \
  613. }
  614. #define _GET_SYSCON_REG_qspi_SCFG_sram_config(_ezchip_macro_read_value_) { \
  615. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_qspi_REG_ADDR); \
  616. _ezchip_macro_read_value_ &= 0xff;\
  617. }
  618. #define _SET_SYSCON_REG_intmem_SCFG_sram_config(v) { \
  619. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_intmem_REG_ADDR); \
  620. _ezchip_macro_read_value_ &= ~(0xFF); \
  621. _ezchip_macro_read_value_ |= (v&0xFF); \
  622. MA_OUTW(syscon_sysmain_ctrl_intmem_REG_ADDR,_ezchip_macro_read_value_); \
  623. }
  624. #define _GET_SYSCON_REG_intmem_SCFG_sram_config(_ezchip_macro_read_value_) { \
  625. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_intmem_REG_ADDR); \
  626. _ezchip_macro_read_value_ &= 0xff;\
  627. }
  628. #define _SET_SYSCON_REG_intmem_SCFG_sram_config_rom(v) { \
  629. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_intmem_REG_ADDR); \
  630. _ezchip_macro_read_value_ &= ~(0xFF<<8); \
  631. _ezchip_macro_read_value_ |= (v&0xFF)<<8; \
  632. MA_OUTW(syscon_sysmain_ctrl_intmem_REG_ADDR,_ezchip_macro_read_value_); \
  633. }
  634. #define _GET_SYSCON_REG_intmem_SCFG_sram_config_rom(_ezchip_macro_read_value_) { \
  635. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_intmem_REG_ADDR) >> 8; \
  636. _ezchip_macro_read_value_ &= 0xff;\
  637. }
  638. #define _SET_SYSCON_REG_register26_SCFG_dma1p2p_sel(v) { \
  639. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register26_REG_ADDR); \
  640. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  641. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  642. MA_OUTW(syscon_sysmain_ctrl_register26_REG_ADDR,_ezchip_macro_read_value_); \
  643. }
  644. #define _GET_SYSCON_REG_register26_SCFG_dma1p2p_sel(_ezchip_macro_read_value_) { \
  645. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register26_REG_ADDR); \
  646. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  647. }
  648. #define _SET_SYSCON_REG_register27_SCFG_dmaezMst_sel(v) { \
  649. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register27_REG_ADDR); \
  650. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  651. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  652. MA_OUTW(syscon_sysmain_ctrl_register27_REG_ADDR,_ezchip_macro_read_value_); \
  653. }
  654. #define _GET_SYSCON_REG_register27_SCFG_dmaezMst_sel(_ezchip_macro_read_value_) { \
  655. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register27_REG_ADDR); \
  656. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  657. }
  658. #define _SET_SYSCON_REG_register28_SCFG_gmac_phy_intf_sel(v) { \
  659. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register28_REG_ADDR); \
  660. _ezchip_macro_read_value_ &= ~(0x7); \
  661. _ezchip_macro_read_value_ |= (v&0x7); \
  662. MA_OUTW(syscon_sysmain_ctrl_register28_REG_ADDR,_ezchip_macro_read_value_); \
  663. }
  664. #define _GET_SYSCON_REG_register28_SCFG_gmac_phy_intf_sel(_ezchip_macro_read_value_) { \
  665. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register28_REG_ADDR); \
  666. _ezchip_macro_read_value_ &= 0x7;\
  667. }
  668. #define _SET_SYSCON_REG_register28_gmac_SCFG_sram_cfg(v) { \
  669. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register28_REG_ADDR); \
  670. _ezchip_macro_read_value_ &= ~(0xFF<<4); \
  671. _ezchip_macro_read_value_ |= (v&0xFF)<<4; \
  672. MA_OUTW(syscon_sysmain_ctrl_register28_REG_ADDR,_ezchip_macro_read_value_); \
  673. }
  674. #define _GET_SYSCON_REG_register28_gmac_SCFG_sram_cfg(_ezchip_macro_read_value_) { \
  675. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register28_REG_ADDR) >> 4; \
  676. _ezchip_macro_read_value_ &= 0xff;\
  677. }
  678. #define _GET_SYSCON_REG_register29_gmac_speed(_ezchip_macro_read_value_) { \
  679. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register29_REG_ADDR); \
  680. _ezchip_macro_read_value_ &= 0x3;\
  681. }
  682. #define _GET_SYSCON_REG_register29_gmac_ptp_pps(_ezchip_macro_read_value_) { \
  683. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register29_REG_ADDR) >> 2; \
  684. _ezchip_macro_read_value_ &= 0x1;\
  685. }
  686. #define _GET_SYSCON_REG_register29_gmac_tx_ckg_ctrl(_ezchip_macro_read_value_) { \
  687. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register29_REG_ADDR) >> 3; \
  688. _ezchip_macro_read_value_ &= 0x1;\
  689. }
  690. #define _GET_SYSCON_REG_SCFG_gmac_timestamp0_ptp(_ezchip_macro_read_value_) { \
  691. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_gmac_timestamp0_REG_ADDR); \
  692. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  693. }
  694. #define _GET_SYSCON_REG_SCFG_gmac_timestamp1_ptp(_ezchip_macro_read_value_) { \
  695. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_gmac_timestamp1_REG_ADDR); \
  696. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  697. }
  698. #define _SET_SYSCON_REG_register32_SCFG_gmac_phy_rstn(v) { \
  699. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register32_REG_ADDR); \
  700. _ezchip_macro_read_value_ &= ~(0x1); \
  701. _ezchip_macro_read_value_ |= (v&0x1); \
  702. MA_OUTW(syscon_sysmain_ctrl_register32_REG_ADDR,_ezchip_macro_read_value_); \
  703. }
  704. #define _GET_SYSCON_REG_register32_SCFG_gmac_phy_rstn(_ezchip_macro_read_value_) { \
  705. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register32_REG_ADDR); \
  706. _ezchip_macro_read_value_ &= 0x1;\
  707. }
  708. #define _SET_SYSCON_REG_register33_SCFG_sdio0_hbig_endian(v) { \
  709. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register33_REG_ADDR); \
  710. _ezchip_macro_read_value_ &= ~(0x1); \
  711. _ezchip_macro_read_value_ |= (v&0x1); \
  712. MA_OUTW(syscon_sysmain_ctrl_register33_REG_ADDR,_ezchip_macro_read_value_); \
  713. }
  714. #define _GET_SYSCON_REG_register33_SCFG_sdio0_hbig_endian(_ezchip_macro_read_value_) { \
  715. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register33_REG_ADDR); \
  716. _ezchip_macro_read_value_ &= 0x1;\
  717. }
  718. #define _SET_SYSCON_REG_register33_SCFG_sdio0_m_hbig_endian(v) { \
  719. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register33_REG_ADDR); \
  720. _ezchip_macro_read_value_ &= ~(0x1<<1); \
  721. _ezchip_macro_read_value_ |= (v&0x1)<<1; \
  722. MA_OUTW(syscon_sysmain_ctrl_register33_REG_ADDR,_ezchip_macro_read_value_); \
  723. }
  724. #define _GET_SYSCON_REG_register33_SCFG_sdio0_m_hbig_endian(_ezchip_macro_read_value_) { \
  725. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register33_REG_ADDR) >> 1; \
  726. _ezchip_macro_read_value_ &= 0x1;\
  727. }
  728. #define _SET_SYSCON_REG_register33_sdio0_SCFG_sram_config(v) { \
  729. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register33_REG_ADDR); \
  730. _ezchip_macro_read_value_ &= ~(0xFF<<2); \
  731. _ezchip_macro_read_value_ |= (v&0xFF)<<2; \
  732. MA_OUTW(syscon_sysmain_ctrl_register33_REG_ADDR,_ezchip_macro_read_value_); \
  733. }
  734. #define _GET_SYSCON_REG_register33_sdio0_SCFG_sram_config(_ezchip_macro_read_value_) { \
  735. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register33_REG_ADDR) >> 2; \
  736. _ezchip_macro_read_value_ &= 0xff;\
  737. }
  738. #define _SET_SYSCON_REG_register34_SCFG_sdio1_hbig_endian(v) { \
  739. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register34_REG_ADDR); \
  740. _ezchip_macro_read_value_ &= ~(0x1); \
  741. _ezchip_macro_read_value_ |= (v&0x1); \
  742. MA_OUTW(syscon_sysmain_ctrl_register34_REG_ADDR,_ezchip_macro_read_value_); \
  743. }
  744. #define _GET_SYSCON_REG_register34_SCFG_sdio1_hbig_endian(_ezchip_macro_read_value_) { \
  745. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register34_REG_ADDR); \
  746. _ezchip_macro_read_value_ &= 0x1;\
  747. }
  748. #define _SET_SYSCON_REG_register34_SCFG_sdio1_m_hbig_endian(v) { \
  749. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register34_REG_ADDR); \
  750. _ezchip_macro_read_value_ &= ~(0x1<<1); \
  751. _ezchip_macro_read_value_ |= (v&0x1)<<1; \
  752. MA_OUTW(syscon_sysmain_ctrl_register34_REG_ADDR,_ezchip_macro_read_value_); \
  753. }
  754. #define _GET_SYSCON_REG_register34_SCFG_sdio1_m_hbig_endian(_ezchip_macro_read_value_) { \
  755. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register34_REG_ADDR) >> 1; \
  756. _ezchip_macro_read_value_ &= 0x1;\
  757. }
  758. #define _SET_SYSCON_REG_register34_sdio1_SCFG_sram_config(v) { \
  759. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register34_REG_ADDR); \
  760. _ezchip_macro_read_value_ &= ~(0xFF<<2); \
  761. _ezchip_macro_read_value_ |= (v&0xFF)<<2; \
  762. MA_OUTW(syscon_sysmain_ctrl_register34_REG_ADDR,_ezchip_macro_read_value_); \
  763. }
  764. #define _GET_SYSCON_REG_register34_sdio1_SCFG_sram_config(_ezchip_macro_read_value_) { \
  765. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register34_REG_ADDR) >> 2; \
  766. _ezchip_macro_read_value_ &= 0xff;\
  767. }
  768. #define _SET_SYSCON_REG_register35_SCFG_spi2ahb_mode(v) { \
  769. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register35_REG_ADDR); \
  770. _ezchip_macro_read_value_ &= ~(0x3); \
  771. _ezchip_macro_read_value_ |= (v&0x3); \
  772. MA_OUTW(syscon_sysmain_ctrl_register35_REG_ADDR,_ezchip_macro_read_value_); \
  773. }
  774. #define _GET_SYSCON_REG_register35_SCFG_spi2ahb_mode(_ezchip_macro_read_value_) { \
  775. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register35_REG_ADDR); \
  776. _ezchip_macro_read_value_ &= 0x3;\
  777. }
  778. #define _GET_SYSCON_REG_register36_spi2ahb_sleep(_ezchip_macro_read_value_) { \
  779. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register36_REG_ADDR); \
  780. _ezchip_macro_read_value_ &= 0x1;\
  781. }
  782. #define _SET_SYSCON_REG_register37_ezmst_SCFG_sram_config(v) { \
  783. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register37_REG_ADDR); \
  784. _ezchip_macro_read_value_ &= ~(0xFF); \
  785. _ezchip_macro_read_value_ |= (v&0xFF); \
  786. MA_OUTW(syscon_sysmain_ctrl_register37_REG_ADDR,_ezchip_macro_read_value_); \
  787. }
  788. #define _GET_SYSCON_REG_register37_ezmst_SCFG_sram_config(_ezchip_macro_read_value_) { \
  789. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register37_REG_ADDR); \
  790. _ezchip_macro_read_value_ &= 0xff;\
  791. }
  792. #define _SET_SYSCON_REG_register38_sec_SCFG_sram_cfg(v) { \
  793. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register38_REG_ADDR); \
  794. _ezchip_macro_read_value_ &= ~(0xFF); \
  795. _ezchip_macro_read_value_ |= (v&0xFF); \
  796. MA_OUTW(syscon_sysmain_ctrl_register38_REG_ADDR,_ezchip_macro_read_value_); \
  797. }
  798. #define _GET_SYSCON_REG_register38_sec_SCFG_sram_cfg(_ezchip_macro_read_value_) { \
  799. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register38_REG_ADDR); \
  800. _ezchip_macro_read_value_ &= 0xff;\
  801. }
  802. #define _SET_SYSCON_REG_register39_uart0_SCFG_sram_config(v) { \
  803. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register39_REG_ADDR); \
  804. _ezchip_macro_read_value_ &= ~(0xFF); \
  805. _ezchip_macro_read_value_ |= (v&0xFF); \
  806. MA_OUTW(syscon_sysmain_ctrl_register39_REG_ADDR,_ezchip_macro_read_value_); \
  807. }
  808. #define _GET_SYSCON_REG_register39_uart0_SCFG_sram_config(_ezchip_macro_read_value_) { \
  809. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register39_REG_ADDR); \
  810. _ezchip_macro_read_value_ &= 0xff;\
  811. }
  812. #define _SET_SYSCON_REG_register39_uart1_SCFG_sram_config(v) { \
  813. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register39_REG_ADDR); \
  814. _ezchip_macro_read_value_ &= ~(0xFF<<8); \
  815. _ezchip_macro_read_value_ |= (v&0xFF)<<8; \
  816. MA_OUTW(syscon_sysmain_ctrl_register39_REG_ADDR,_ezchip_macro_read_value_); \
  817. }
  818. #define _GET_SYSCON_REG_register39_uart1_SCFG_sram_config(_ezchip_macro_read_value_) { \
  819. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register39_REG_ADDR) >> 8; \
  820. _ezchip_macro_read_value_ &= 0xff;\
  821. }
  822. #define _GET_SYSCON_REG_register40_trng_secure_mode(_ezchip_macro_read_value_) { \
  823. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register40_REG_ADDR); \
  824. _ezchip_macro_read_value_ &= 0x1;\
  825. }
  826. #define _GET_SYSCON_REG_register40_trng_nonce_mode(_ezchip_macro_read_value_) { \
  827. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register40_REG_ADDR) >> 1; \
  828. _ezchip_macro_read_value_ &= 0x1;\
  829. }
  830. #define _SET_SYSCON_REG_SCFG_intC1_7to0_int_src1(v) { \
  831. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_intC1_7to0_REG_ADDR); \
  832. _ezchip_macro_read_value_ &= ~(0xFF); \
  833. _ezchip_macro_read_value_ |= (v&0xFF); \
  834. MA_OUTW(syscon_sysmain_ctrl_SCFG_intC1_7to0_REG_ADDR,_ezchip_macro_read_value_); \
  835. }
  836. #define _GET_SYSCON_REG_SCFG_intC1_7to0_int_src1(_ezchip_macro_read_value_) { \
  837. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_intC1_7to0_REG_ADDR); \
  838. _ezchip_macro_read_value_ &= 0xff;\
  839. }
  840. #define _SET_SYSCON_REG_SCFG_intC0_src15to8_int_src1(v) { \
  841. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_intC0_src15to8_REG_ADDR); \
  842. _ezchip_macro_read_value_ &= ~(0xFF); \
  843. _ezchip_macro_read_value_ |= (v&0xFF); \
  844. MA_OUTW(syscon_sysmain_ctrl_SCFG_intC0_src15to8_REG_ADDR,_ezchip_macro_read_value_); \
  845. }
  846. #define _GET_SYSCON_REG_SCFG_intC0_src15to8_int_src1(_ezchip_macro_read_value_) { \
  847. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_intC0_src15to8_REG_ADDR); \
  848. _ezchip_macro_read_value_ &= 0xff;\
  849. }
  850. #define _SET_SYSCON_REG_SCFG_intC0_src23to16_int_src1(v) { \
  851. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_intC0_src23to16_REG_ADDR); \
  852. _ezchip_macro_read_value_ &= ~(0xFF); \
  853. _ezchip_macro_read_value_ |= (v&0xFF); \
  854. MA_OUTW(syscon_sysmain_ctrl_SCFG_intC0_src23to16_REG_ADDR,_ezchip_macro_read_value_); \
  855. }
  856. #define _GET_SYSCON_REG_SCFG_intC0_src23to16_int_src1(_ezchip_macro_read_value_) { \
  857. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_intC0_src23to16_REG_ADDR); \
  858. _ezchip_macro_read_value_ &= 0xff;\
  859. }
  860. #define _SET_SYSCON_REG_SCFG_intC0_src31to24_int_src1(v) { \
  861. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_intC0_src31to24_REG_ADDR); \
  862. _ezchip_macro_read_value_ &= ~(0xFF); \
  863. _ezchip_macro_read_value_ |= (v&0xFF); \
  864. MA_OUTW(syscon_sysmain_ctrl_SCFG_intC0_src31to24_REG_ADDR,_ezchip_macro_read_value_); \
  865. }
  866. #define _GET_SYSCON_REG_SCFG_intC0_src31to24_int_src1(_ezchip_macro_read_value_) { \
  867. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_intC0_src31to24_REG_ADDR); \
  868. _ezchip_macro_read_value_ &= 0xff;\
  869. }
  870. #define _SET_SYSCON_REG_register47_e24_reset_vector(v) { \
  871. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register47_REG_ADDR); \
  872. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  873. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  874. MA_OUTW(syscon_sysmain_ctrl_register47_REG_ADDR,_ezchip_macro_read_value_); \
  875. }
  876. #define _GET_SYSCON_REG_register47_e24_reset_vector(_ezchip_macro_read_value_) { \
  877. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register47_REG_ADDR); \
  878. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  879. }
  880. #define _SET_SYSCON_REG_register48_SCFG_qspi_sclk_dlychain_sel(v) { \
  881. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register48_REG_ADDR); \
  882. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  883. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  884. MA_OUTW(syscon_sysmain_ctrl_register48_REG_ADDR,_ezchip_macro_read_value_); \
  885. }
  886. #define _GET_SYSCON_REG_register48_SCFG_qspi_sclk_dlychain_sel(_ezchip_macro_read_value_) { \
  887. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register48_REG_ADDR); \
  888. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  889. }
  890. #define _SET_SYSCON_REG_register52_SCFG_gmac_rxclk_dlychain_sel(v) { \
  891. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register52_REG_ADDR); \
  892. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  893. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  894. MA_OUTW(syscon_sysmain_ctrl_register52_REG_ADDR,_ezchip_macro_read_value_); \
  895. }
  896. #define _GET_SYSCON_REG_register52_SCFG_gmac_rxclk_dlychain_sel(_ezchip_macro_read_value_) { \
  897. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register52_REG_ADDR); \
  898. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  899. }
  900. #define _SET_SYSCON_REG_register49_SCFG_gmac_gtxclk_dlychain_sel(v) { \
  901. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register49_REG_ADDR); \
  902. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  903. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  904. MA_OUTW(syscon_sysmain_ctrl_register49_REG_ADDR,_ezchip_macro_read_value_); \
  905. }
  906. #define _GET_SYSCON_REG_register49_SCFG_gmac_gtxclk_dlychain_sel(_ezchip_macro_read_value_) { \
  907. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register49_REG_ADDR); \
  908. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  909. }
  910. #define _SET_SYSCON_REG_register50_SCFG_sdio0_cclk_dlychain_sel(v) { \
  911. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register50_REG_ADDR); \
  912. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  913. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  914. MA_OUTW(syscon_sysmain_ctrl_register50_REG_ADDR,_ezchip_macro_read_value_); \
  915. }
  916. #define _GET_SYSCON_REG_register50_SCFG_sdio0_cclk_dlychain_sel(_ezchip_macro_read_value_) { \
  917. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register50_REG_ADDR); \
  918. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  919. }
  920. #define _SET_SYSCON_REG_register51_SCFG_sdio1_cclk_dlychain_sel(v) { \
  921. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register51_REG_ADDR); \
  922. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  923. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  924. MA_OUTW(syscon_sysmain_ctrl_register51_REG_ADDR,_ezchip_macro_read_value_); \
  925. }
  926. #define _GET_SYSCON_REG_register51_SCFG_sdio1_cclk_dlychain_sel(_ezchip_macro_read_value_) { \
  927. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register51_REG_ADDR); \
  928. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  929. }
  930. #define _SET_SYSCON_REG_register66_SCFG_axi_cache_sel(v) { \
  931. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register66_REG_ADDR); \
  932. _ezchip_macro_read_value_ &= ~(0xFF); \
  933. _ezchip_macro_read_value_ |= (v&0xFF); \
  934. MA_OUTW(syscon_sysmain_ctrl_register66_REG_ADDR,_ezchip_macro_read_value_); \
  935. }
  936. #define _GET_SYSCON_REG_register66_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  937. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register66_REG_ADDR); \
  938. _ezchip_macro_read_value_ &= 0xff;\
  939. }
  940. #define _SET_SYSCON_REG_register66_SCFG_default_arcache(v) { \
  941. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register66_REG_ADDR); \
  942. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  943. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  944. MA_OUTW(syscon_sysmain_ctrl_register66_REG_ADDR,_ezchip_macro_read_value_); \
  945. }
  946. #define _GET_SYSCON_REG_register66_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  947. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register66_REG_ADDR) >> 8; \
  948. _ezchip_macro_read_value_ &= 0xf;\
  949. }
  950. #define _SET_SYSCON_REG_register66_SCFG_default_awcache(v) { \
  951. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register66_REG_ADDR); \
  952. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  953. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  954. MA_OUTW(syscon_sysmain_ctrl_register66_REG_ADDR,_ezchip_macro_read_value_); \
  955. }
  956. #define _GET_SYSCON_REG_register66_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  957. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register66_REG_ADDR) >> 12; \
  958. _ezchip_macro_read_value_ &= 0xf;\
  959. }
  960. #define _SET_SYSCON_REG_register53_SCFG_axi_cache_sel(v) { \
  961. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register53_REG_ADDR); \
  962. _ezchip_macro_read_value_ &= ~(0xFF); \
  963. _ezchip_macro_read_value_ |= (v&0xFF); \
  964. MA_OUTW(syscon_sysmain_ctrl_register53_REG_ADDR,_ezchip_macro_read_value_); \
  965. }
  966. #define _GET_SYSCON_REG_register53_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  967. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register53_REG_ADDR); \
  968. _ezchip_macro_read_value_ &= 0xff;\
  969. }
  970. #define _SET_SYSCON_REG_register53_SCFG_default_arcache(v) { \
  971. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register53_REG_ADDR); \
  972. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  973. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  974. MA_OUTW(syscon_sysmain_ctrl_register53_REG_ADDR,_ezchip_macro_read_value_); \
  975. }
  976. #define _GET_SYSCON_REG_register53_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  977. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register53_REG_ADDR) >> 8; \
  978. _ezchip_macro_read_value_ &= 0xf;\
  979. }
  980. #define _SET_SYSCON_REG_register53_SCFG_default_awcache(v) { \
  981. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register53_REG_ADDR); \
  982. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  983. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  984. MA_OUTW(syscon_sysmain_ctrl_register53_REG_ADDR,_ezchip_macro_read_value_); \
  985. }
  986. #define _GET_SYSCON_REG_register53_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  987. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register53_REG_ADDR) >> 12; \
  988. _ezchip_macro_read_value_ &= 0xf;\
  989. }
  990. #define _SET_SYSCON_REG_register54_SCFG_axi_cache_sel(v) { \
  991. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register54_REG_ADDR); \
  992. _ezchip_macro_read_value_ &= ~(0xFF); \
  993. _ezchip_macro_read_value_ |= (v&0xFF); \
  994. MA_OUTW(syscon_sysmain_ctrl_register54_REG_ADDR,_ezchip_macro_read_value_); \
  995. }
  996. #define _GET_SYSCON_REG_register54_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  997. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register54_REG_ADDR); \
  998. _ezchip_macro_read_value_ &= 0xff;\
  999. }
  1000. #define _SET_SYSCON_REG_register54_SCFG_default_arcache(v) { \
  1001. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register54_REG_ADDR); \
  1002. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1003. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1004. MA_OUTW(syscon_sysmain_ctrl_register54_REG_ADDR,_ezchip_macro_read_value_); \
  1005. }
  1006. #define _GET_SYSCON_REG_register54_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1007. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register54_REG_ADDR) >> 8; \
  1008. _ezchip_macro_read_value_ &= 0xf;\
  1009. }
  1010. #define _SET_SYSCON_REG_register54_SCFG_default_awcache(v) { \
  1011. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register54_REG_ADDR); \
  1012. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1013. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1014. MA_OUTW(syscon_sysmain_ctrl_register54_REG_ADDR,_ezchip_macro_read_value_); \
  1015. }
  1016. #define _GET_SYSCON_REG_register54_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1017. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register54_REG_ADDR) >> 12; \
  1018. _ezchip_macro_read_value_ &= 0xf;\
  1019. }
  1020. #define _SET_SYSCON_REG_register55_SCFG_axi_cache_sel(v) { \
  1021. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register55_REG_ADDR); \
  1022. _ezchip_macro_read_value_ &= ~(0xFF); \
  1023. _ezchip_macro_read_value_ |= (v&0xFF); \
  1024. MA_OUTW(syscon_sysmain_ctrl_register55_REG_ADDR,_ezchip_macro_read_value_); \
  1025. }
  1026. #define _GET_SYSCON_REG_register55_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1027. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register55_REG_ADDR); \
  1028. _ezchip_macro_read_value_ &= 0xff;\
  1029. }
  1030. #define _SET_SYSCON_REG_register55_SCFG_default_arcache(v) { \
  1031. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register55_REG_ADDR); \
  1032. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1033. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1034. MA_OUTW(syscon_sysmain_ctrl_register55_REG_ADDR,_ezchip_macro_read_value_); \
  1035. }
  1036. #define _GET_SYSCON_REG_register55_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1037. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register55_REG_ADDR) >> 8; \
  1038. _ezchip_macro_read_value_ &= 0xf;\
  1039. }
  1040. #define _SET_SYSCON_REG_register55_SCFG_default_awcache(v) { \
  1041. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register55_REG_ADDR); \
  1042. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1043. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1044. MA_OUTW(syscon_sysmain_ctrl_register55_REG_ADDR,_ezchip_macro_read_value_); \
  1045. }
  1046. #define _GET_SYSCON_REG_register55_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1047. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register55_REG_ADDR) >> 12; \
  1048. _ezchip_macro_read_value_ &= 0xf;\
  1049. }
  1050. #define _SET_SYSCON_REG_register56_SCFG_axi_cache_sel(v) { \
  1051. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register56_REG_ADDR); \
  1052. _ezchip_macro_read_value_ &= ~(0xFF); \
  1053. _ezchip_macro_read_value_ |= (v&0xFF); \
  1054. MA_OUTW(syscon_sysmain_ctrl_register56_REG_ADDR,_ezchip_macro_read_value_); \
  1055. }
  1056. #define _GET_SYSCON_REG_register56_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1057. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register56_REG_ADDR); \
  1058. _ezchip_macro_read_value_ &= 0xff;\
  1059. }
  1060. #define _SET_SYSCON_REG_register56_SCFG_default_arcache(v) { \
  1061. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register56_REG_ADDR); \
  1062. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1063. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1064. MA_OUTW(syscon_sysmain_ctrl_register56_REG_ADDR,_ezchip_macro_read_value_); \
  1065. }
  1066. #define _GET_SYSCON_REG_register56_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1067. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register56_REG_ADDR) >> 8; \
  1068. _ezchip_macro_read_value_ &= 0xf;\
  1069. }
  1070. #define _SET_SYSCON_REG_register56_SCFG_default_awcache(v) { \
  1071. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register56_REG_ADDR); \
  1072. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1073. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1074. MA_OUTW(syscon_sysmain_ctrl_register56_REG_ADDR,_ezchip_macro_read_value_); \
  1075. }
  1076. #define _GET_SYSCON_REG_register56_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1077. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register56_REG_ADDR) >> 12; \
  1078. _ezchip_macro_read_value_ &= 0xf;\
  1079. }
  1080. #define _SET_SYSCON_REG_register57_SCFG_axi_cache_sel(v) { \
  1081. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register57_REG_ADDR); \
  1082. _ezchip_macro_read_value_ &= ~(0xFF); \
  1083. _ezchip_macro_read_value_ |= (v&0xFF); \
  1084. MA_OUTW(syscon_sysmain_ctrl_register57_REG_ADDR,_ezchip_macro_read_value_); \
  1085. }
  1086. #define _GET_SYSCON_REG_register57_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1087. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register57_REG_ADDR); \
  1088. _ezchip_macro_read_value_ &= 0xff;\
  1089. }
  1090. #define _SET_SYSCON_REG_register57_SCFG_default_arcache(v) { \
  1091. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register57_REG_ADDR); \
  1092. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1093. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1094. MA_OUTW(syscon_sysmain_ctrl_register57_REG_ADDR,_ezchip_macro_read_value_); \
  1095. }
  1096. #define _GET_SYSCON_REG_register57_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1097. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register57_REG_ADDR) >> 8; \
  1098. _ezchip_macro_read_value_ &= 0xf;\
  1099. }
  1100. #define _SET_SYSCON_REG_register57_SCFG_default_awcache(v) { \
  1101. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register57_REG_ADDR); \
  1102. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1103. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1104. MA_OUTW(syscon_sysmain_ctrl_register57_REG_ADDR,_ezchip_macro_read_value_); \
  1105. }
  1106. #define _GET_SYSCON_REG_register57_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1107. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register57_REG_ADDR) >> 12; \
  1108. _ezchip_macro_read_value_ &= 0xf;\
  1109. }
  1110. #define _SET_SYSCON_REG_register58_SCFG_axi_cache_sel(v) { \
  1111. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register58_REG_ADDR); \
  1112. _ezchip_macro_read_value_ &= ~(0xFF); \
  1113. _ezchip_macro_read_value_ |= (v&0xFF); \
  1114. MA_OUTW(syscon_sysmain_ctrl_register58_REG_ADDR,_ezchip_macro_read_value_); \
  1115. }
  1116. #define _GET_SYSCON_REG_register58_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1117. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register58_REG_ADDR); \
  1118. _ezchip_macro_read_value_ &= 0xff;\
  1119. }
  1120. #define _SET_SYSCON_REG_register58_SCFG_default_arcache(v) { \
  1121. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register58_REG_ADDR); \
  1122. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1123. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1124. MA_OUTW(syscon_sysmain_ctrl_register58_REG_ADDR,_ezchip_macro_read_value_); \
  1125. }
  1126. #define _GET_SYSCON_REG_register58_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1127. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register58_REG_ADDR) >> 8; \
  1128. _ezchip_macro_read_value_ &= 0xf;\
  1129. }
  1130. #define _SET_SYSCON_REG_register58_SCFG_default_awcache(v) { \
  1131. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register58_REG_ADDR); \
  1132. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1133. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1134. MA_OUTW(syscon_sysmain_ctrl_register58_REG_ADDR,_ezchip_macro_read_value_); \
  1135. }
  1136. #define _GET_SYSCON_REG_register58_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1137. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register58_REG_ADDR) >> 12; \
  1138. _ezchip_macro_read_value_ &= 0xf;\
  1139. }
  1140. #define _SET_SYSCON_REG_register59_SCFG_axi_cache_sel(v) { \
  1141. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register59_REG_ADDR); \
  1142. _ezchip_macro_read_value_ &= ~(0xFF); \
  1143. _ezchip_macro_read_value_ |= (v&0xFF); \
  1144. MA_OUTW(syscon_sysmain_ctrl_register59_REG_ADDR,_ezchip_macro_read_value_); \
  1145. }
  1146. #define _GET_SYSCON_REG_register59_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1147. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register59_REG_ADDR); \
  1148. _ezchip_macro_read_value_ &= 0xff;\
  1149. }
  1150. #define _SET_SYSCON_REG_register59_SCFG_default_arcache(v) { \
  1151. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register59_REG_ADDR); \
  1152. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1153. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1154. MA_OUTW(syscon_sysmain_ctrl_register59_REG_ADDR,_ezchip_macro_read_value_); \
  1155. }
  1156. #define _GET_SYSCON_REG_register59_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1157. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register59_REG_ADDR) >> 8; \
  1158. _ezchip_macro_read_value_ &= 0xf;\
  1159. }
  1160. #define _SET_SYSCON_REG_register59_SCFG_default_awcache(v) { \
  1161. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register59_REG_ADDR); \
  1162. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1163. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1164. MA_OUTW(syscon_sysmain_ctrl_register59_REG_ADDR,_ezchip_macro_read_value_); \
  1165. }
  1166. #define _GET_SYSCON_REG_register59_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1167. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register59_REG_ADDR) >> 12; \
  1168. _ezchip_macro_read_value_ &= 0xf;\
  1169. }
  1170. #define _SET_SYSCON_REG_register60_SCFG_axi_cache_sel(v) { \
  1171. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register60_REG_ADDR); \
  1172. _ezchip_macro_read_value_ &= ~(0xFF); \
  1173. _ezchip_macro_read_value_ |= (v&0xFF); \
  1174. MA_OUTW(syscon_sysmain_ctrl_register60_REG_ADDR,_ezchip_macro_read_value_); \
  1175. }
  1176. #define _GET_SYSCON_REG_register60_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1177. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register60_REG_ADDR); \
  1178. _ezchip_macro_read_value_ &= 0xff;\
  1179. }
  1180. #define _SET_SYSCON_REG_register60_SCFG_default_arcache(v) { \
  1181. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register60_REG_ADDR); \
  1182. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1183. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1184. MA_OUTW(syscon_sysmain_ctrl_register60_REG_ADDR,_ezchip_macro_read_value_); \
  1185. }
  1186. #define _GET_SYSCON_REG_register60_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1187. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register60_REG_ADDR) >> 8; \
  1188. _ezchip_macro_read_value_ &= 0xf;\
  1189. }
  1190. #define _SET_SYSCON_REG_register60_SCFG_default_awcache(v) { \
  1191. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register60_REG_ADDR); \
  1192. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1193. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1194. MA_OUTW(syscon_sysmain_ctrl_register60_REG_ADDR,_ezchip_macro_read_value_); \
  1195. }
  1196. #define _GET_SYSCON_REG_register60_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1197. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register60_REG_ADDR) >> 12; \
  1198. _ezchip_macro_read_value_ &= 0xf;\
  1199. }
  1200. #define _SET_SYSCON_REG_register61_SCFG_axi_cache_sel(v) { \
  1201. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register61_REG_ADDR); \
  1202. _ezchip_macro_read_value_ &= ~(0xFF); \
  1203. _ezchip_macro_read_value_ |= (v&0xFF); \
  1204. MA_OUTW(syscon_sysmain_ctrl_register61_REG_ADDR,_ezchip_macro_read_value_); \
  1205. }
  1206. #define _GET_SYSCON_REG_register61_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1207. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register61_REG_ADDR); \
  1208. _ezchip_macro_read_value_ &= 0xff;\
  1209. }
  1210. #define _SET_SYSCON_REG_register61_SCFG_default_arcache(v) { \
  1211. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register61_REG_ADDR); \
  1212. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1213. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1214. MA_OUTW(syscon_sysmain_ctrl_register61_REG_ADDR,_ezchip_macro_read_value_); \
  1215. }
  1216. #define _GET_SYSCON_REG_register61_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1217. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register61_REG_ADDR) >> 8; \
  1218. _ezchip_macro_read_value_ &= 0xf;\
  1219. }
  1220. #define _SET_SYSCON_REG_register61_SCFG_default_awcache(v) { \
  1221. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register61_REG_ADDR); \
  1222. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1223. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1224. MA_OUTW(syscon_sysmain_ctrl_register61_REG_ADDR,_ezchip_macro_read_value_); \
  1225. }
  1226. #define _GET_SYSCON_REG_register61_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1227. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register61_REG_ADDR) >> 12; \
  1228. _ezchip_macro_read_value_ &= 0xf;\
  1229. }
  1230. #define _SET_SYSCON_REG_register62_SCFG_axi_cache_sel(v) { \
  1231. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register62_REG_ADDR); \
  1232. _ezchip_macro_read_value_ &= ~(0xFF); \
  1233. _ezchip_macro_read_value_ |= (v&0xFF); \
  1234. MA_OUTW(syscon_sysmain_ctrl_register62_REG_ADDR,_ezchip_macro_read_value_); \
  1235. }
  1236. #define _GET_SYSCON_REG_register62_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1237. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register62_REG_ADDR); \
  1238. _ezchip_macro_read_value_ &= 0xff;\
  1239. }
  1240. #define _SET_SYSCON_REG_register62_SCFG_default_arcache(v) { \
  1241. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register62_REG_ADDR); \
  1242. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1243. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1244. MA_OUTW(syscon_sysmain_ctrl_register62_REG_ADDR,_ezchip_macro_read_value_); \
  1245. }
  1246. #define _GET_SYSCON_REG_register62_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1247. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register62_REG_ADDR) >> 8; \
  1248. _ezchip_macro_read_value_ &= 0xf;\
  1249. }
  1250. #define _SET_SYSCON_REG_register62_SCFG_default_awcache(v) { \
  1251. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register62_REG_ADDR); \
  1252. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1253. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1254. MA_OUTW(syscon_sysmain_ctrl_register62_REG_ADDR,_ezchip_macro_read_value_); \
  1255. }
  1256. #define _GET_SYSCON_REG_register62_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1257. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register62_REG_ADDR) >> 12; \
  1258. _ezchip_macro_read_value_ &= 0xf;\
  1259. }
  1260. #define _SET_SYSCON_REG_register63_SCFG_axi_cache_sel(v) { \
  1261. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register63_REG_ADDR); \
  1262. _ezchip_macro_read_value_ &= ~(0xFF); \
  1263. _ezchip_macro_read_value_ |= (v&0xFF); \
  1264. MA_OUTW(syscon_sysmain_ctrl_register63_REG_ADDR,_ezchip_macro_read_value_); \
  1265. }
  1266. #define _GET_SYSCON_REG_register63_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1267. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register63_REG_ADDR); \
  1268. _ezchip_macro_read_value_ &= 0xff;\
  1269. }
  1270. #define _SET_SYSCON_REG_register63_SCFG_default_arcache(v) { \
  1271. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register63_REG_ADDR); \
  1272. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1273. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1274. MA_OUTW(syscon_sysmain_ctrl_register63_REG_ADDR,_ezchip_macro_read_value_); \
  1275. }
  1276. #define _GET_SYSCON_REG_register63_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1277. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register63_REG_ADDR) >> 8; \
  1278. _ezchip_macro_read_value_ &= 0xf;\
  1279. }
  1280. #define _SET_SYSCON_REG_register63_SCFG_default_awcache(v) { \
  1281. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register63_REG_ADDR); \
  1282. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1283. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1284. MA_OUTW(syscon_sysmain_ctrl_register63_REG_ADDR,_ezchip_macro_read_value_); \
  1285. }
  1286. #define _GET_SYSCON_REG_register63_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1287. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register63_REG_ADDR) >> 12; \
  1288. _ezchip_macro_read_value_ &= 0xf;\
  1289. }
  1290. #define _SET_SYSCON_REG_register64_SCFG_axi_cache_sel(v) { \
  1291. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register64_REG_ADDR); \
  1292. _ezchip_macro_read_value_ &= ~(0xFF); \
  1293. _ezchip_macro_read_value_ |= (v&0xFF); \
  1294. MA_OUTW(syscon_sysmain_ctrl_register64_REG_ADDR,_ezchip_macro_read_value_); \
  1295. }
  1296. #define _GET_SYSCON_REG_register64_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1297. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register64_REG_ADDR); \
  1298. _ezchip_macro_read_value_ &= 0xff;\
  1299. }
  1300. #define _SET_SYSCON_REG_register64_SCFG_default_arcache(v) { \
  1301. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register64_REG_ADDR); \
  1302. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1303. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1304. MA_OUTW(syscon_sysmain_ctrl_register64_REG_ADDR,_ezchip_macro_read_value_); \
  1305. }
  1306. #define _GET_SYSCON_REG_register64_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1307. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register64_REG_ADDR) >> 8; \
  1308. _ezchip_macro_read_value_ &= 0xf;\
  1309. }
  1310. #define _SET_SYSCON_REG_register64_SCFG_default_awcache(v) { \
  1311. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register64_REG_ADDR); \
  1312. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1313. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1314. MA_OUTW(syscon_sysmain_ctrl_register64_REG_ADDR,_ezchip_macro_read_value_); \
  1315. }
  1316. #define _GET_SYSCON_REG_register64_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1317. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register64_REG_ADDR) >> 12; \
  1318. _ezchip_macro_read_value_ &= 0xf;\
  1319. }
  1320. #define _SET_SYSCON_REG_register65_SCFG_axi_cache_sel(v) { \
  1321. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register65_REG_ADDR); \
  1322. _ezchip_macro_read_value_ &= ~(0xFF); \
  1323. _ezchip_macro_read_value_ |= (v&0xFF); \
  1324. MA_OUTW(syscon_sysmain_ctrl_register65_REG_ADDR,_ezchip_macro_read_value_); \
  1325. }
  1326. #define _GET_SYSCON_REG_register65_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1327. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register65_REG_ADDR); \
  1328. _ezchip_macro_read_value_ &= 0xff;\
  1329. }
  1330. #define _SET_SYSCON_REG_register65_SCFG_default_arcache(v) { \
  1331. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register65_REG_ADDR); \
  1332. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1333. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1334. MA_OUTW(syscon_sysmain_ctrl_register65_REG_ADDR,_ezchip_macro_read_value_); \
  1335. }
  1336. #define _GET_SYSCON_REG_register65_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1337. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register65_REG_ADDR) >> 8; \
  1338. _ezchip_macro_read_value_ &= 0xf;\
  1339. }
  1340. #define _SET_SYSCON_REG_register65_SCFG_default_awcache(v) { \
  1341. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register65_REG_ADDR); \
  1342. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1343. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1344. MA_OUTW(syscon_sysmain_ctrl_register65_REG_ADDR,_ezchip_macro_read_value_); \
  1345. }
  1346. #define _GET_SYSCON_REG_register65_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1347. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register65_REG_ADDR) >> 12; \
  1348. _ezchip_macro_read_value_ &= 0xf;\
  1349. }
  1350. #define _SET_SYSCON_REG_register68_SCFG_disable_u74_memaxi_remap(v) { \
  1351. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register68_REG_ADDR); \
  1352. _ezchip_macro_read_value_ &= ~(0x1); \
  1353. _ezchip_macro_read_value_ |= (v&0x1); \
  1354. MA_OUTW(syscon_sysmain_ctrl_register68_REG_ADDR,_ezchip_macro_read_value_); \
  1355. }
  1356. #define _GET_SYSCON_REG_register68_SCFG_disable_u74_memaxi_remap(_ezchip_macro_read_value_) { \
  1357. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register68_REG_ADDR); \
  1358. _ezchip_macro_read_value_ &= 0x1;\
  1359. }
  1360. #define _SET_SYSCON_REG_register67_SCFG_axi_cache_sel(v) { \
  1361. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register67_REG_ADDR); \
  1362. _ezchip_macro_read_value_ &= ~(0xFF); \
  1363. _ezchip_macro_read_value_ |= (v&0xFF); \
  1364. MA_OUTW(syscon_sysmain_ctrl_register67_REG_ADDR,_ezchip_macro_read_value_); \
  1365. }
  1366. #define _GET_SYSCON_REG_register67_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1367. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register67_REG_ADDR); \
  1368. _ezchip_macro_read_value_ &= 0xff;\
  1369. }
  1370. #define _SET_SYSCON_REG_register67_SCFG_default_arcache(v) { \
  1371. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register67_REG_ADDR); \
  1372. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1373. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1374. MA_OUTW(syscon_sysmain_ctrl_register67_REG_ADDR,_ezchip_macro_read_value_); \
  1375. }
  1376. #define _GET_SYSCON_REG_register67_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1377. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register67_REG_ADDR) >> 8; \
  1378. _ezchip_macro_read_value_ &= 0xf;\
  1379. }
  1380. #define _SET_SYSCON_REG_register67_SCFG_default_awcache(v) { \
  1381. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register67_REG_ADDR); \
  1382. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1383. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1384. MA_OUTW(syscon_sysmain_ctrl_register67_REG_ADDR,_ezchip_macro_read_value_); \
  1385. }
  1386. #define _GET_SYSCON_REG_register67_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1387. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register67_REG_ADDR) >> 12; \
  1388. _ezchip_macro_read_value_ &= 0xf;\
  1389. }
  1390. #define _SET_SYSCON_REG_register69_core1_en(v) { \
  1391. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register69_REG_ADDR); \
  1392. _ezchip_macro_read_value_ &= ~(0x1); \
  1393. _ezchip_macro_read_value_ |= (v&0x1); \
  1394. MA_OUTW(syscon_sysmain_ctrl_register69_REG_ADDR,_ezchip_macro_read_value_); \
  1395. }
  1396. #define _GET_SYSCON_REG_register69_core1_en(_ezchip_macro_read_value_) { \
  1397. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register69_REG_ADDR); \
  1398. _ezchip_macro_read_value_ &= 0x1;\
  1399. }
  1400. #define _SET_SYSCON_REG_register70_SCFG_boot_mode(v) { \
  1401. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register70_REG_ADDR); \
  1402. _ezchip_macro_read_value_ &= ~(0x1); \
  1403. _ezchip_macro_read_value_ |= (v&0x1); \
  1404. MA_OUTW(syscon_sysmain_ctrl_register70_REG_ADDR,_ezchip_macro_read_value_); \
  1405. }
  1406. #define _GET_SYSCON_REG_register70_SCFG_boot_mode(_ezchip_macro_read_value_) { \
  1407. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register70_REG_ADDR); \
  1408. _ezchip_macro_read_value_ &= 0x1;\
  1409. }
  1410. #define _GET_SYSCON_REG_register70_SCFG_u74_IOPAD_bootmode(_ezchip_macro_read_value_) { \
  1411. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register70_REG_ADDR) >> 1; \
  1412. _ezchip_macro_read_value_ &= 0x1;\
  1413. }
  1414. #define _SET_SYSCON_REG_register71_SCFG_u74_reset_vector(v) { \
  1415. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register71_REG_ADDR); \
  1416. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1417. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1418. MA_OUTW(syscon_sysmain_ctrl_register71_REG_ADDR,_ezchip_macro_read_value_); \
  1419. }
  1420. #define _GET_SYSCON_REG_register71_SCFG_u74_reset_vector(_ezchip_macro_read_value_) { \
  1421. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register71_REG_ADDR); \
  1422. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1423. }
  1424. #define _GET_SYSCON_REG_register72_u74_boot_device_sel(_ezchip_macro_read_value_) { \
  1425. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register72_REG_ADDR); \
  1426. _ezchip_macro_read_value_ &= 0x7;\
  1427. }
  1428. #endif //_SYSCON_SYSMAIN_CTRL_MACRO_H_