sys.h 2.0 KB

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  1. #ifndef SYS_H_
  2. #define SYS_H_
  3. /*********************************** sys clock************************/
  4. #define QSPI_CLK 100000000
  5. #define QSPI_REF_CLK 250000000
  6. #define DEFAULT_SD_BOOT_LOAD_BLOCK 1000
  7. #define DEFAULT_SPI_BOOT_START_ADDR 1
  8. #define DEFAULT_SPI_BOOT_SIZE_ADDR 0x0
  9. #define DEFAULT_SPI_BOOT_LOAD_PAGES 512
  10. // QSPI
  11. #define QSPI_BASE_ADDR 0x11860000
  12. //CADENCE QSPI AHB
  13. #define QSPI_BASE_AHB_ADDR 0x20000000
  14. // SDIO0
  15. #define SDIO0_BASE_ADDR 0x10000000
  16. // SDIO1
  17. #define SDIO1_BASE_ADDR 0x10010000
  18. // GPIO
  19. #define GPIO_BASE_ADDR 0x11910000///0xA9060000
  20. #define EZGPIO_FULLMUX_BASE_ADDR 0x11910000
  21. #define RSTGEN_BASE_ADDR 0x11840000
  22. #define CLKGEN_BASE_ADDR 0x11800000
  23. // CLKGEN
  24. #define VIC_CLKGEN_TOP_SV_BASE_ADDR 0x11800000///0xA9090000
  25. // RSTGEN
  26. #define VIC_RSTGEN_BASE_ADDR 0x11840000///0xA90A0000
  27. #define SYSCON_IOPAD_CTRL_BASE_ADDR 0x11858000
  28. // SYSCON
  29. #define SYSCON_SYSMAIN_CTRL_BASE_ADDR 0x11850000
  30. // HS-UART0
  31. #define UART0_HS_BASE_ADDR 0x11870000
  32. // HS-UART1
  33. #define UART1_HS_BASE_ADDR 0x11880000
  34. // UART2
  35. #define UART2_BASE_ADDR 0x12430000
  36. // UART3
  37. #define UART3_BASE_ADDR 0x12440000
  38. /*Reserved information:
  39. *second boot:64K 0x0 - 0xffff
  40. *ddr init:64K 0x10000 - 0x1ffff
  41. *uboot:1M 0x20000 - 0x11ffff
  42. *kernel:25M 0x120000 - 0x1a1ffff
  43. */
  44. /*Reserved information:
  45. *second boot:32K 0x0 - 0x7fff
  46. *ddr init:50K 0x8000 - 0x147ff
  47. *uboot:500K 0x14800 - 0x917ff
  48. *kernel:25M 0x130000 - 0x1a3ffff
  49. */
  50. /*DDR bin file */
  51. #define DEFAULT_DDR_ADDR 0x18080000
  52. #define DEFAULT_DDR_OFFSET 0x100
  53. /*uboot bin file*/
  54. #define DEFAULT_UBOOT_ADDR 0x80000000
  55. #define DEFAULT_UBOOT_OFFSET 0x200
  56. /*kernel image file*/
  57. #define DEFAULT_KERNEL_ADDR 0xa0000000
  58. #define DEFAULT_KERNEL_OFFSET 0x1200
  59. #define FLASH_SECONDBOOT_START_ADDR 0
  60. #define FLASH_DDRINIT_START_ADDR 0x10000
  61. #define FLASH_UBOOT_START_ADDR 0x20000
  62. #define DEFAULT_BOOT_LOAD_ADDR 0x80000000
  63. #endif