clkgen_ctrl_macro.h 173 KB

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  1. /******************************************************************
  2. *
  3. * clkgen controller C MACRO generated by ezchip
  4. *
  5. ******************************************************************/
  6. #ifndef _CLKGEN_MACRO_H_
  7. #define _CLKGEN_MACRO_H_
  8. //#define CLKGEN_BASE_ADDR 0x0
  9. #define clk_cpundbus_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x0
  10. #define clk_dla_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x4
  11. #define clk_dsp_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x8
  12. #define clk_gmacusb_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xC
  13. #define clk_perh0_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x10
  14. #define clk_perh1_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x14
  15. #define clk_vin_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x18
  16. #define clk_vout_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1C
  17. #define clk_audio_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x20
  18. #define clk_cdechifi4_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x24
  19. #define clk_cdec_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x28
  20. #define clk_voutbus_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2C
  21. #define clk_cpunbus_root_div_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x30
  22. #define clk_dsp_root_div_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x34
  23. #define clk_perh0_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x38
  24. #define clk_perh1_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x3C
  25. #define clk_pll0_testout_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x40
  26. #define clk_pll1_testout_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x44
  27. #define clk_pll2_testout_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x48
  28. #define clk_pll2_refclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x4C
  29. #define clk_cpu_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x50
  30. #define clk_cpu_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x54
  31. #define clk_ahb_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x58
  32. #define clk_apb1_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x5C
  33. #define clk_apb2_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x60
  34. #define clk_dom3ahb_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x64
  35. #define clk_dom7ahb_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x68
  36. #define clk_u74_core0_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x6C
  37. #define clk_u74_core1_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x70
  38. #define clk_u74_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x74
  39. #define clk_u74rtc_toggle_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x78
  40. #define clk_sgdma2p_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x7C
  41. #define clk_dma2pnoc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x80
  42. #define clk_sgdma2p_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x84
  43. #define clk_dla_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x88
  44. #define clk_dla_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x8C
  45. #define clk_dlanoc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x90
  46. #define clk_dla_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x94
  47. #define clk_vp6_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x98
  48. #define clk_vp6bus_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x9C
  49. #define clk_vp6_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xA0
  50. #define clk_vcdecbus_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xA4
  51. #define clk_vdec_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xA8
  52. #define clk_vdec_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xAC
  53. #define clk_vdecbrg_mainclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xB0
  54. #define clk_vdec_bclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xB4
  55. #define clk_vdec_cclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xB8
  56. #define clk_vdec_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xBC
  57. #define clk_jpeg_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xC0
  58. #define clk_jpeg_cclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xC4
  59. #define clk_jpeg_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xC8
  60. #define clk_gc300_2x_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xCC
  61. #define clk_gc300_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xD0
  62. #define clk_jpcgc300_axibus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xD4
  63. #define clk_gc300_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xD8
  64. #define clk_jpcgc300_mainclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xDC
  65. #define clk_venc_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xE0
  66. #define clk_venc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xE4
  67. #define clk_vencbrg_mainclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xE8
  68. #define clk_venc_bclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xEC
  69. #define clk_venc_cclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xF0
  70. #define clk_venc_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xF4
  71. #define clk_ddrpll_div2_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xF8
  72. #define clk_ddrpll_div4_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xFC
  73. #define clk_ddrpll_div8_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x100
  74. #define clk_ddrosc_div2_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x104
  75. #define clk_ddrc0_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x108
  76. #define clk_ddrc1_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x10C
  77. #define clk_ddrphy_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x110
  78. #define clk_noc_rob_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x114
  79. #define clk_noc_cog_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x118
  80. #define clk_nne_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x11C
  81. #define clk_nnebus_src1_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x120
  82. #define clk_nne_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x124
  83. #define clk_nne_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x128
  84. #define clk_nnenoc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x12C
  85. #define clk_dlaslv_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x130
  86. #define clk_dspx2c_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x134
  87. #define clk_hifi4_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x138
  88. #define clk_hifi4_corefree_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x13C
  89. #define clk_hifi4_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x140
  90. #define clk_hifi4_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x144
  91. #define clk_hifi4_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x148
  92. #define clk_hifi4noc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x14C
  93. #define clk_sgdma1p_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x150
  94. #define clk_sgdma1p_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x154
  95. #define clk_dma1p_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x158
  96. #define clk_x2c_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x15C
  97. #define clk_usb_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x160
  98. #define clk_usb_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x164
  99. #define clk_usbnoc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x168
  100. #define clk_usbphy_rootdiv_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x16C
  101. #define clk_usbphy_125m_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x170
  102. #define clk_usbphy_plldiv25m_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x174
  103. #define clk_usbphy_25m_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x178
  104. #define clk_audio_div_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x17C
  105. #define clk_audio_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x180
  106. #define clk_audio_12288_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x184
  107. #define clk_vin_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x188
  108. #define clk_isp0_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x18C
  109. #define clk_isp0_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x190
  110. #define clk_isp0noc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x194
  111. #define clk_ispslv_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x198
  112. #define clk_isp1_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x19C
  113. #define clk_isp1_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1A0
  114. #define clk_isp1noc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1A4
  115. #define clk_vin_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1A8
  116. #define clk_vin_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1AC
  117. #define clk_vinnoc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1B0
  118. #define clk_vout_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1B4
  119. #define clk_dispbus_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1B8
  120. #define clk_disp_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1BC
  121. #define clk_disp_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1C0
  122. #define clk_dispnoc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1C4
  123. #define clk_sdio0_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1C8
  124. #define clk_sdio0_cclkint_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1CC
  125. #define clk_sdio0_cclkint_inv_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1D0
  126. #define clk_sdio1_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1D4
  127. #define clk_sdio1_cclkint_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1D8
  128. #define clk_sdio1_cclkint_inv_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1DC
  129. #define clk_gmac_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1E0
  130. #define clk_gmac_root_div_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1E4
  131. #define clk_gmac_ptp_refclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1E8
  132. #define clk_gmac_gtxclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1EC
  133. #define clk_gmac_rmii_txclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1F0
  134. #define clk_gmac_rmii_rxclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1F4
  135. #define clk_gmac_tx_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1F8
  136. #define clk_gmac_tx_inv_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1FC
  137. #define clk_gmac_rx_pre_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x200
  138. #define clk_gmac_rx_inv_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x204
  139. #define clk_gmac_rmii_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x208
  140. #define clk_gmac_tophyref_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x20C
  141. #define clk_spi2ahb_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x210
  142. #define clk_spi2ahb_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x214
  143. #define clk_ezmaster_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x218
  144. #define clk_e24_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x21C
  145. #define clk_e24rtc_toggle_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x220
  146. #define clk_qspi_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x224
  147. #define clk_qspi_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x228
  148. #define clk_qspi_refclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x22C
  149. #define clk_sec_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x230
  150. #define clk_aes_clk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x234
  151. #define clk_sha_clk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x238
  152. #define clk_pka_clk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x23C
  153. #define clk_trng_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x240
  154. #define clk_otp_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x244
  155. #define clk_uart0_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x248
  156. #define clk_uart0_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x24C
  157. #define clk_uart1_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x250
  158. #define clk_uart1_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x254
  159. #define clk_spi0_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x258
  160. #define clk_spi0_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x25C
  161. #define clk_spi1_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x260
  162. #define clk_spi1_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x264
  163. #define clk_i2c0_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x268
  164. #define clk_i2c0_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x26C
  165. #define clk_i2c1_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x270
  166. #define clk_i2c1_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x274
  167. #define clk_gpio_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x278
  168. #define clk_uart2_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x27C
  169. #define clk_uart2_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x280
  170. #define clk_uart3_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x284
  171. #define clk_uart3_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x288
  172. #define clk_spi2_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x28C
  173. #define clk_spi2_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x290
  174. #define clk_spi3_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x294
  175. #define clk_spi3_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x298
  176. #define clk_i2c2_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x29C
  177. #define clk_i2c2_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2A0
  178. #define clk_i2c3_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2A4
  179. #define clk_i2c3_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2A8
  180. #define clk_wdtimer_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2AC
  181. #define clk_wdt_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2B0
  182. #define clk_timer0_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2B4
  183. #define clk_timer1_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2B8
  184. #define clk_timer2_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2BC
  185. #define clk_timer3_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2C0
  186. #define clk_timer4_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2C4
  187. #define clk_timer5_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2C8
  188. #define clk_timer6_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2CC
  189. #define clk_vp6intc_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2D0
  190. #define clk_pwm_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2D4
  191. #define clk_msi_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2D8
  192. #define clk_temp_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2DC
  193. #define clk_temp_sense_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2E0
  194. #define clk_syserr_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2E4
  195. #define _ENABLE_CLOCK_clk_cpundbus_root_ {}
  196. #define _SWITCH_CLOCK_clk_cpundbus_root_SOURCE_clk_osc_sys_ { \
  197. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cpundbus_root_ctrl_REG_ADDR); \
  198. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  199. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  200. MA_OUTW(clk_cpundbus_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  201. }
  202. #define _SWITCH_CLOCK_clk_cpundbus_root_SOURCE_clk_pll0_out_ { \
  203. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cpundbus_root_ctrl_REG_ADDR); \
  204. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  205. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  206. MA_OUTW(clk_cpundbus_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  207. }
  208. #define _SWITCH_CLOCK_clk_cpundbus_root_SOURCE_clk_pll1_out_ { \
  209. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cpundbus_root_ctrl_REG_ADDR); \
  210. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  211. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  212. MA_OUTW(clk_cpundbus_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  213. }
  214. #define _SWITCH_CLOCK_clk_cpundbus_root_SOURCE_clk_pll2_out_ { \
  215. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cpundbus_root_ctrl_REG_ADDR); \
  216. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  217. _ezchip_macro_read_value_ |= (0x3&0x3)<<24; \
  218. MA_OUTW(clk_cpundbus_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  219. }
  220. #define _GET_CLOCK_SOURCE_STATUS_clk_cpundbus_root_(_ezchip_macro_read_value_) { \
  221. _ezchip_macro_read_value_=MA_INW(clk_cpundbus_root_ctrl_REG_ADDR) >> 24; \
  222. _ezchip_macro_read_value_ &= 0x3;\
  223. }
  224. #define _ENABLE_CLOCK_clk_dla_root_ {}
  225. #define _SWITCH_CLOCK_clk_dla_root_SOURCE_clk_osc_sys_ { \
  226. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_root_ctrl_REG_ADDR); \
  227. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  228. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  229. MA_OUTW(clk_dla_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  230. }
  231. #define _SWITCH_CLOCK_clk_dla_root_SOURCE_clk_pll1_out_ { \
  232. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_root_ctrl_REG_ADDR); \
  233. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  234. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  235. MA_OUTW(clk_dla_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  236. }
  237. #define _SWITCH_CLOCK_clk_dla_root_SOURCE_clk_pll2_out_ { \
  238. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_root_ctrl_REG_ADDR); \
  239. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  240. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  241. MA_OUTW(clk_dla_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  242. }
  243. #define _GET_CLOCK_SOURCE_STATUS_clk_dla_root_(_ezchip_macro_read_value_) { \
  244. _ezchip_macro_read_value_=MA_INW(clk_dla_root_ctrl_REG_ADDR) >> 24; \
  245. _ezchip_macro_read_value_ &= 0x3;\
  246. }
  247. #define _ENABLE_CLOCK_clk_dsp_root_ {}
  248. #define _SWITCH_CLOCK_clk_dsp_root_SOURCE_clk_osc_sys_ { \
  249. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dsp_root_ctrl_REG_ADDR); \
  250. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  251. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  252. MA_OUTW(clk_dsp_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  253. }
  254. #define _SWITCH_CLOCK_clk_dsp_root_SOURCE_clk_pll0_out_ { \
  255. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dsp_root_ctrl_REG_ADDR); \
  256. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  257. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  258. MA_OUTW(clk_dsp_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  259. }
  260. #define _SWITCH_CLOCK_clk_dsp_root_SOURCE_clk_pll1_out_ { \
  261. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dsp_root_ctrl_REG_ADDR); \
  262. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  263. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  264. MA_OUTW(clk_dsp_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  265. }
  266. #define _SWITCH_CLOCK_clk_dsp_root_SOURCE_clk_pll2_out_ { \
  267. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dsp_root_ctrl_REG_ADDR); \
  268. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  269. _ezchip_macro_read_value_ |= (0x3&0x3)<<24; \
  270. MA_OUTW(clk_dsp_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  271. }
  272. #define _GET_CLOCK_SOURCE_STATUS_clk_dsp_root_(_ezchip_macro_read_value_) { \
  273. _ezchip_macro_read_value_=MA_INW(clk_dsp_root_ctrl_REG_ADDR) >> 24; \
  274. _ezchip_macro_read_value_ &= 0x3;\
  275. }
  276. #define _ENABLE_CLOCK_clk_gmacusb_root_ {}
  277. #define _SWITCH_CLOCK_clk_gmacusb_root_SOURCE_clk_osc_sys_ { \
  278. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmacusb_root_ctrl_REG_ADDR); \
  279. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  280. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  281. MA_OUTW(clk_gmacusb_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  282. }
  283. #define _SWITCH_CLOCK_clk_gmacusb_root_SOURCE_clk_pll0_out_ { \
  284. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmacusb_root_ctrl_REG_ADDR); \
  285. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  286. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  287. MA_OUTW(clk_gmacusb_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  288. }
  289. #define _SWITCH_CLOCK_clk_gmacusb_root_SOURCE_clk_pll2_out_ { \
  290. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmacusb_root_ctrl_REG_ADDR); \
  291. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  292. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  293. MA_OUTW(clk_gmacusb_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  294. }
  295. #define _GET_CLOCK_SOURCE_STATUS_clk_gmacusb_root_(_ezchip_macro_read_value_) { \
  296. _ezchip_macro_read_value_=MA_INW(clk_gmacusb_root_ctrl_REG_ADDR) >> 24; \
  297. _ezchip_macro_read_value_ &= 0x3;\
  298. }
  299. #define _ENABLE_CLOCK_clk_perh0_root_ {}
  300. #define _SWITCH_CLOCK_clk_perh0_root_SOURCE_clk_osc_sys_ { \
  301. uint32_t _ezchip_macro_read_value_=MA_INW(clk_perh0_root_ctrl_REG_ADDR); \
  302. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  303. _ezchip_macro_read_value_ |= (0x0&0x1)<<24; \
  304. MA_OUTW(clk_perh0_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  305. }
  306. #define _SWITCH_CLOCK_clk_perh0_root_SOURCE_clk_pll0_out_ { \
  307. uint32_t _ezchip_macro_read_value_=MA_INW(clk_perh0_root_ctrl_REG_ADDR); \
  308. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  309. _ezchip_macro_read_value_ |= (0x1&0x1)<<24; \
  310. MA_OUTW(clk_perh0_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  311. }
  312. #define _GET_CLOCK_SOURCE_STATUS_clk_perh0_root_(_ezchip_macro_read_value_) { \
  313. _ezchip_macro_read_value_=MA_INW(clk_perh0_root_ctrl_REG_ADDR) >> 24; \
  314. _ezchip_macro_read_value_ &= 0x1;\
  315. }
  316. #define _ENABLE_CLOCK_clk_perh1_root_ {}
  317. #define _SWITCH_CLOCK_clk_perh1_root_SOURCE_clk_osc_sys_ { \
  318. uint32_t _ezchip_macro_read_value_=MA_INW(clk_perh1_root_ctrl_REG_ADDR); \
  319. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  320. _ezchip_macro_read_value_ |= (0x0&0x1)<<24; \
  321. MA_OUTW(clk_perh1_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  322. }
  323. #define _SWITCH_CLOCK_clk_perh1_root_SOURCE_clk_pll2_out_ { \
  324. uint32_t _ezchip_macro_read_value_=MA_INW(clk_perh1_root_ctrl_REG_ADDR); \
  325. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  326. _ezchip_macro_read_value_ |= (0x1&0x1)<<24; \
  327. MA_OUTW(clk_perh1_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  328. }
  329. #define _GET_CLOCK_SOURCE_STATUS_clk_perh1_root_(_ezchip_macro_read_value_) { \
  330. _ezchip_macro_read_value_=MA_INW(clk_perh1_root_ctrl_REG_ADDR) >> 24; \
  331. _ezchip_macro_read_value_ &= 0x1;\
  332. }
  333. #define _ENABLE_CLOCK_clk_vin_root_ {}
  334. #define _SWITCH_CLOCK_clk_vin_root_SOURCE_clk_osc_sys_ { \
  335. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_root_ctrl_REG_ADDR); \
  336. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  337. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  338. MA_OUTW(clk_vin_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  339. }
  340. #define _SWITCH_CLOCK_clk_vin_root_SOURCE_clk_pll1_out_ { \
  341. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_root_ctrl_REG_ADDR); \
  342. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  343. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  344. MA_OUTW(clk_vin_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  345. }
  346. #define _SWITCH_CLOCK_clk_vin_root_SOURCE_clk_pll2_out_ { \
  347. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_root_ctrl_REG_ADDR); \
  348. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  349. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  350. MA_OUTW(clk_vin_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  351. }
  352. #define _GET_CLOCK_SOURCE_STATUS_clk_vin_root_(_ezchip_macro_read_value_) { \
  353. _ezchip_macro_read_value_=MA_INW(clk_vin_root_ctrl_REG_ADDR) >> 24; \
  354. _ezchip_macro_read_value_ &= 0x3;\
  355. }
  356. #define _ENABLE_CLOCK_clk_vout_root_ {}
  357. #define _SWITCH_CLOCK_clk_vout_root_SOURCE_clk_osc_aud_ { \
  358. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vout_root_ctrl_REG_ADDR); \
  359. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  360. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  361. MA_OUTW(clk_vout_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  362. }
  363. #define _SWITCH_CLOCK_clk_vout_root_SOURCE_clk_pll0_out_ { \
  364. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vout_root_ctrl_REG_ADDR); \
  365. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  366. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  367. MA_OUTW(clk_vout_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  368. }
  369. #define _SWITCH_CLOCK_clk_vout_root_SOURCE_clk_pll2_out_ { \
  370. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vout_root_ctrl_REG_ADDR); \
  371. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  372. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  373. MA_OUTW(clk_vout_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  374. }
  375. #define _GET_CLOCK_SOURCE_STATUS_clk_vout_root_(_ezchip_macro_read_value_) { \
  376. _ezchip_macro_read_value_=MA_INW(clk_vout_root_ctrl_REG_ADDR) >> 24; \
  377. _ezchip_macro_read_value_ &= 0x3;\
  378. }
  379. #define _ENABLE_CLOCK_clk_audio_root_ { \
  380. uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_root_ctrl_REG_ADDR); \
  381. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  382. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  383. MA_OUTW(clk_audio_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  384. }
  385. #define _DISABLE_CLOCK_clk_audio_root_ { \
  386. uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_root_ctrl_REG_ADDR); \
  387. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  388. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  389. MA_OUTW(clk_audio_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  390. }
  391. #define _GET_CLOCK_ENABLE_STATUS_clk_audio_root_(_ezchip_macro_read_value_) { \
  392. _ezchip_macro_read_value_=MA_INW(clk_audio_root_ctrl_REG_ADDR) >> 31; \
  393. _ezchip_macro_read_value_ &= 0x1;\
  394. }
  395. #define _DIVIDE_CLOCK_clk_audio_root_(div) { \
  396. uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_root_ctrl_REG_ADDR); \
  397. _ezchip_macro_read_value_ &= ~(0xF); \
  398. _ezchip_macro_read_value_ |= (div&0xF); \
  399. MA_OUTW(clk_audio_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  400. }
  401. #define _GET_CLOCK_DIVIDE_STATUS_clk_audio_root_(_ezchip_macro_read_value_) { \
  402. _ezchip_macro_read_value_=MA_INW(clk_audio_root_ctrl_REG_ADDR); \
  403. _ezchip_macro_read_value_ &= 0xf;\
  404. }
  405. #define _ENABLE_CLOCK_clk_cdechifi4_root_ {}
  406. #define _SWITCH_CLOCK_clk_cdechifi4_root_SOURCE_clk_osc_sys_ { \
  407. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cdechifi4_root_ctrl_REG_ADDR); \
  408. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  409. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  410. MA_OUTW(clk_cdechifi4_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  411. }
  412. #define _SWITCH_CLOCK_clk_cdechifi4_root_SOURCE_clk_pll1_out_ { \
  413. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cdechifi4_root_ctrl_REG_ADDR); \
  414. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  415. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  416. MA_OUTW(clk_cdechifi4_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  417. }
  418. #define _SWITCH_CLOCK_clk_cdechifi4_root_SOURCE_clk_pll2_out_ { \
  419. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cdechifi4_root_ctrl_REG_ADDR); \
  420. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  421. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  422. MA_OUTW(clk_cdechifi4_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  423. }
  424. #define _GET_CLOCK_SOURCE_STATUS_clk_cdechifi4_root_(_ezchip_macro_read_value_) { \
  425. _ezchip_macro_read_value_=MA_INW(clk_cdechifi4_root_ctrl_REG_ADDR) >> 24; \
  426. _ezchip_macro_read_value_ &= 0x3;\
  427. }
  428. #define _ENABLE_CLOCK_clk_cdec_root_ {}
  429. #define _SWITCH_CLOCK_clk_cdec_root_SOURCE_clk_osc_sys_ { \
  430. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cdec_root_ctrl_REG_ADDR); \
  431. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  432. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  433. MA_OUTW(clk_cdec_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  434. }
  435. #define _SWITCH_CLOCK_clk_cdec_root_SOURCE_clk_pll0_out_ { \
  436. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cdec_root_ctrl_REG_ADDR); \
  437. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  438. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  439. MA_OUTW(clk_cdec_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  440. }
  441. #define _SWITCH_CLOCK_clk_cdec_root_SOURCE_clk_pll1_out_ { \
  442. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cdec_root_ctrl_REG_ADDR); \
  443. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  444. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  445. MA_OUTW(clk_cdec_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  446. }
  447. #define _GET_CLOCK_SOURCE_STATUS_clk_cdec_root_(_ezchip_macro_read_value_) { \
  448. _ezchip_macro_read_value_=MA_INW(clk_cdec_root_ctrl_REG_ADDR) >> 24; \
  449. _ezchip_macro_read_value_ &= 0x3;\
  450. }
  451. #define _ENABLE_CLOCK_clk_voutbus_root_ {}
  452. #define _SWITCH_CLOCK_clk_voutbus_root_SOURCE_clk_osc_aud_ { \
  453. uint32_t _ezchip_macro_read_value_=MA_INW(clk_voutbus_root_ctrl_REG_ADDR); \
  454. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  455. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  456. MA_OUTW(clk_voutbus_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  457. }
  458. #define _SWITCH_CLOCK_clk_voutbus_root_SOURCE_clk_pll0_out_ { \
  459. uint32_t _ezchip_macro_read_value_=MA_INW(clk_voutbus_root_ctrl_REG_ADDR); \
  460. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  461. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  462. MA_OUTW(clk_voutbus_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  463. }
  464. #define _SWITCH_CLOCK_clk_voutbus_root_SOURCE_clk_pll2_out_ { \
  465. uint32_t _ezchip_macro_read_value_=MA_INW(clk_voutbus_root_ctrl_REG_ADDR); \
  466. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  467. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  468. MA_OUTW(clk_voutbus_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  469. }
  470. #define _GET_CLOCK_SOURCE_STATUS_clk_voutbus_root_(_ezchip_macro_read_value_) { \
  471. _ezchip_macro_read_value_=MA_INW(clk_voutbus_root_ctrl_REG_ADDR) >> 24; \
  472. _ezchip_macro_read_value_ &= 0x3;\
  473. }
  474. #define _ENABLE_CLOCK_clk_cpunbus_root_div_ {}
  475. #define _DIVIDE_CLOCK_clk_cpunbus_root_div_(div) { \
  476. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cpunbus_root_div_ctrl_REG_ADDR); \
  477. _ezchip_macro_read_value_ &= ~(0x3); \
  478. _ezchip_macro_read_value_ |= (div&0x3); \
  479. MA_OUTW(clk_cpunbus_root_div_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  480. }
  481. #define _GET_CLOCK_DIVIDE_STATUS_clk_cpunbus_root_div_(_ezchip_macro_read_value_) { \
  482. _ezchip_macro_read_value_=MA_INW(clk_cpunbus_root_div_ctrl_REG_ADDR); \
  483. _ezchip_macro_read_value_ &= 0x3;\
  484. }
  485. #define _ENABLE_CLOCK_clk_dsp_root_div_ {}
  486. #define _DIVIDE_CLOCK_clk_dsp_root_div_(div) { \
  487. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dsp_root_div_ctrl_REG_ADDR); \
  488. _ezchip_macro_read_value_ &= ~(0x7); \
  489. _ezchip_macro_read_value_ |= (div&0x7); \
  490. MA_OUTW(clk_dsp_root_div_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  491. }
  492. #define _GET_CLOCK_DIVIDE_STATUS_clk_dsp_root_div_(_ezchip_macro_read_value_) { \
  493. _ezchip_macro_read_value_=MA_INW(clk_dsp_root_div_ctrl_REG_ADDR); \
  494. _ezchip_macro_read_value_ &= 0x7;\
  495. }
  496. #define _ENABLE_CLOCK_clk_perh0_src_ {}
  497. #define _DIVIDE_CLOCK_clk_perh0_src_(div) { \
  498. uint32_t _ezchip_macro_read_value_=MA_INW(clk_perh0_src_ctrl_REG_ADDR); \
  499. _ezchip_macro_read_value_ &= ~(0x7); \
  500. _ezchip_macro_read_value_ |= (div&0x7); \
  501. MA_OUTW(clk_perh0_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  502. }
  503. #define _GET_CLOCK_DIVIDE_STATUS_clk_perh0_src_(_ezchip_macro_read_value_) { \
  504. _ezchip_macro_read_value_=MA_INW(clk_perh0_src_ctrl_REG_ADDR); \
  505. _ezchip_macro_read_value_ &= 0x7;\
  506. }
  507. #define _ENABLE_CLOCK_clk_perh1_src_ {}
  508. #define _DIVIDE_CLOCK_clk_perh1_src_(div) { \
  509. uint32_t _ezchip_macro_read_value_=MA_INW(clk_perh1_src_ctrl_REG_ADDR); \
  510. _ezchip_macro_read_value_ &= ~(0x7); \
  511. _ezchip_macro_read_value_ |= (div&0x7); \
  512. MA_OUTW(clk_perh1_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  513. }
  514. #define _GET_CLOCK_DIVIDE_STATUS_clk_perh1_src_(_ezchip_macro_read_value_) { \
  515. _ezchip_macro_read_value_=MA_INW(clk_perh1_src_ctrl_REG_ADDR); \
  516. _ezchip_macro_read_value_ &= 0x7;\
  517. }
  518. #define _ENABLE_CLOCK_clk_pll0_testout_ { \
  519. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll0_testout_ctrl_REG_ADDR); \
  520. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  521. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  522. MA_OUTW(clk_pll0_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  523. }
  524. #define _DISABLE_CLOCK_clk_pll0_testout_ { \
  525. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll0_testout_ctrl_REG_ADDR); \
  526. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  527. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  528. MA_OUTW(clk_pll0_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  529. }
  530. #define _GET_CLOCK_ENABLE_STATUS_clk_pll0_testout_(_ezchip_macro_read_value_) { \
  531. _ezchip_macro_read_value_=MA_INW(clk_pll0_testout_ctrl_REG_ADDR) >> 31; \
  532. _ezchip_macro_read_value_ &= 0x1;\
  533. }
  534. #define _DIVIDE_CLOCK_clk_pll0_testout_(div) { \
  535. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll0_testout_ctrl_REG_ADDR); \
  536. _ezchip_macro_read_value_ &= ~(0x1F); \
  537. _ezchip_macro_read_value_ |= (div&0x1F); \
  538. MA_OUTW(clk_pll0_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  539. }
  540. #define _GET_CLOCK_DIVIDE_STATUS_clk_pll0_testout_(_ezchip_macro_read_value_) { \
  541. _ezchip_macro_read_value_=MA_INW(clk_pll0_testout_ctrl_REG_ADDR); \
  542. _ezchip_macro_read_value_ &= 0x1f;\
  543. }
  544. #define _ENABLE_CLOCK_clk_pll1_testout_ { \
  545. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll1_testout_ctrl_REG_ADDR); \
  546. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  547. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  548. MA_OUTW(clk_pll1_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  549. }
  550. #define _DISABLE_CLOCK_clk_pll1_testout_ { \
  551. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll1_testout_ctrl_REG_ADDR); \
  552. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  553. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  554. MA_OUTW(clk_pll1_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  555. }
  556. #define _GET_CLOCK_ENABLE_STATUS_clk_pll1_testout_(_ezchip_macro_read_value_) { \
  557. _ezchip_macro_read_value_=MA_INW(clk_pll1_testout_ctrl_REG_ADDR) >> 31; \
  558. _ezchip_macro_read_value_ &= 0x1;\
  559. }
  560. #define _DIVIDE_CLOCK_clk_pll1_testout_(div) { \
  561. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll1_testout_ctrl_REG_ADDR); \
  562. _ezchip_macro_read_value_ &= ~(0x1F); \
  563. _ezchip_macro_read_value_ |= (div&0x1F); \
  564. MA_OUTW(clk_pll1_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  565. }
  566. #define _GET_CLOCK_DIVIDE_STATUS_clk_pll1_testout_(_ezchip_macro_read_value_) { \
  567. _ezchip_macro_read_value_=MA_INW(clk_pll1_testout_ctrl_REG_ADDR); \
  568. _ezchip_macro_read_value_ &= 0x1f;\
  569. }
  570. #define _ENABLE_CLOCK_clk_pll2_testout_ { \
  571. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll2_testout_ctrl_REG_ADDR); \
  572. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  573. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  574. MA_OUTW(clk_pll2_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  575. }
  576. #define _DISABLE_CLOCK_clk_pll2_testout_ { \
  577. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll2_testout_ctrl_REG_ADDR); \
  578. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  579. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  580. MA_OUTW(clk_pll2_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  581. }
  582. #define _GET_CLOCK_ENABLE_STATUS_clk_pll2_testout_(_ezchip_macro_read_value_) { \
  583. _ezchip_macro_read_value_=MA_INW(clk_pll2_testout_ctrl_REG_ADDR) >> 31; \
  584. _ezchip_macro_read_value_ &= 0x1;\
  585. }
  586. #define _DIVIDE_CLOCK_clk_pll2_testout_(div) { \
  587. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll2_testout_ctrl_REG_ADDR); \
  588. _ezchip_macro_read_value_ &= ~(0x1F); \
  589. _ezchip_macro_read_value_ |= (div&0x1F); \
  590. MA_OUTW(clk_pll2_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  591. }
  592. #define _GET_CLOCK_DIVIDE_STATUS_clk_pll2_testout_(_ezchip_macro_read_value_) { \
  593. _ezchip_macro_read_value_=MA_INW(clk_pll2_testout_ctrl_REG_ADDR); \
  594. _ezchip_macro_read_value_ &= 0x1f;\
  595. }
  596. #define _ENABLE_CLOCK_clk_pll2_refclk_ {}
  597. #define _SWITCH_CLOCK_clk_pll2_refclk_SOURCE_clk_osc_sys_ { \
  598. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll2_refclk_ctrl_REG_ADDR); \
  599. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  600. _ezchip_macro_read_value_ |= (0x0&0x1)<<24; \
  601. MA_OUTW(clk_pll2_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  602. }
  603. #define _SWITCH_CLOCK_clk_pll2_refclk_SOURCE_clk_osc_aud_ { \
  604. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll2_refclk_ctrl_REG_ADDR); \
  605. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  606. _ezchip_macro_read_value_ |= (0x1&0x1)<<24; \
  607. MA_OUTW(clk_pll2_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  608. }
  609. #define _GET_CLOCK_SOURCE_STATUS_clk_pll2_refclk_(_ezchip_macro_read_value_) { \
  610. _ezchip_macro_read_value_=MA_INW(clk_pll2_refclk_ctrl_REG_ADDR) >> 24; \
  611. _ezchip_macro_read_value_ &= 0x1;\
  612. }
  613. #define _ENABLE_CLOCK_clk_cpu_core_ {}
  614. #define _DIVIDE_CLOCK_clk_cpu_core_(div) { \
  615. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cpu_core_ctrl_REG_ADDR); \
  616. _ezchip_macro_read_value_ &= ~(0xF); \
  617. _ezchip_macro_read_value_ |= (div&0xF); \
  618. MA_OUTW(clk_cpu_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  619. }
  620. #define _GET_CLOCK_DIVIDE_STATUS_clk_cpu_core_(_ezchip_macro_read_value_) { \
  621. _ezchip_macro_read_value_=MA_INW(clk_cpu_core_ctrl_REG_ADDR); \
  622. _ezchip_macro_read_value_ &= 0xf;\
  623. }
  624. #define _ENABLE_CLOCK_clk_cpu_axi_ {}
  625. #define _DIVIDE_CLOCK_clk_cpu_axi_(div) { \
  626. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cpu_axi_ctrl_REG_ADDR); \
  627. _ezchip_macro_read_value_ &= ~(0xF); \
  628. _ezchip_macro_read_value_ |= (div&0xF); \
  629. MA_OUTW(clk_cpu_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  630. }
  631. #define _GET_CLOCK_DIVIDE_STATUS_clk_cpu_axi_(_ezchip_macro_read_value_) { \
  632. _ezchip_macro_read_value_=MA_INW(clk_cpu_axi_ctrl_REG_ADDR); \
  633. _ezchip_macro_read_value_ &= 0xf;\
  634. }
  635. #define _ENABLE_CLOCK_clk_ahb_bus_ {}
  636. #define _DIVIDE_CLOCK_clk_ahb_bus_(div) { \
  637. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ahb_bus_ctrl_REG_ADDR); \
  638. _ezchip_macro_read_value_ &= ~(0xF); \
  639. _ezchip_macro_read_value_ |= (div&0xF); \
  640. MA_OUTW(clk_ahb_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  641. }
  642. #define _GET_CLOCK_DIVIDE_STATUS_clk_ahb_bus_(_ezchip_macro_read_value_) { \
  643. _ezchip_macro_read_value_=MA_INW(clk_ahb_bus_ctrl_REG_ADDR); \
  644. _ezchip_macro_read_value_ &= 0xf;\
  645. }
  646. #define _ENABLE_CLOCK_clk_apb1_bus_ {}
  647. #define _DIVIDE_CLOCK_clk_apb1_bus_(div) { \
  648. uint32_t _ezchip_macro_read_value_=MA_INW(clk_apb1_bus_ctrl_REG_ADDR); \
  649. _ezchip_macro_read_value_ &= ~(0xF); \
  650. _ezchip_macro_read_value_ |= (div&0xF); \
  651. MA_OUTW(clk_apb1_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  652. }
  653. #define _GET_CLOCK_DIVIDE_STATUS_clk_apb1_bus_(_ezchip_macro_read_value_) { \
  654. _ezchip_macro_read_value_=MA_INW(clk_apb1_bus_ctrl_REG_ADDR); \
  655. _ezchip_macro_read_value_ &= 0xf;\
  656. }
  657. #define _ENABLE_CLOCK_clk_apb2_bus_ {}
  658. #define _DIVIDE_CLOCK_clk_apb2_bus_(div) { \
  659. uint32_t _ezchip_macro_read_value_=MA_INW(clk_apb2_bus_ctrl_REG_ADDR); \
  660. _ezchip_macro_read_value_ &= ~(0xF); \
  661. _ezchip_macro_read_value_ |= (div&0xF); \
  662. MA_OUTW(clk_apb2_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  663. }
  664. #define _GET_CLOCK_DIVIDE_STATUS_clk_apb2_bus_(_ezchip_macro_read_value_) { \
  665. _ezchip_macro_read_value_=MA_INW(clk_apb2_bus_ctrl_REG_ADDR); \
  666. _ezchip_macro_read_value_ &= 0xf;\
  667. }
  668. #define _ENABLE_CLOCK_clk_dom3ahb_bus_ { \
  669. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dom3ahb_bus_ctrl_REG_ADDR); \
  670. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  671. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  672. MA_OUTW(clk_dom3ahb_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  673. }
  674. #define _DISABLE_CLOCK_clk_dom3ahb_bus_ { \
  675. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dom3ahb_bus_ctrl_REG_ADDR); \
  676. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  677. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  678. MA_OUTW(clk_dom3ahb_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  679. }
  680. #define _GET_CLOCK_ENABLE_STATUS_clk_dom3ahb_bus_(_ezchip_macro_read_value_) { \
  681. _ezchip_macro_read_value_=MA_INW(clk_dom3ahb_bus_ctrl_REG_ADDR) >> 31; \
  682. _ezchip_macro_read_value_ &= 0x1;\
  683. }
  684. #define _ENABLE_CLOCK_clk_dom7ahb_bus_ { \
  685. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dom7ahb_bus_ctrl_REG_ADDR); \
  686. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  687. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  688. MA_OUTW(clk_dom7ahb_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  689. }
  690. #define _DISABLE_CLOCK_clk_dom7ahb_bus_ { \
  691. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dom7ahb_bus_ctrl_REG_ADDR); \
  692. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  693. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  694. MA_OUTW(clk_dom7ahb_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  695. }
  696. #define _GET_CLOCK_ENABLE_STATUS_clk_dom7ahb_bus_(_ezchip_macro_read_value_) { \
  697. _ezchip_macro_read_value_=MA_INW(clk_dom7ahb_bus_ctrl_REG_ADDR) >> 31; \
  698. _ezchip_macro_read_value_ &= 0x1;\
  699. }
  700. #define _ENABLE_CLOCK_clk_u74_core0_ { \
  701. uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74_core0_ctrl_REG_ADDR); \
  702. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  703. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  704. MA_OUTW(clk_u74_core0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  705. }
  706. #define _DISABLE_CLOCK_clk_u74_core0_ { \
  707. uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74_core0_ctrl_REG_ADDR); \
  708. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  709. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  710. MA_OUTW(clk_u74_core0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  711. }
  712. #define _GET_CLOCK_ENABLE_STATUS_clk_u74_core0_(_ezchip_macro_read_value_) { \
  713. _ezchip_macro_read_value_=MA_INW(clk_u74_core0_ctrl_REG_ADDR) >> 31; \
  714. _ezchip_macro_read_value_ &= 0x1;\
  715. }
  716. #define _ENABLE_CLOCK_clk_u74_core1_ { \
  717. uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74_core1_ctrl_REG_ADDR); \
  718. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  719. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  720. MA_OUTW(clk_u74_core1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  721. }
  722. #define _DISABLE_CLOCK_clk_u74_core1_ { \
  723. uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74_core1_ctrl_REG_ADDR); \
  724. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  725. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  726. MA_OUTW(clk_u74_core1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  727. }
  728. #define _GET_CLOCK_ENABLE_STATUS_clk_u74_core1_(_ezchip_macro_read_value_) { \
  729. _ezchip_macro_read_value_=MA_INW(clk_u74_core1_ctrl_REG_ADDR) >> 31; \
  730. _ezchip_macro_read_value_ &= 0x1;\
  731. }
  732. #define _DIVIDE_CLOCK_clk_u74_core1_(div) { \
  733. uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74_core1_ctrl_REG_ADDR); \
  734. _ezchip_macro_read_value_ &= ~(0xF); \
  735. _ezchip_macro_read_value_ |= (div&0xF); \
  736. MA_OUTW(clk_u74_core1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  737. }
  738. #define _GET_CLOCK_DIVIDE_STATUS_clk_u74_core1_(_ezchip_macro_read_value_) { \
  739. _ezchip_macro_read_value_=MA_INW(clk_u74_core1_ctrl_REG_ADDR); \
  740. _ezchip_macro_read_value_ &= 0xf;\
  741. }
  742. #define _ENABLE_CLOCK_clk_u74_axi_ { \
  743. uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74_axi_ctrl_REG_ADDR); \
  744. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  745. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  746. MA_OUTW(clk_u74_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  747. }
  748. #define _DISABLE_CLOCK_clk_u74_axi_ { \
  749. uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74_axi_ctrl_REG_ADDR); \
  750. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  751. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  752. MA_OUTW(clk_u74_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  753. }
  754. #define _GET_CLOCK_ENABLE_STATUS_clk_u74_axi_(_ezchip_macro_read_value_) { \
  755. _ezchip_macro_read_value_=MA_INW(clk_u74_axi_ctrl_REG_ADDR) >> 31; \
  756. _ezchip_macro_read_value_ &= 0x1;\
  757. }
  758. #define _ENABLE_CLOCK_clk_u74rtc_toggle_ { \
  759. uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74rtc_toggle_ctrl_REG_ADDR); \
  760. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  761. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  762. MA_OUTW(clk_u74rtc_toggle_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  763. }
  764. #define _DISABLE_CLOCK_clk_u74rtc_toggle_ { \
  765. uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74rtc_toggle_ctrl_REG_ADDR); \
  766. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  767. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  768. MA_OUTW(clk_u74rtc_toggle_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  769. }
  770. #define _GET_CLOCK_ENABLE_STATUS_clk_u74rtc_toggle_(_ezchip_macro_read_value_) { \
  771. _ezchip_macro_read_value_=MA_INW(clk_u74rtc_toggle_ctrl_REG_ADDR) >> 31; \
  772. _ezchip_macro_read_value_ &= 0x1;\
  773. }
  774. #define _ENABLE_CLOCK_clk_sgdma2p_axi_ { \
  775. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sgdma2p_axi_ctrl_REG_ADDR); \
  776. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  777. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  778. MA_OUTW(clk_sgdma2p_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  779. }
  780. #define _DISABLE_CLOCK_clk_sgdma2p_axi_ { \
  781. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sgdma2p_axi_ctrl_REG_ADDR); \
  782. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  783. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  784. MA_OUTW(clk_sgdma2p_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  785. }
  786. #define _GET_CLOCK_ENABLE_STATUS_clk_sgdma2p_axi_(_ezchip_macro_read_value_) { \
  787. _ezchip_macro_read_value_=MA_INW(clk_sgdma2p_axi_ctrl_REG_ADDR) >> 31; \
  788. _ezchip_macro_read_value_ &= 0x1;\
  789. }
  790. #define _ENABLE_CLOCK_clk_dma2pnoc_axi_ { \
  791. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dma2pnoc_axi_ctrl_REG_ADDR); \
  792. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  793. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  794. MA_OUTW(clk_dma2pnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  795. }
  796. #define _DISABLE_CLOCK_clk_dma2pnoc_axi_ { \
  797. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dma2pnoc_axi_ctrl_REG_ADDR); \
  798. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  799. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  800. MA_OUTW(clk_dma2pnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  801. }
  802. #define _GET_CLOCK_ENABLE_STATUS_clk_dma2pnoc_axi_(_ezchip_macro_read_value_) { \
  803. _ezchip_macro_read_value_=MA_INW(clk_dma2pnoc_axi_ctrl_REG_ADDR) >> 31; \
  804. _ezchip_macro_read_value_ &= 0x1;\
  805. }
  806. #define _ENABLE_CLOCK_clk_sgdma2p_ahb_ { \
  807. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sgdma2p_ahb_ctrl_REG_ADDR); \
  808. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  809. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  810. MA_OUTW(clk_sgdma2p_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  811. }
  812. #define _DISABLE_CLOCK_clk_sgdma2p_ahb_ { \
  813. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sgdma2p_ahb_ctrl_REG_ADDR); \
  814. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  815. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  816. MA_OUTW(clk_sgdma2p_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  817. }
  818. #define _GET_CLOCK_ENABLE_STATUS_clk_sgdma2p_ahb_(_ezchip_macro_read_value_) { \
  819. _ezchip_macro_read_value_=MA_INW(clk_sgdma2p_ahb_ctrl_REG_ADDR) >> 31; \
  820. _ezchip_macro_read_value_ &= 0x1;\
  821. }
  822. #define _ENABLE_CLOCK_clk_dla_bus_ {}
  823. #define _DIVIDE_CLOCK_clk_dla_bus_(div) { \
  824. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_bus_ctrl_REG_ADDR); \
  825. _ezchip_macro_read_value_ &= ~(0x7); \
  826. _ezchip_macro_read_value_ |= (div&0x7); \
  827. MA_OUTW(clk_dla_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  828. }
  829. #define _GET_CLOCK_DIVIDE_STATUS_clk_dla_bus_(_ezchip_macro_read_value_) { \
  830. _ezchip_macro_read_value_=MA_INW(clk_dla_bus_ctrl_REG_ADDR); \
  831. _ezchip_macro_read_value_ &= 0x7;\
  832. }
  833. #define _ENABLE_CLOCK_clk_dla_axi_ { \
  834. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_axi_ctrl_REG_ADDR); \
  835. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  836. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  837. MA_OUTW(clk_dla_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  838. }
  839. #define _DISABLE_CLOCK_clk_dla_axi_ { \
  840. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_axi_ctrl_REG_ADDR); \
  841. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  842. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  843. MA_OUTW(clk_dla_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  844. }
  845. #define _GET_CLOCK_ENABLE_STATUS_clk_dla_axi_(_ezchip_macro_read_value_) { \
  846. _ezchip_macro_read_value_=MA_INW(clk_dla_axi_ctrl_REG_ADDR) >> 31; \
  847. _ezchip_macro_read_value_ &= 0x1;\
  848. }
  849. #define _ENABLE_CLOCK_clk_dlanoc_axi_ { \
  850. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dlanoc_axi_ctrl_REG_ADDR); \
  851. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  852. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  853. MA_OUTW(clk_dlanoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  854. }
  855. #define _DISABLE_CLOCK_clk_dlanoc_axi_ { \
  856. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dlanoc_axi_ctrl_REG_ADDR); \
  857. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  858. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  859. MA_OUTW(clk_dlanoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  860. }
  861. #define _GET_CLOCK_ENABLE_STATUS_clk_dlanoc_axi_(_ezchip_macro_read_value_) { \
  862. _ezchip_macro_read_value_=MA_INW(clk_dlanoc_axi_ctrl_REG_ADDR) >> 31; \
  863. _ezchip_macro_read_value_ &= 0x1;\
  864. }
  865. #define _ENABLE_CLOCK_clk_dla_apb_ { \
  866. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_apb_ctrl_REG_ADDR); \
  867. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  868. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  869. MA_OUTW(clk_dla_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  870. }
  871. #define _DISABLE_CLOCK_clk_dla_apb_ { \
  872. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_apb_ctrl_REG_ADDR); \
  873. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  874. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  875. MA_OUTW(clk_dla_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  876. }
  877. #define _GET_CLOCK_ENABLE_STATUS_clk_dla_apb_(_ezchip_macro_read_value_) { \
  878. _ezchip_macro_read_value_=MA_INW(clk_dla_apb_ctrl_REG_ADDR) >> 31; \
  879. _ezchip_macro_read_value_ &= 0x1;\
  880. }
  881. #define _ENABLE_CLOCK_clk_vp6_core_ { \
  882. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6_core_ctrl_REG_ADDR); \
  883. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  884. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  885. MA_OUTW(clk_vp6_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  886. }
  887. #define _DISABLE_CLOCK_clk_vp6_core_ { \
  888. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6_core_ctrl_REG_ADDR); \
  889. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  890. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  891. MA_OUTW(clk_vp6_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  892. }
  893. #define _GET_CLOCK_ENABLE_STATUS_clk_vp6_core_(_ezchip_macro_read_value_) { \
  894. _ezchip_macro_read_value_=MA_INW(clk_vp6_core_ctrl_REG_ADDR) >> 31; \
  895. _ezchip_macro_read_value_ &= 0x1;\
  896. }
  897. #define _DIVIDE_CLOCK_clk_vp6_core_(div) { \
  898. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6_core_ctrl_REG_ADDR); \
  899. _ezchip_macro_read_value_ &= ~(0x7); \
  900. _ezchip_macro_read_value_ |= (div&0x7); \
  901. MA_OUTW(clk_vp6_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  902. }
  903. #define _GET_CLOCK_DIVIDE_STATUS_clk_vp6_core_(_ezchip_macro_read_value_) { \
  904. _ezchip_macro_read_value_=MA_INW(clk_vp6_core_ctrl_REG_ADDR); \
  905. _ezchip_macro_read_value_ &= 0x7;\
  906. }
  907. #define _ENABLE_CLOCK_clk_vp6bus_src_ {}
  908. #define _DIVIDE_CLOCK_clk_vp6bus_src_(div) { \
  909. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6bus_src_ctrl_REG_ADDR); \
  910. _ezchip_macro_read_value_ &= ~(0x7); \
  911. _ezchip_macro_read_value_ |= (div&0x7); \
  912. MA_OUTW(clk_vp6bus_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  913. }
  914. #define _GET_CLOCK_DIVIDE_STATUS_clk_vp6bus_src_(_ezchip_macro_read_value_) { \
  915. _ezchip_macro_read_value_=MA_INW(clk_vp6bus_src_ctrl_REG_ADDR); \
  916. _ezchip_macro_read_value_ &= 0x7;\
  917. }
  918. #define _ENABLE_CLOCK_clk_vp6_axi_ { \
  919. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6_axi_ctrl_REG_ADDR); \
  920. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  921. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  922. MA_OUTW(clk_vp6_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  923. }
  924. #define _DISABLE_CLOCK_clk_vp6_axi_ { \
  925. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6_axi_ctrl_REG_ADDR); \
  926. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  927. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  928. MA_OUTW(clk_vp6_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  929. }
  930. #define _GET_CLOCK_ENABLE_STATUS_clk_vp6_axi_(_ezchip_macro_read_value_) { \
  931. _ezchip_macro_read_value_=MA_INW(clk_vp6_axi_ctrl_REG_ADDR) >> 31; \
  932. _ezchip_macro_read_value_ &= 0x1;\
  933. }
  934. #define _DIVIDE_CLOCK_clk_vp6_axi_(div) { \
  935. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6_axi_ctrl_REG_ADDR); \
  936. _ezchip_macro_read_value_ &= ~(0x7); \
  937. _ezchip_macro_read_value_ |= (div&0x7); \
  938. MA_OUTW(clk_vp6_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  939. }
  940. #define _GET_CLOCK_DIVIDE_STATUS_clk_vp6_axi_(_ezchip_macro_read_value_) { \
  941. _ezchip_macro_read_value_=MA_INW(clk_vp6_axi_ctrl_REG_ADDR); \
  942. _ezchip_macro_read_value_ &= 0x7;\
  943. }
  944. #define _ENABLE_CLOCK_clk_vcdecbus_src_ {}
  945. #define _DIVIDE_CLOCK_clk_vcdecbus_src_(div) { \
  946. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vcdecbus_src_ctrl_REG_ADDR); \
  947. _ezchip_macro_read_value_ &= ~(0x7); \
  948. _ezchip_macro_read_value_ |= (div&0x7); \
  949. MA_OUTW(clk_vcdecbus_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  950. }
  951. #define _GET_CLOCK_DIVIDE_STATUS_clk_vcdecbus_src_(_ezchip_macro_read_value_) { \
  952. _ezchip_macro_read_value_=MA_INW(clk_vcdecbus_src_ctrl_REG_ADDR); \
  953. _ezchip_macro_read_value_ &= 0x7;\
  954. }
  955. #define _ENABLE_CLOCK_clk_vdec_bus_ {}
  956. #define _DIVIDE_CLOCK_clk_vdec_bus_(div) { \
  957. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_bus_ctrl_REG_ADDR); \
  958. _ezchip_macro_read_value_ &= ~(0xF); \
  959. _ezchip_macro_read_value_ |= (div&0xF); \
  960. MA_OUTW(clk_vdec_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  961. }
  962. #define _GET_CLOCK_DIVIDE_STATUS_clk_vdec_bus_(_ezchip_macro_read_value_) { \
  963. _ezchip_macro_read_value_=MA_INW(clk_vdec_bus_ctrl_REG_ADDR); \
  964. _ezchip_macro_read_value_ &= 0xf;\
  965. }
  966. #define _ENABLE_CLOCK_clk_vdec_axi_ { \
  967. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_axi_ctrl_REG_ADDR); \
  968. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  969. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  970. MA_OUTW(clk_vdec_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  971. }
  972. #define _DISABLE_CLOCK_clk_vdec_axi_ { \
  973. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_axi_ctrl_REG_ADDR); \
  974. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  975. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  976. MA_OUTW(clk_vdec_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  977. }
  978. #define _GET_CLOCK_ENABLE_STATUS_clk_vdec_axi_(_ezchip_macro_read_value_) { \
  979. _ezchip_macro_read_value_=MA_INW(clk_vdec_axi_ctrl_REG_ADDR) >> 31; \
  980. _ezchip_macro_read_value_ &= 0x1;\
  981. }
  982. #define _ENABLE_CLOCK_clk_vdecbrg_mainclk_ { \
  983. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdecbrg_mainclk_ctrl_REG_ADDR); \
  984. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  985. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  986. MA_OUTW(clk_vdecbrg_mainclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  987. }
  988. #define _DISABLE_CLOCK_clk_vdecbrg_mainclk_ { \
  989. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdecbrg_mainclk_ctrl_REG_ADDR); \
  990. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  991. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  992. MA_OUTW(clk_vdecbrg_mainclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  993. }
  994. #define _GET_CLOCK_ENABLE_STATUS_clk_vdecbrg_mainclk_(_ezchip_macro_read_value_) { \
  995. _ezchip_macro_read_value_=MA_INW(clk_vdecbrg_mainclk_ctrl_REG_ADDR) >> 31; \
  996. _ezchip_macro_read_value_ &= 0x1;\
  997. }
  998. #define _ENABLE_CLOCK_clk_vdec_bclk_ { \
  999. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_bclk_ctrl_REG_ADDR); \
  1000. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1001. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1002. MA_OUTW(clk_vdec_bclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1003. }
  1004. #define _DISABLE_CLOCK_clk_vdec_bclk_ { \
  1005. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_bclk_ctrl_REG_ADDR); \
  1006. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1007. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1008. MA_OUTW(clk_vdec_bclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1009. }
  1010. #define _GET_CLOCK_ENABLE_STATUS_clk_vdec_bclk_(_ezchip_macro_read_value_) { \
  1011. _ezchip_macro_read_value_=MA_INW(clk_vdec_bclk_ctrl_REG_ADDR) >> 31; \
  1012. _ezchip_macro_read_value_ &= 0x1;\
  1013. }
  1014. #define _DIVIDE_CLOCK_clk_vdec_bclk_(div) { \
  1015. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_bclk_ctrl_REG_ADDR); \
  1016. _ezchip_macro_read_value_ &= ~(0xF); \
  1017. _ezchip_macro_read_value_ |= (div&0xF); \
  1018. MA_OUTW(clk_vdec_bclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1019. }
  1020. #define _GET_CLOCK_DIVIDE_STATUS_clk_vdec_bclk_(_ezchip_macro_read_value_) { \
  1021. _ezchip_macro_read_value_=MA_INW(clk_vdec_bclk_ctrl_REG_ADDR); \
  1022. _ezchip_macro_read_value_ &= 0xf;\
  1023. }
  1024. #define _ENABLE_CLOCK_clk_vdec_cclk_ { \
  1025. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_cclk_ctrl_REG_ADDR); \
  1026. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1027. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1028. MA_OUTW(clk_vdec_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1029. }
  1030. #define _DISABLE_CLOCK_clk_vdec_cclk_ { \
  1031. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_cclk_ctrl_REG_ADDR); \
  1032. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1033. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1034. MA_OUTW(clk_vdec_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1035. }
  1036. #define _GET_CLOCK_ENABLE_STATUS_clk_vdec_cclk_(_ezchip_macro_read_value_) { \
  1037. _ezchip_macro_read_value_=MA_INW(clk_vdec_cclk_ctrl_REG_ADDR) >> 31; \
  1038. _ezchip_macro_read_value_ &= 0x1;\
  1039. }
  1040. #define _DIVIDE_CLOCK_clk_vdec_cclk_(div) { \
  1041. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_cclk_ctrl_REG_ADDR); \
  1042. _ezchip_macro_read_value_ &= ~(0xF); \
  1043. _ezchip_macro_read_value_ |= (div&0xF); \
  1044. MA_OUTW(clk_vdec_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1045. }
  1046. #define _GET_CLOCK_DIVIDE_STATUS_clk_vdec_cclk_(_ezchip_macro_read_value_) { \
  1047. _ezchip_macro_read_value_=MA_INW(clk_vdec_cclk_ctrl_REG_ADDR); \
  1048. _ezchip_macro_read_value_ &= 0xf;\
  1049. }
  1050. #define _ENABLE_CLOCK_clk_vdec_apb_ { \
  1051. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_apb_ctrl_REG_ADDR); \
  1052. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1053. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1054. MA_OUTW(clk_vdec_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1055. }
  1056. #define _DISABLE_CLOCK_clk_vdec_apb_ { \
  1057. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_apb_ctrl_REG_ADDR); \
  1058. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1059. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1060. MA_OUTW(clk_vdec_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1061. }
  1062. #define _GET_CLOCK_ENABLE_STATUS_clk_vdec_apb_(_ezchip_macro_read_value_) { \
  1063. _ezchip_macro_read_value_=MA_INW(clk_vdec_apb_ctrl_REG_ADDR) >> 31; \
  1064. _ezchip_macro_read_value_ &= 0x1;\
  1065. }
  1066. #define _ENABLE_CLOCK_clk_jpeg_axi_ { \
  1067. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_axi_ctrl_REG_ADDR); \
  1068. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1069. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1070. MA_OUTW(clk_jpeg_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1071. }
  1072. #define _DISABLE_CLOCK_clk_jpeg_axi_ { \
  1073. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_axi_ctrl_REG_ADDR); \
  1074. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1075. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1076. MA_OUTW(clk_jpeg_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1077. }
  1078. #define _GET_CLOCK_ENABLE_STATUS_clk_jpeg_axi_(_ezchip_macro_read_value_) { \
  1079. _ezchip_macro_read_value_=MA_INW(clk_jpeg_axi_ctrl_REG_ADDR) >> 31; \
  1080. _ezchip_macro_read_value_ &= 0x1;\
  1081. }
  1082. #define _DIVIDE_CLOCK_clk_jpeg_axi_(div) { \
  1083. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_axi_ctrl_REG_ADDR); \
  1084. _ezchip_macro_read_value_ &= ~(0xF); \
  1085. _ezchip_macro_read_value_ |= (div&0xF); \
  1086. MA_OUTW(clk_jpeg_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1087. }
  1088. #define _GET_CLOCK_DIVIDE_STATUS_clk_jpeg_axi_(_ezchip_macro_read_value_) { \
  1089. _ezchip_macro_read_value_=MA_INW(clk_jpeg_axi_ctrl_REG_ADDR); \
  1090. _ezchip_macro_read_value_ &= 0xf;\
  1091. }
  1092. #define _ENABLE_CLOCK_clk_jpeg_cclk_ { \
  1093. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_cclk_ctrl_REG_ADDR); \
  1094. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1095. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1096. MA_OUTW(clk_jpeg_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1097. }
  1098. #define _DISABLE_CLOCK_clk_jpeg_cclk_ { \
  1099. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_cclk_ctrl_REG_ADDR); \
  1100. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1101. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1102. MA_OUTW(clk_jpeg_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1103. }
  1104. #define _GET_CLOCK_ENABLE_STATUS_clk_jpeg_cclk_(_ezchip_macro_read_value_) { \
  1105. _ezchip_macro_read_value_=MA_INW(clk_jpeg_cclk_ctrl_REG_ADDR) >> 31; \
  1106. _ezchip_macro_read_value_ &= 0x1;\
  1107. }
  1108. #define _DIVIDE_CLOCK_clk_jpeg_cclk_(div) { \
  1109. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_cclk_ctrl_REG_ADDR); \
  1110. _ezchip_macro_read_value_ &= ~(0xF); \
  1111. _ezchip_macro_read_value_ |= (div&0xF); \
  1112. MA_OUTW(clk_jpeg_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1113. }
  1114. #define _GET_CLOCK_DIVIDE_STATUS_clk_jpeg_cclk_(_ezchip_macro_read_value_) { \
  1115. _ezchip_macro_read_value_=MA_INW(clk_jpeg_cclk_ctrl_REG_ADDR); \
  1116. _ezchip_macro_read_value_ &= 0xf;\
  1117. }
  1118. #define _ENABLE_CLOCK_clk_jpeg_apb_ { \
  1119. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_apb_ctrl_REG_ADDR); \
  1120. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1121. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1122. MA_OUTW(clk_jpeg_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1123. }
  1124. #define _DISABLE_CLOCK_clk_jpeg_apb_ { \
  1125. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_apb_ctrl_REG_ADDR); \
  1126. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1127. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1128. MA_OUTW(clk_jpeg_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1129. }
  1130. #define _GET_CLOCK_ENABLE_STATUS_clk_jpeg_apb_(_ezchip_macro_read_value_) { \
  1131. _ezchip_macro_read_value_=MA_INW(clk_jpeg_apb_ctrl_REG_ADDR) >> 31; \
  1132. _ezchip_macro_read_value_ &= 0x1;\
  1133. }
  1134. #define _ENABLE_CLOCK_clk_gc300_2x_ { \
  1135. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gc300_2x_ctrl_REG_ADDR); \
  1136. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1137. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1138. MA_OUTW(clk_gc300_2x_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1139. }
  1140. #define _DISABLE_CLOCK_clk_gc300_2x_ { \
  1141. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gc300_2x_ctrl_REG_ADDR); \
  1142. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1143. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1144. MA_OUTW(clk_gc300_2x_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1145. }
  1146. #define _GET_CLOCK_ENABLE_STATUS_clk_gc300_2x_(_ezchip_macro_read_value_) { \
  1147. _ezchip_macro_read_value_=MA_INW(clk_gc300_2x_ctrl_REG_ADDR) >> 31; \
  1148. _ezchip_macro_read_value_ &= 0x1;\
  1149. }
  1150. #define _DIVIDE_CLOCK_clk_gc300_2x_(div) { \
  1151. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gc300_2x_ctrl_REG_ADDR); \
  1152. _ezchip_macro_read_value_ &= ~(0xF); \
  1153. _ezchip_macro_read_value_ |= (div&0xF); \
  1154. MA_OUTW(clk_gc300_2x_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1155. }
  1156. #define _GET_CLOCK_DIVIDE_STATUS_clk_gc300_2x_(_ezchip_macro_read_value_) { \
  1157. _ezchip_macro_read_value_=MA_INW(clk_gc300_2x_ctrl_REG_ADDR); \
  1158. _ezchip_macro_read_value_ &= 0xf;\
  1159. }
  1160. #define _ENABLE_CLOCK_clk_gc300_ahb_ { \
  1161. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gc300_ahb_ctrl_REG_ADDR); \
  1162. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1163. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1164. MA_OUTW(clk_gc300_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1165. }
  1166. #define _DISABLE_CLOCK_clk_gc300_ahb_ { \
  1167. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gc300_ahb_ctrl_REG_ADDR); \
  1168. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1169. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1170. MA_OUTW(clk_gc300_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1171. }
  1172. #define _GET_CLOCK_ENABLE_STATUS_clk_gc300_ahb_(_ezchip_macro_read_value_) { \
  1173. _ezchip_macro_read_value_=MA_INW(clk_gc300_ahb_ctrl_REG_ADDR) >> 31; \
  1174. _ezchip_macro_read_value_ &= 0x1;\
  1175. }
  1176. #define _ENABLE_CLOCK_clk_jpcgc300_axibus_ {}
  1177. #define _DIVIDE_CLOCK_clk_jpcgc300_axibus_(div) { \
  1178. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpcgc300_axibus_ctrl_REG_ADDR); \
  1179. _ezchip_macro_read_value_ &= ~(0xF); \
  1180. _ezchip_macro_read_value_ |= (div&0xF); \
  1181. MA_OUTW(clk_jpcgc300_axibus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1182. }
  1183. #define _GET_CLOCK_DIVIDE_STATUS_clk_jpcgc300_axibus_(_ezchip_macro_read_value_) { \
  1184. _ezchip_macro_read_value_=MA_INW(clk_jpcgc300_axibus_ctrl_REG_ADDR); \
  1185. _ezchip_macro_read_value_ &= 0xf;\
  1186. }
  1187. #define _ENABLE_CLOCK_clk_gc300_axi_ { \
  1188. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gc300_axi_ctrl_REG_ADDR); \
  1189. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1190. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1191. MA_OUTW(clk_gc300_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1192. }
  1193. #define _DISABLE_CLOCK_clk_gc300_axi_ { \
  1194. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gc300_axi_ctrl_REG_ADDR); \
  1195. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1196. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1197. MA_OUTW(clk_gc300_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1198. }
  1199. #define _GET_CLOCK_ENABLE_STATUS_clk_gc300_axi_(_ezchip_macro_read_value_) { \
  1200. _ezchip_macro_read_value_=MA_INW(clk_gc300_axi_ctrl_REG_ADDR) >> 31; \
  1201. _ezchip_macro_read_value_ &= 0x1;\
  1202. }
  1203. #define _ENABLE_CLOCK_clk_jpcgc300_mainclk_ { \
  1204. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpcgc300_mainclk_ctrl_REG_ADDR); \
  1205. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1206. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1207. MA_OUTW(clk_jpcgc300_mainclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1208. }
  1209. #define _DISABLE_CLOCK_clk_jpcgc300_mainclk_ { \
  1210. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpcgc300_mainclk_ctrl_REG_ADDR); \
  1211. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1212. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1213. MA_OUTW(clk_jpcgc300_mainclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1214. }
  1215. #define _GET_CLOCK_ENABLE_STATUS_clk_jpcgc300_mainclk_(_ezchip_macro_read_value_) { \
  1216. _ezchip_macro_read_value_=MA_INW(clk_jpcgc300_mainclk_ctrl_REG_ADDR) >> 31; \
  1217. _ezchip_macro_read_value_ &= 0x1;\
  1218. }
  1219. #define _ENABLE_CLOCK_clk_venc_bus_ {}
  1220. #define _DIVIDE_CLOCK_clk_venc_bus_(div) { \
  1221. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_bus_ctrl_REG_ADDR); \
  1222. _ezchip_macro_read_value_ &= ~(0xF); \
  1223. _ezchip_macro_read_value_ |= (div&0xF); \
  1224. MA_OUTW(clk_venc_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1225. }
  1226. #define _GET_CLOCK_DIVIDE_STATUS_clk_venc_bus_(_ezchip_macro_read_value_) { \
  1227. _ezchip_macro_read_value_=MA_INW(clk_venc_bus_ctrl_REG_ADDR); \
  1228. _ezchip_macro_read_value_ &= 0xf;\
  1229. }
  1230. #define _ENABLE_CLOCK_clk_venc_axi_ { \
  1231. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_axi_ctrl_REG_ADDR); \
  1232. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1233. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1234. MA_OUTW(clk_venc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1235. }
  1236. #define _DISABLE_CLOCK_clk_venc_axi_ { \
  1237. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_axi_ctrl_REG_ADDR); \
  1238. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1239. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1240. MA_OUTW(clk_venc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1241. }
  1242. #define _GET_CLOCK_ENABLE_STATUS_clk_venc_axi_(_ezchip_macro_read_value_) { \
  1243. _ezchip_macro_read_value_=MA_INW(clk_venc_axi_ctrl_REG_ADDR) >> 31; \
  1244. _ezchip_macro_read_value_ &= 0x1;\
  1245. }
  1246. #define _ENABLE_CLOCK_clk_vencbrg_mainclk_ { \
  1247. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vencbrg_mainclk_ctrl_REG_ADDR); \
  1248. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1249. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1250. MA_OUTW(clk_vencbrg_mainclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1251. }
  1252. #define _DISABLE_CLOCK_clk_vencbrg_mainclk_ { \
  1253. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vencbrg_mainclk_ctrl_REG_ADDR); \
  1254. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1255. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1256. MA_OUTW(clk_vencbrg_mainclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1257. }
  1258. #define _GET_CLOCK_ENABLE_STATUS_clk_vencbrg_mainclk_(_ezchip_macro_read_value_) { \
  1259. _ezchip_macro_read_value_=MA_INW(clk_vencbrg_mainclk_ctrl_REG_ADDR) >> 31; \
  1260. _ezchip_macro_read_value_ &= 0x1;\
  1261. }
  1262. #define _ENABLE_CLOCK_clk_venc_bclk_ { \
  1263. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_bclk_ctrl_REG_ADDR); \
  1264. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1265. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1266. MA_OUTW(clk_venc_bclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1267. }
  1268. #define _DISABLE_CLOCK_clk_venc_bclk_ { \
  1269. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_bclk_ctrl_REG_ADDR); \
  1270. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1271. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1272. MA_OUTW(clk_venc_bclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1273. }
  1274. #define _GET_CLOCK_ENABLE_STATUS_clk_venc_bclk_(_ezchip_macro_read_value_) { \
  1275. _ezchip_macro_read_value_=MA_INW(clk_venc_bclk_ctrl_REG_ADDR) >> 31; \
  1276. _ezchip_macro_read_value_ &= 0x1;\
  1277. }
  1278. #define _DIVIDE_CLOCK_clk_venc_bclk_(div) { \
  1279. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_bclk_ctrl_REG_ADDR); \
  1280. _ezchip_macro_read_value_ &= ~(0xF); \
  1281. _ezchip_macro_read_value_ |= (div&0xF); \
  1282. MA_OUTW(clk_venc_bclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1283. }
  1284. #define _GET_CLOCK_DIVIDE_STATUS_clk_venc_bclk_(_ezchip_macro_read_value_) { \
  1285. _ezchip_macro_read_value_=MA_INW(clk_venc_bclk_ctrl_REG_ADDR); \
  1286. _ezchip_macro_read_value_ &= 0xf;\
  1287. }
  1288. #define _ENABLE_CLOCK_clk_venc_cclk_ { \
  1289. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_cclk_ctrl_REG_ADDR); \
  1290. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1291. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1292. MA_OUTW(clk_venc_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1293. }
  1294. #define _DISABLE_CLOCK_clk_venc_cclk_ { \
  1295. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_cclk_ctrl_REG_ADDR); \
  1296. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1297. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1298. MA_OUTW(clk_venc_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1299. }
  1300. #define _GET_CLOCK_ENABLE_STATUS_clk_venc_cclk_(_ezchip_macro_read_value_) { \
  1301. _ezchip_macro_read_value_=MA_INW(clk_venc_cclk_ctrl_REG_ADDR) >> 31; \
  1302. _ezchip_macro_read_value_ &= 0x1;\
  1303. }
  1304. #define _DIVIDE_CLOCK_clk_venc_cclk_(div) { \
  1305. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_cclk_ctrl_REG_ADDR); \
  1306. _ezchip_macro_read_value_ &= ~(0xF); \
  1307. _ezchip_macro_read_value_ |= (div&0xF); \
  1308. MA_OUTW(clk_venc_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1309. }
  1310. #define _GET_CLOCK_DIVIDE_STATUS_clk_venc_cclk_(_ezchip_macro_read_value_) { \
  1311. _ezchip_macro_read_value_=MA_INW(clk_venc_cclk_ctrl_REG_ADDR); \
  1312. _ezchip_macro_read_value_ &= 0xf;\
  1313. }
  1314. #define _ENABLE_CLOCK_clk_venc_apb_ { \
  1315. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_apb_ctrl_REG_ADDR); \
  1316. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1317. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1318. MA_OUTW(clk_venc_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1319. }
  1320. #define _DISABLE_CLOCK_clk_venc_apb_ { \
  1321. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_apb_ctrl_REG_ADDR); \
  1322. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1323. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1324. MA_OUTW(clk_venc_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1325. }
  1326. #define _GET_CLOCK_ENABLE_STATUS_clk_venc_apb_(_ezchip_macro_read_value_) { \
  1327. _ezchip_macro_read_value_=MA_INW(clk_venc_apb_ctrl_REG_ADDR) >> 31; \
  1328. _ezchip_macro_read_value_ &= 0x1;\
  1329. }
  1330. #define _ENABLE_CLOCK_clk_ddrpll_div2_ { \
  1331. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div2_ctrl_REG_ADDR); \
  1332. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1333. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1334. MA_OUTW(clk_ddrpll_div2_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1335. }
  1336. #define _DISABLE_CLOCK_clk_ddrpll_div2_ { \
  1337. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div2_ctrl_REG_ADDR); \
  1338. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1339. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1340. MA_OUTW(clk_ddrpll_div2_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1341. }
  1342. #define _GET_CLOCK_ENABLE_STATUS_clk_ddrpll_div2_(_ezchip_macro_read_value_) { \
  1343. _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div2_ctrl_REG_ADDR) >> 31; \
  1344. _ezchip_macro_read_value_ &= 0x1;\
  1345. }
  1346. #define _DIVIDE_CLOCK_clk_ddrpll_div2_(div) { \
  1347. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div2_ctrl_REG_ADDR); \
  1348. _ezchip_macro_read_value_ &= ~(0x3); \
  1349. _ezchip_macro_read_value_ |= (div&0x3); \
  1350. MA_OUTW(clk_ddrpll_div2_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1351. }
  1352. #define _GET_CLOCK_DIVIDE_STATUS_clk_ddrpll_div2_(_ezchip_macro_read_value_) { \
  1353. _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div2_ctrl_REG_ADDR); \
  1354. _ezchip_macro_read_value_ &= 0x3;\
  1355. }
  1356. #define _ENABLE_CLOCK_clk_ddrpll_div4_ { \
  1357. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div4_ctrl_REG_ADDR); \
  1358. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1359. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1360. MA_OUTW(clk_ddrpll_div4_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1361. }
  1362. #define _DISABLE_CLOCK_clk_ddrpll_div4_ { \
  1363. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div4_ctrl_REG_ADDR); \
  1364. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1365. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1366. MA_OUTW(clk_ddrpll_div4_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1367. }
  1368. #define _GET_CLOCK_ENABLE_STATUS_clk_ddrpll_div4_(_ezchip_macro_read_value_) { \
  1369. _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div4_ctrl_REG_ADDR) >> 31; \
  1370. _ezchip_macro_read_value_ &= 0x1;\
  1371. }
  1372. #define _DIVIDE_CLOCK_clk_ddrpll_div4_(div) { \
  1373. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div4_ctrl_REG_ADDR); \
  1374. _ezchip_macro_read_value_ &= ~(0x3); \
  1375. _ezchip_macro_read_value_ |= (div&0x3); \
  1376. MA_OUTW(clk_ddrpll_div4_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1377. }
  1378. #define _GET_CLOCK_DIVIDE_STATUS_clk_ddrpll_div4_(_ezchip_macro_read_value_) { \
  1379. _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div4_ctrl_REG_ADDR); \
  1380. _ezchip_macro_read_value_ &= 0x3;\
  1381. }
  1382. #define _ENABLE_CLOCK_clk_ddrpll_div8_ { \
  1383. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div8_ctrl_REG_ADDR); \
  1384. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1385. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1386. MA_OUTW(clk_ddrpll_div8_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1387. }
  1388. #define _DISABLE_CLOCK_clk_ddrpll_div8_ { \
  1389. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div8_ctrl_REG_ADDR); \
  1390. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1391. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1392. MA_OUTW(clk_ddrpll_div8_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1393. }
  1394. #define _GET_CLOCK_ENABLE_STATUS_clk_ddrpll_div8_(_ezchip_macro_read_value_) { \
  1395. _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div8_ctrl_REG_ADDR) >> 31; \
  1396. _ezchip_macro_read_value_ &= 0x1;\
  1397. }
  1398. #define _DIVIDE_CLOCK_clk_ddrpll_div8_(div) { \
  1399. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div8_ctrl_REG_ADDR); \
  1400. _ezchip_macro_read_value_ &= ~(0x3); \
  1401. _ezchip_macro_read_value_ |= (div&0x3); \
  1402. MA_OUTW(clk_ddrpll_div8_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1403. }
  1404. #define _GET_CLOCK_DIVIDE_STATUS_clk_ddrpll_div8_(_ezchip_macro_read_value_) { \
  1405. _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div8_ctrl_REG_ADDR); \
  1406. _ezchip_macro_read_value_ &= 0x3;\
  1407. }
  1408. #define _ENABLE_CLOCK_clk_ddrosc_div2_ { \
  1409. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrosc_div2_ctrl_REG_ADDR); \
  1410. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1411. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1412. MA_OUTW(clk_ddrosc_div2_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1413. }
  1414. #define _DISABLE_CLOCK_clk_ddrosc_div2_ { \
  1415. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrosc_div2_ctrl_REG_ADDR); \
  1416. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1417. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1418. MA_OUTW(clk_ddrosc_div2_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1419. }
  1420. #define _GET_CLOCK_ENABLE_STATUS_clk_ddrosc_div2_(_ezchip_macro_read_value_) { \
  1421. _ezchip_macro_read_value_=MA_INW(clk_ddrosc_div2_ctrl_REG_ADDR) >> 31; \
  1422. _ezchip_macro_read_value_ &= 0x1;\
  1423. }
  1424. #define _DIVIDE_CLOCK_clk_ddrosc_div2_(div) { \
  1425. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrosc_div2_ctrl_REG_ADDR); \
  1426. _ezchip_macro_read_value_ &= ~(0x3); \
  1427. _ezchip_macro_read_value_ |= (div&0x3); \
  1428. MA_OUTW(clk_ddrosc_div2_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1429. }
  1430. #define _GET_CLOCK_DIVIDE_STATUS_clk_ddrosc_div2_(_ezchip_macro_read_value_) { \
  1431. _ezchip_macro_read_value_=MA_INW(clk_ddrosc_div2_ctrl_REG_ADDR); \
  1432. _ezchip_macro_read_value_ &= 0x3;\
  1433. }
  1434. #define _ENABLE_CLOCK_clk_ddrc0_ { \
  1435. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR); \
  1436. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1437. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1438. MA_OUTW(clk_ddrc0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1439. }
  1440. #define _DISABLE_CLOCK_clk_ddrc0_ { \
  1441. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR); \
  1442. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1443. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1444. MA_OUTW(clk_ddrc0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1445. }
  1446. #define _GET_CLOCK_ENABLE_STATUS_clk_ddrc0_(_ezchip_macro_read_value_) { \
  1447. _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR) >> 31; \
  1448. _ezchip_macro_read_value_ &= 0x1;\
  1449. }
  1450. #define _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrosc_div2_ { \
  1451. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR); \
  1452. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  1453. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  1454. MA_OUTW(clk_ddrc0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1455. }
  1456. #define _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div2_ { \
  1457. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR); \
  1458. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  1459. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  1460. MA_OUTW(clk_ddrc0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1461. }
  1462. #define _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div4_ { \
  1463. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR); \
  1464. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  1465. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  1466. MA_OUTW(clk_ddrc0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1467. }
  1468. #define _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div8_ { \
  1469. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR); \
  1470. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  1471. _ezchip_macro_read_value_ |= (0x3&0x3)<<24; \
  1472. MA_OUTW(clk_ddrc0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1473. }
  1474. #define _GET_CLOCK_SOURCE_STATUS_clk_ddrc0_(_ezchip_macro_read_value_) { \
  1475. _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR) >> 24; \
  1476. _ezchip_macro_read_value_ &= 0x3;\
  1477. }
  1478. #define _ENABLE_CLOCK_clk_ddrc1_ { \
  1479. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR); \
  1480. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1481. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1482. MA_OUTW(clk_ddrc1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1483. }
  1484. #define _DISABLE_CLOCK_clk_ddrc1_ { \
  1485. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR); \
  1486. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1487. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1488. MA_OUTW(clk_ddrc1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1489. }
  1490. #define _GET_CLOCK_ENABLE_STATUS_clk_ddrc1_(_ezchip_macro_read_value_) { \
  1491. _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR) >> 31; \
  1492. _ezchip_macro_read_value_ &= 0x1;\
  1493. }
  1494. #define _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrosc_div2_ { \
  1495. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR); \
  1496. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  1497. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  1498. MA_OUTW(clk_ddrc1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1499. }
  1500. #define _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div2_ { \
  1501. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR); \
  1502. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  1503. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  1504. MA_OUTW(clk_ddrc1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1505. }
  1506. #define _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div4_ { \
  1507. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR); \
  1508. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  1509. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  1510. MA_OUTW(clk_ddrc1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1511. }
  1512. #define _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div8_ { \
  1513. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR); \
  1514. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  1515. _ezchip_macro_read_value_ |= (0x3&0x3)<<24; \
  1516. MA_OUTW(clk_ddrc1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1517. }
  1518. #define _GET_CLOCK_SOURCE_STATUS_clk_ddrc1_(_ezchip_macro_read_value_) { \
  1519. _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR) >> 24; \
  1520. _ezchip_macro_read_value_ &= 0x3;\
  1521. }
  1522. #define _ENABLE_CLOCK_clk_ddrphy_apb_ { \
  1523. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrphy_apb_ctrl_REG_ADDR); \
  1524. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1525. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1526. MA_OUTW(clk_ddrphy_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1527. }
  1528. #define _DISABLE_CLOCK_clk_ddrphy_apb_ { \
  1529. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrphy_apb_ctrl_REG_ADDR); \
  1530. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1531. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1532. MA_OUTW(clk_ddrphy_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1533. }
  1534. #define _GET_CLOCK_ENABLE_STATUS_clk_ddrphy_apb_(_ezchip_macro_read_value_) { \
  1535. _ezchip_macro_read_value_=MA_INW(clk_ddrphy_apb_ctrl_REG_ADDR) >> 31; \
  1536. _ezchip_macro_read_value_ &= 0x1;\
  1537. }
  1538. #define _ENABLE_CLOCK_clk_noc_rob_ {}
  1539. #define _DIVIDE_CLOCK_clk_noc_rob_(div) { \
  1540. uint32_t _ezchip_macro_read_value_=MA_INW(clk_noc_rob_ctrl_REG_ADDR); \
  1541. _ezchip_macro_read_value_ &= ~(0xF); \
  1542. _ezchip_macro_read_value_ |= (div&0xF); \
  1543. MA_OUTW(clk_noc_rob_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1544. }
  1545. #define _GET_CLOCK_DIVIDE_STATUS_clk_noc_rob_(_ezchip_macro_read_value_) { \
  1546. _ezchip_macro_read_value_=MA_INW(clk_noc_rob_ctrl_REG_ADDR); \
  1547. _ezchip_macro_read_value_ &= 0xf;\
  1548. }
  1549. #define _ENABLE_CLOCK_clk_noc_cog_ {}
  1550. #define _DIVIDE_CLOCK_clk_noc_cog_(div) { \
  1551. uint32_t _ezchip_macro_read_value_=MA_INW(clk_noc_cog_ctrl_REG_ADDR); \
  1552. _ezchip_macro_read_value_ &= ~(0xF); \
  1553. _ezchip_macro_read_value_ |= (div&0xF); \
  1554. MA_OUTW(clk_noc_cog_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1555. }
  1556. #define _GET_CLOCK_DIVIDE_STATUS_clk_noc_cog_(_ezchip_macro_read_value_) { \
  1557. _ezchip_macro_read_value_=MA_INW(clk_noc_cog_ctrl_REG_ADDR); \
  1558. _ezchip_macro_read_value_ &= 0xf;\
  1559. }
  1560. #define _ENABLE_CLOCK_clk_nne_ahb_ { \
  1561. uint32_t _ezchip_macro_read_value_=MA_INW(clk_nne_ahb_ctrl_REG_ADDR); \
  1562. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1563. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1564. MA_OUTW(clk_nne_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1565. }
  1566. #define _DISABLE_CLOCK_clk_nne_ahb_ { \
  1567. uint32_t _ezchip_macro_read_value_=MA_INW(clk_nne_ahb_ctrl_REG_ADDR); \
  1568. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1569. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1570. MA_OUTW(clk_nne_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1571. }
  1572. #define _GET_CLOCK_ENABLE_STATUS_clk_nne_ahb_(_ezchip_macro_read_value_) { \
  1573. _ezchip_macro_read_value_=MA_INW(clk_nne_ahb_ctrl_REG_ADDR) >> 31; \
  1574. _ezchip_macro_read_value_ &= 0x1;\
  1575. }
  1576. #define _ENABLE_CLOCK_clk_nnebus_src1_ {}
  1577. #define _DIVIDE_CLOCK_clk_nnebus_src1_(div) { \
  1578. uint32_t _ezchip_macro_read_value_=MA_INW(clk_nnebus_src1_ctrl_REG_ADDR); \
  1579. _ezchip_macro_read_value_ &= ~(0x7); \
  1580. _ezchip_macro_read_value_ |= (div&0x7); \
  1581. MA_OUTW(clk_nnebus_src1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1582. }
  1583. #define _GET_CLOCK_DIVIDE_STATUS_clk_nnebus_src1_(_ezchip_macro_read_value_) { \
  1584. _ezchip_macro_read_value_=MA_INW(clk_nnebus_src1_ctrl_REG_ADDR); \
  1585. _ezchip_macro_read_value_ &= 0x7;\
  1586. }
  1587. #define _ENABLE_CLOCK_clk_nne_bus_ {}
  1588. #define _SWITCH_CLOCK_clk_nne_bus_SOURCE_clk_cpu_axi_ { \
  1589. uint32_t _ezchip_macro_read_value_=MA_INW(clk_nne_bus_ctrl_REG_ADDR); \
  1590. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  1591. _ezchip_macro_read_value_ |= (0x0&0x1)<<24; \
  1592. MA_OUTW(clk_nne_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1593. }
  1594. #define _SWITCH_CLOCK_clk_nne_bus_SOURCE_clk_nnebus_src1_ { \
  1595. uint32_t _ezchip_macro_read_value_=MA_INW(clk_nne_bus_ctrl_REG_ADDR); \
  1596. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  1597. _ezchip_macro_read_value_ |= (0x1&0x1)<<24; \
  1598. MA_OUTW(clk_nne_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1599. }
  1600. #define _GET_CLOCK_SOURCE_STATUS_clk_nne_bus_(_ezchip_macro_read_value_) { \
  1601. _ezchip_macro_read_value_=MA_INW(clk_nne_bus_ctrl_REG_ADDR) >> 24; \
  1602. _ezchip_macro_read_value_ &= 0x1;\
  1603. }
  1604. #define _ENABLE_CLOCK_clk_nne_axi_ { \
  1605. uint32_t _ezchip_macro_read_value_=MA_INW(clk_nne_axi_ctrl_REG_ADDR); \
  1606. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1607. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1608. MA_OUTW(clk_nne_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1609. }
  1610. #define _DISABLE_CLOCK_clk_nne_axi_ { \
  1611. uint32_t _ezchip_macro_read_value_=MA_INW(clk_nne_axi_ctrl_REG_ADDR); \
  1612. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1613. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1614. MA_OUTW(clk_nne_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1615. }
  1616. #define _GET_CLOCK_ENABLE_STATUS_clk_nne_axi_(_ezchip_macro_read_value_) { \
  1617. _ezchip_macro_read_value_=MA_INW(clk_nne_axi_ctrl_REG_ADDR) >> 31; \
  1618. _ezchip_macro_read_value_ &= 0x1;\
  1619. }
  1620. #define _ENABLE_CLOCK_clk_nnenoc_axi_ { \
  1621. uint32_t _ezchip_macro_read_value_=MA_INW(clk_nnenoc_axi_ctrl_REG_ADDR); \
  1622. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1623. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1624. MA_OUTW(clk_nnenoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1625. }
  1626. #define _DISABLE_CLOCK_clk_nnenoc_axi_ { \
  1627. uint32_t _ezchip_macro_read_value_=MA_INW(clk_nnenoc_axi_ctrl_REG_ADDR); \
  1628. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1629. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1630. MA_OUTW(clk_nnenoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1631. }
  1632. #define _GET_CLOCK_ENABLE_STATUS_clk_nnenoc_axi_(_ezchip_macro_read_value_) { \
  1633. _ezchip_macro_read_value_=MA_INW(clk_nnenoc_axi_ctrl_REG_ADDR) >> 31; \
  1634. _ezchip_macro_read_value_ &= 0x1;\
  1635. }
  1636. #define _ENABLE_CLOCK_clk_dlaslv_axi_ { \
  1637. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dlaslv_axi_ctrl_REG_ADDR); \
  1638. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1639. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1640. MA_OUTW(clk_dlaslv_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1641. }
  1642. #define _DISABLE_CLOCK_clk_dlaslv_axi_ { \
  1643. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dlaslv_axi_ctrl_REG_ADDR); \
  1644. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1645. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1646. MA_OUTW(clk_dlaslv_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1647. }
  1648. #define _GET_CLOCK_ENABLE_STATUS_clk_dlaslv_axi_(_ezchip_macro_read_value_) { \
  1649. _ezchip_macro_read_value_=MA_INW(clk_dlaslv_axi_ctrl_REG_ADDR) >> 31; \
  1650. _ezchip_macro_read_value_ &= 0x1;\
  1651. }
  1652. #define _ENABLE_CLOCK_clk_dspx2c_axi_ { \
  1653. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dspx2c_axi_ctrl_REG_ADDR); \
  1654. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1655. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1656. MA_OUTW(clk_dspx2c_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1657. }
  1658. #define _DISABLE_CLOCK_clk_dspx2c_axi_ { \
  1659. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dspx2c_axi_ctrl_REG_ADDR); \
  1660. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1661. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1662. MA_OUTW(clk_dspx2c_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1663. }
  1664. #define _GET_CLOCK_ENABLE_STATUS_clk_dspx2c_axi_(_ezchip_macro_read_value_) { \
  1665. _ezchip_macro_read_value_=MA_INW(clk_dspx2c_axi_ctrl_REG_ADDR) >> 31; \
  1666. _ezchip_macro_read_value_ &= 0x1;\
  1667. }
  1668. #define _ENABLE_CLOCK_clk_hifi4_src_ {}
  1669. #define _DIVIDE_CLOCK_clk_hifi4_src_(div) { \
  1670. uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4_src_ctrl_REG_ADDR); \
  1671. _ezchip_macro_read_value_ &= ~(0x7); \
  1672. _ezchip_macro_read_value_ |= (div&0x7); \
  1673. MA_OUTW(clk_hifi4_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1674. }
  1675. #define _GET_CLOCK_DIVIDE_STATUS_clk_hifi4_src_(_ezchip_macro_read_value_) { \
  1676. _ezchip_macro_read_value_=MA_INW(clk_hifi4_src_ctrl_REG_ADDR); \
  1677. _ezchip_macro_read_value_ &= 0x7;\
  1678. }
  1679. #define _ENABLE_CLOCK_clk_hifi4_corefree_ {}
  1680. #define _DIVIDE_CLOCK_clk_hifi4_corefree_(div) { \
  1681. uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4_corefree_ctrl_REG_ADDR); \
  1682. _ezchip_macro_read_value_ &= ~(0xF); \
  1683. _ezchip_macro_read_value_ |= (div&0xF); \
  1684. MA_OUTW(clk_hifi4_corefree_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1685. }
  1686. #define _GET_CLOCK_DIVIDE_STATUS_clk_hifi4_corefree_(_ezchip_macro_read_value_) { \
  1687. _ezchip_macro_read_value_=MA_INW(clk_hifi4_corefree_ctrl_REG_ADDR); \
  1688. _ezchip_macro_read_value_ &= 0xf;\
  1689. }
  1690. #define _ENABLE_CLOCK_clk_hifi4_core_ { \
  1691. uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4_core_ctrl_REG_ADDR); \
  1692. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1693. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1694. MA_OUTW(clk_hifi4_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1695. }
  1696. #define _DISABLE_CLOCK_clk_hifi4_core_ { \
  1697. uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4_core_ctrl_REG_ADDR); \
  1698. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1699. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1700. MA_OUTW(clk_hifi4_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1701. }
  1702. #define _GET_CLOCK_ENABLE_STATUS_clk_hifi4_core_(_ezchip_macro_read_value_) { \
  1703. _ezchip_macro_read_value_=MA_INW(clk_hifi4_core_ctrl_REG_ADDR) >> 31; \
  1704. _ezchip_macro_read_value_ &= 0x1;\
  1705. }
  1706. #define _ENABLE_CLOCK_clk_hifi4_bus_ {}
  1707. #define _DIVIDE_CLOCK_clk_hifi4_bus_(div) { \
  1708. uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4_bus_ctrl_REG_ADDR); \
  1709. _ezchip_macro_read_value_ &= ~(0xF); \
  1710. _ezchip_macro_read_value_ |= (div&0xF); \
  1711. MA_OUTW(clk_hifi4_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1712. }
  1713. #define _GET_CLOCK_DIVIDE_STATUS_clk_hifi4_bus_(_ezchip_macro_read_value_) { \
  1714. _ezchip_macro_read_value_=MA_INW(clk_hifi4_bus_ctrl_REG_ADDR); \
  1715. _ezchip_macro_read_value_ &= 0xf;\
  1716. }
  1717. #define _ENABLE_CLOCK_clk_hifi4_axi_ { \
  1718. uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4_axi_ctrl_REG_ADDR); \
  1719. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1720. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1721. MA_OUTW(clk_hifi4_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1722. }
  1723. #define _DISABLE_CLOCK_clk_hifi4_axi_ { \
  1724. uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4_axi_ctrl_REG_ADDR); \
  1725. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1726. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1727. MA_OUTW(clk_hifi4_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1728. }
  1729. #define _GET_CLOCK_ENABLE_STATUS_clk_hifi4_axi_(_ezchip_macro_read_value_) { \
  1730. _ezchip_macro_read_value_=MA_INW(clk_hifi4_axi_ctrl_REG_ADDR) >> 31; \
  1731. _ezchip_macro_read_value_ &= 0x1;\
  1732. }
  1733. #define _ENABLE_CLOCK_clk_hifi4noc_axi_ { \
  1734. uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4noc_axi_ctrl_REG_ADDR); \
  1735. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1736. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1737. MA_OUTW(clk_hifi4noc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1738. }
  1739. #define _DISABLE_CLOCK_clk_hifi4noc_axi_ { \
  1740. uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4noc_axi_ctrl_REG_ADDR); \
  1741. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1742. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1743. MA_OUTW(clk_hifi4noc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1744. }
  1745. #define _GET_CLOCK_ENABLE_STATUS_clk_hifi4noc_axi_(_ezchip_macro_read_value_) { \
  1746. _ezchip_macro_read_value_=MA_INW(clk_hifi4noc_axi_ctrl_REG_ADDR) >> 31; \
  1747. _ezchip_macro_read_value_ &= 0x1;\
  1748. }
  1749. #define _ENABLE_CLOCK_clk_sgdma1p_bus_ {}
  1750. #define _DIVIDE_CLOCK_clk_sgdma1p_bus_(div) { \
  1751. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sgdma1p_bus_ctrl_REG_ADDR); \
  1752. _ezchip_macro_read_value_ &= ~(0xF); \
  1753. _ezchip_macro_read_value_ |= (div&0xF); \
  1754. MA_OUTW(clk_sgdma1p_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1755. }
  1756. #define _GET_CLOCK_DIVIDE_STATUS_clk_sgdma1p_bus_(_ezchip_macro_read_value_) { \
  1757. _ezchip_macro_read_value_=MA_INW(clk_sgdma1p_bus_ctrl_REG_ADDR); \
  1758. _ezchip_macro_read_value_ &= 0xf;\
  1759. }
  1760. #define _ENABLE_CLOCK_clk_sgdma1p_axi_ { \
  1761. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sgdma1p_axi_ctrl_REG_ADDR); \
  1762. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1763. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1764. MA_OUTW(clk_sgdma1p_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1765. }
  1766. #define _DISABLE_CLOCK_clk_sgdma1p_axi_ { \
  1767. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sgdma1p_axi_ctrl_REG_ADDR); \
  1768. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1769. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1770. MA_OUTW(clk_sgdma1p_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1771. }
  1772. #define _GET_CLOCK_ENABLE_STATUS_clk_sgdma1p_axi_(_ezchip_macro_read_value_) { \
  1773. _ezchip_macro_read_value_=MA_INW(clk_sgdma1p_axi_ctrl_REG_ADDR) >> 31; \
  1774. _ezchip_macro_read_value_ &= 0x1;\
  1775. }
  1776. #define _ENABLE_CLOCK_clk_dma1p_axi_ { \
  1777. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dma1p_axi_ctrl_REG_ADDR); \
  1778. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1779. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1780. MA_OUTW(clk_dma1p_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1781. }
  1782. #define _DISABLE_CLOCK_clk_dma1p_axi_ { \
  1783. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dma1p_axi_ctrl_REG_ADDR); \
  1784. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1785. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1786. MA_OUTW(clk_dma1p_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1787. }
  1788. #define _GET_CLOCK_ENABLE_STATUS_clk_dma1p_axi_(_ezchip_macro_read_value_) { \
  1789. _ezchip_macro_read_value_=MA_INW(clk_dma1p_axi_ctrl_REG_ADDR) >> 31; \
  1790. _ezchip_macro_read_value_ &= 0x1;\
  1791. }
  1792. #define _ENABLE_CLOCK_clk_x2c_axi_ { \
  1793. uint32_t _ezchip_macro_read_value_=MA_INW(clk_x2c_axi_ctrl_REG_ADDR); \
  1794. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1795. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1796. MA_OUTW(clk_x2c_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1797. }
  1798. #define _DISABLE_CLOCK_clk_x2c_axi_ { \
  1799. uint32_t _ezchip_macro_read_value_=MA_INW(clk_x2c_axi_ctrl_REG_ADDR); \
  1800. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1801. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1802. MA_OUTW(clk_x2c_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1803. }
  1804. #define _GET_CLOCK_ENABLE_STATUS_clk_x2c_axi_(_ezchip_macro_read_value_) { \
  1805. _ezchip_macro_read_value_=MA_INW(clk_x2c_axi_ctrl_REG_ADDR) >> 31; \
  1806. _ezchip_macro_read_value_ &= 0x1;\
  1807. }
  1808. #define _DIVIDE_CLOCK_clk_x2c_axi_(div) { \
  1809. uint32_t _ezchip_macro_read_value_=MA_INW(clk_x2c_axi_ctrl_REG_ADDR); \
  1810. _ezchip_macro_read_value_ &= ~(0xF); \
  1811. _ezchip_macro_read_value_ |= (div&0xF); \
  1812. MA_OUTW(clk_x2c_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1813. }
  1814. #define _GET_CLOCK_DIVIDE_STATUS_clk_x2c_axi_(_ezchip_macro_read_value_) { \
  1815. _ezchip_macro_read_value_=MA_INW(clk_x2c_axi_ctrl_REG_ADDR); \
  1816. _ezchip_macro_read_value_ &= 0xf;\
  1817. }
  1818. #define _ENABLE_CLOCK_clk_usb_bus_ {}
  1819. #define _DIVIDE_CLOCK_clk_usb_bus_(div) { \
  1820. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usb_bus_ctrl_REG_ADDR); \
  1821. _ezchip_macro_read_value_ &= ~(0xF); \
  1822. _ezchip_macro_read_value_ |= (div&0xF); \
  1823. MA_OUTW(clk_usb_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1824. }
  1825. #define _GET_CLOCK_DIVIDE_STATUS_clk_usb_bus_(_ezchip_macro_read_value_) { \
  1826. _ezchip_macro_read_value_=MA_INW(clk_usb_bus_ctrl_REG_ADDR); \
  1827. _ezchip_macro_read_value_ &= 0xf;\
  1828. }
  1829. #define _ENABLE_CLOCK_clk_usb_axi_ { \
  1830. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usb_axi_ctrl_REG_ADDR); \
  1831. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1832. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1833. MA_OUTW(clk_usb_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1834. }
  1835. #define _DISABLE_CLOCK_clk_usb_axi_ { \
  1836. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usb_axi_ctrl_REG_ADDR); \
  1837. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1838. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1839. MA_OUTW(clk_usb_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1840. }
  1841. #define _GET_CLOCK_ENABLE_STATUS_clk_usb_axi_(_ezchip_macro_read_value_) { \
  1842. _ezchip_macro_read_value_=MA_INW(clk_usb_axi_ctrl_REG_ADDR) >> 31; \
  1843. _ezchip_macro_read_value_ &= 0x1;\
  1844. }
  1845. #define _ENABLE_CLOCK_clk_usbnoc_axi_ { \
  1846. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbnoc_axi_ctrl_REG_ADDR); \
  1847. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1848. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1849. MA_OUTW(clk_usbnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1850. }
  1851. #define _DISABLE_CLOCK_clk_usbnoc_axi_ { \
  1852. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbnoc_axi_ctrl_REG_ADDR); \
  1853. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1854. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1855. MA_OUTW(clk_usbnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1856. }
  1857. #define _GET_CLOCK_ENABLE_STATUS_clk_usbnoc_axi_(_ezchip_macro_read_value_) { \
  1858. _ezchip_macro_read_value_=MA_INW(clk_usbnoc_axi_ctrl_REG_ADDR) >> 31; \
  1859. _ezchip_macro_read_value_ &= 0x1;\
  1860. }
  1861. #define _ENABLE_CLOCK_clk_usbphy_rootdiv_ {}
  1862. #define _DIVIDE_CLOCK_clk_usbphy_rootdiv_(div) { \
  1863. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_rootdiv_ctrl_REG_ADDR); \
  1864. _ezchip_macro_read_value_ &= ~(0x7); \
  1865. _ezchip_macro_read_value_ |= (div&0x7); \
  1866. MA_OUTW(clk_usbphy_rootdiv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1867. }
  1868. #define _GET_CLOCK_DIVIDE_STATUS_clk_usbphy_rootdiv_(_ezchip_macro_read_value_) { \
  1869. _ezchip_macro_read_value_=MA_INW(clk_usbphy_rootdiv_ctrl_REG_ADDR); \
  1870. _ezchip_macro_read_value_ &= 0x7;\
  1871. }
  1872. #define _ENABLE_CLOCK_clk_usbphy_125m_ { \
  1873. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_125m_ctrl_REG_ADDR); \
  1874. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1875. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1876. MA_OUTW(clk_usbphy_125m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1877. }
  1878. #define _DISABLE_CLOCK_clk_usbphy_125m_ { \
  1879. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_125m_ctrl_REG_ADDR); \
  1880. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1881. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1882. MA_OUTW(clk_usbphy_125m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1883. }
  1884. #define _GET_CLOCK_ENABLE_STATUS_clk_usbphy_125m_(_ezchip_macro_read_value_) { \
  1885. _ezchip_macro_read_value_=MA_INW(clk_usbphy_125m_ctrl_REG_ADDR) >> 31; \
  1886. _ezchip_macro_read_value_ &= 0x1;\
  1887. }
  1888. #define _DIVIDE_CLOCK_clk_usbphy_125m_(div) { \
  1889. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_125m_ctrl_REG_ADDR); \
  1890. _ezchip_macro_read_value_ &= ~(0xF); \
  1891. _ezchip_macro_read_value_ |= (div&0xF); \
  1892. MA_OUTW(clk_usbphy_125m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1893. }
  1894. #define _GET_CLOCK_DIVIDE_STATUS_clk_usbphy_125m_(_ezchip_macro_read_value_) { \
  1895. _ezchip_macro_read_value_=MA_INW(clk_usbphy_125m_ctrl_REG_ADDR); \
  1896. _ezchip_macro_read_value_ &= 0xf;\
  1897. }
  1898. #define _ENABLE_CLOCK_clk_usbphy_plldiv25m_ { \
  1899. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_plldiv25m_ctrl_REG_ADDR); \
  1900. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1901. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1902. MA_OUTW(clk_usbphy_plldiv25m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1903. }
  1904. #define _DISABLE_CLOCK_clk_usbphy_plldiv25m_ { \
  1905. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_plldiv25m_ctrl_REG_ADDR); \
  1906. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1907. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1908. MA_OUTW(clk_usbphy_plldiv25m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1909. }
  1910. #define _GET_CLOCK_ENABLE_STATUS_clk_usbphy_plldiv25m_(_ezchip_macro_read_value_) { \
  1911. _ezchip_macro_read_value_=MA_INW(clk_usbphy_plldiv25m_ctrl_REG_ADDR) >> 31; \
  1912. _ezchip_macro_read_value_ &= 0x1;\
  1913. }
  1914. #define _DIVIDE_CLOCK_clk_usbphy_plldiv25m_(div) { \
  1915. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_plldiv25m_ctrl_REG_ADDR); \
  1916. _ezchip_macro_read_value_ &= ~(0x3F); \
  1917. _ezchip_macro_read_value_ |= (div&0x3F); \
  1918. MA_OUTW(clk_usbphy_plldiv25m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1919. }
  1920. #define _GET_CLOCK_DIVIDE_STATUS_clk_usbphy_plldiv25m_(_ezchip_macro_read_value_) { \
  1921. _ezchip_macro_read_value_=MA_INW(clk_usbphy_plldiv25m_ctrl_REG_ADDR); \
  1922. _ezchip_macro_read_value_ &= 0x3f;\
  1923. }
  1924. #define _ENABLE_CLOCK_clk_usbphy_25m_ {}
  1925. #define _SWITCH_CLOCK_clk_usbphy_25m_SOURCE_clk_osc_sys_ { \
  1926. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_25m_ctrl_REG_ADDR); \
  1927. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  1928. _ezchip_macro_read_value_ |= (0x0&0x1)<<24; \
  1929. MA_OUTW(clk_usbphy_25m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1930. }
  1931. #define _SWITCH_CLOCK_clk_usbphy_25m_SOURCE_clk_usbphy_plldiv25m_ { \
  1932. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_25m_ctrl_REG_ADDR); \
  1933. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  1934. _ezchip_macro_read_value_ |= (0x1&0x1)<<24; \
  1935. MA_OUTW(clk_usbphy_25m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1936. }
  1937. #define _GET_CLOCK_SOURCE_STATUS_clk_usbphy_25m_(_ezchip_macro_read_value_) { \
  1938. _ezchip_macro_read_value_=MA_INW(clk_usbphy_25m_ctrl_REG_ADDR) >> 24; \
  1939. _ezchip_macro_read_value_ &= 0x1;\
  1940. }
  1941. #define _ENABLE_CLOCK_clk_audio_div_ {}
  1942. #define _DIVIDE_CLOCK_clk_audio_div_(div) { \
  1943. uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_div_ctrl_REG_ADDR); \
  1944. _ezchip_macro_read_value_ &= ~(0x3FFFF); \
  1945. _ezchip_macro_read_value_ |= (div&0x3FFFF); \
  1946. MA_OUTW(clk_audio_div_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1947. }
  1948. #define _GET_CLOCK_DIVIDE_STATUS_clk_audio_div_(_ezchip_macro_read_value_) { \
  1949. _ezchip_macro_read_value_=MA_INW(clk_audio_div_ctrl_REG_ADDR); \
  1950. _ezchip_macro_read_value_ &= 0x3ffff;\
  1951. }
  1952. #define _ENABLE_CLOCK_clk_audio_src_ { \
  1953. uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_src_ctrl_REG_ADDR); \
  1954. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1955. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1956. MA_OUTW(clk_audio_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1957. }
  1958. #define _DISABLE_CLOCK_clk_audio_src_ { \
  1959. uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_src_ctrl_REG_ADDR); \
  1960. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1961. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1962. MA_OUTW(clk_audio_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1963. }
  1964. #define _GET_CLOCK_ENABLE_STATUS_clk_audio_src_(_ezchip_macro_read_value_) { \
  1965. _ezchip_macro_read_value_=MA_INW(clk_audio_src_ctrl_REG_ADDR) >> 31; \
  1966. _ezchip_macro_read_value_ &= 0x1;\
  1967. }
  1968. #define _ENABLE_CLOCK_clk_audio_12288_ { \
  1969. uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_12288_ctrl_REG_ADDR); \
  1970. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1971. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1972. MA_OUTW(clk_audio_12288_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1973. }
  1974. #define _DISABLE_CLOCK_clk_audio_12288_ { \
  1975. uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_12288_ctrl_REG_ADDR); \
  1976. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1977. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1978. MA_OUTW(clk_audio_12288_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1979. }
  1980. #define _GET_CLOCK_ENABLE_STATUS_clk_audio_12288_(_ezchip_macro_read_value_) { \
  1981. _ezchip_macro_read_value_=MA_INW(clk_audio_12288_ctrl_REG_ADDR) >> 31; \
  1982. _ezchip_macro_read_value_ &= 0x1;\
  1983. }
  1984. #define _ENABLE_CLOCK_clk_vin_src_ { \
  1985. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_src_ctrl_REG_ADDR); \
  1986. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1987. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1988. MA_OUTW(clk_vin_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1989. }
  1990. #define _DISABLE_CLOCK_clk_vin_src_ { \
  1991. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_src_ctrl_REG_ADDR); \
  1992. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1993. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1994. MA_OUTW(clk_vin_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1995. }
  1996. #define _GET_CLOCK_ENABLE_STATUS_clk_vin_src_(_ezchip_macro_read_value_) { \
  1997. _ezchip_macro_read_value_=MA_INW(clk_vin_src_ctrl_REG_ADDR) >> 31; \
  1998. _ezchip_macro_read_value_ &= 0x1;\
  1999. }
  2000. #define _DIVIDE_CLOCK_clk_vin_src_(div) { \
  2001. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_src_ctrl_REG_ADDR); \
  2002. _ezchip_macro_read_value_ &= ~(0x7); \
  2003. _ezchip_macro_read_value_ |= (div&0x7); \
  2004. MA_OUTW(clk_vin_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2005. }
  2006. #define _GET_CLOCK_DIVIDE_STATUS_clk_vin_src_(_ezchip_macro_read_value_) { \
  2007. _ezchip_macro_read_value_=MA_INW(clk_vin_src_ctrl_REG_ADDR); \
  2008. _ezchip_macro_read_value_ &= 0x7;\
  2009. }
  2010. #define _ENABLE_CLOCK_clk_isp0_bus_ {}
  2011. #define _DIVIDE_CLOCK_clk_isp0_bus_(div) { \
  2012. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp0_bus_ctrl_REG_ADDR); \
  2013. _ezchip_macro_read_value_ &= ~(0xF); \
  2014. _ezchip_macro_read_value_ |= (div&0xF); \
  2015. MA_OUTW(clk_isp0_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2016. }
  2017. #define _GET_CLOCK_DIVIDE_STATUS_clk_isp0_bus_(_ezchip_macro_read_value_) { \
  2018. _ezchip_macro_read_value_=MA_INW(clk_isp0_bus_ctrl_REG_ADDR); \
  2019. _ezchip_macro_read_value_ &= 0xf;\
  2020. }
  2021. #define _ENABLE_CLOCK_clk_isp0_axi_ { \
  2022. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp0_axi_ctrl_REG_ADDR); \
  2023. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2024. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2025. MA_OUTW(clk_isp0_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2026. }
  2027. #define _DISABLE_CLOCK_clk_isp0_axi_ { \
  2028. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp0_axi_ctrl_REG_ADDR); \
  2029. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2030. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2031. MA_OUTW(clk_isp0_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2032. }
  2033. #define _GET_CLOCK_ENABLE_STATUS_clk_isp0_axi_(_ezchip_macro_read_value_) { \
  2034. _ezchip_macro_read_value_=MA_INW(clk_isp0_axi_ctrl_REG_ADDR) >> 31; \
  2035. _ezchip_macro_read_value_ &= 0x1;\
  2036. }
  2037. #define _ENABLE_CLOCK_clk_isp0noc_axi_ { \
  2038. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp0noc_axi_ctrl_REG_ADDR); \
  2039. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2040. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2041. MA_OUTW(clk_isp0noc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2042. }
  2043. #define _DISABLE_CLOCK_clk_isp0noc_axi_ { \
  2044. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp0noc_axi_ctrl_REG_ADDR); \
  2045. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2046. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2047. MA_OUTW(clk_isp0noc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2048. }
  2049. #define _GET_CLOCK_ENABLE_STATUS_clk_isp0noc_axi_(_ezchip_macro_read_value_) { \
  2050. _ezchip_macro_read_value_=MA_INW(clk_isp0noc_axi_ctrl_REG_ADDR) >> 31; \
  2051. _ezchip_macro_read_value_ &= 0x1;\
  2052. }
  2053. #define _ENABLE_CLOCK_clk_ispslv_axi_ { \
  2054. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ispslv_axi_ctrl_REG_ADDR); \
  2055. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2056. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2057. MA_OUTW(clk_ispslv_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2058. }
  2059. #define _DISABLE_CLOCK_clk_ispslv_axi_ { \
  2060. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ispslv_axi_ctrl_REG_ADDR); \
  2061. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2062. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2063. MA_OUTW(clk_ispslv_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2064. }
  2065. #define _GET_CLOCK_ENABLE_STATUS_clk_ispslv_axi_(_ezchip_macro_read_value_) { \
  2066. _ezchip_macro_read_value_=MA_INW(clk_ispslv_axi_ctrl_REG_ADDR) >> 31; \
  2067. _ezchip_macro_read_value_ &= 0x1;\
  2068. }
  2069. #define _ENABLE_CLOCK_clk_isp1_bus_ {}
  2070. #define _DIVIDE_CLOCK_clk_isp1_bus_(div) { \
  2071. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp1_bus_ctrl_REG_ADDR); \
  2072. _ezchip_macro_read_value_ &= ~(0xF); \
  2073. _ezchip_macro_read_value_ |= (div&0xF); \
  2074. MA_OUTW(clk_isp1_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2075. }
  2076. #define _GET_CLOCK_DIVIDE_STATUS_clk_isp1_bus_(_ezchip_macro_read_value_) { \
  2077. _ezchip_macro_read_value_=MA_INW(clk_isp1_bus_ctrl_REG_ADDR); \
  2078. _ezchip_macro_read_value_ &= 0xf;\
  2079. }
  2080. #define _ENABLE_CLOCK_clk_isp1_axi_ { \
  2081. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp1_axi_ctrl_REG_ADDR); \
  2082. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2083. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2084. MA_OUTW(clk_isp1_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2085. }
  2086. #define _DISABLE_CLOCK_clk_isp1_axi_ { \
  2087. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp1_axi_ctrl_REG_ADDR); \
  2088. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2089. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2090. MA_OUTW(clk_isp1_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2091. }
  2092. #define _GET_CLOCK_ENABLE_STATUS_clk_isp1_axi_(_ezchip_macro_read_value_) { \
  2093. _ezchip_macro_read_value_=MA_INW(clk_isp1_axi_ctrl_REG_ADDR) >> 31; \
  2094. _ezchip_macro_read_value_ &= 0x1;\
  2095. }
  2096. #define _ENABLE_CLOCK_clk_isp1noc_axi_ { \
  2097. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp1noc_axi_ctrl_REG_ADDR); \
  2098. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2099. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2100. MA_OUTW(clk_isp1noc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2101. }
  2102. #define _DISABLE_CLOCK_clk_isp1noc_axi_ { \
  2103. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp1noc_axi_ctrl_REG_ADDR); \
  2104. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2105. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2106. MA_OUTW(clk_isp1noc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2107. }
  2108. #define _GET_CLOCK_ENABLE_STATUS_clk_isp1noc_axi_(_ezchip_macro_read_value_) { \
  2109. _ezchip_macro_read_value_=MA_INW(clk_isp1noc_axi_ctrl_REG_ADDR) >> 31; \
  2110. _ezchip_macro_read_value_ &= 0x1;\
  2111. }
  2112. #define _ENABLE_CLOCK_clk_vin_bus_ {}
  2113. #define _DIVIDE_CLOCK_clk_vin_bus_(div) { \
  2114. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_bus_ctrl_REG_ADDR); \
  2115. _ezchip_macro_read_value_ &= ~(0xF); \
  2116. _ezchip_macro_read_value_ |= (div&0xF); \
  2117. MA_OUTW(clk_vin_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2118. }
  2119. #define _GET_CLOCK_DIVIDE_STATUS_clk_vin_bus_(_ezchip_macro_read_value_) { \
  2120. _ezchip_macro_read_value_=MA_INW(clk_vin_bus_ctrl_REG_ADDR); \
  2121. _ezchip_macro_read_value_ &= 0xf;\
  2122. }
  2123. #define _ENABLE_CLOCK_clk_vin_axi_ { \
  2124. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_axi_ctrl_REG_ADDR); \
  2125. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2126. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2127. MA_OUTW(clk_vin_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2128. }
  2129. #define _DISABLE_CLOCK_clk_vin_axi_ { \
  2130. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_axi_ctrl_REG_ADDR); \
  2131. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2132. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2133. MA_OUTW(clk_vin_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2134. }
  2135. #define _GET_CLOCK_ENABLE_STATUS_clk_vin_axi_(_ezchip_macro_read_value_) { \
  2136. _ezchip_macro_read_value_=MA_INW(clk_vin_axi_ctrl_REG_ADDR) >> 31; \
  2137. _ezchip_macro_read_value_ &= 0x1;\
  2138. }
  2139. #define _ENABLE_CLOCK_clk_vinnoc_axi_ { \
  2140. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vinnoc_axi_ctrl_REG_ADDR); \
  2141. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2142. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2143. MA_OUTW(clk_vinnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2144. }
  2145. #define _DISABLE_CLOCK_clk_vinnoc_axi_ { \
  2146. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vinnoc_axi_ctrl_REG_ADDR); \
  2147. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2148. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2149. MA_OUTW(clk_vinnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2150. }
  2151. #define _GET_CLOCK_ENABLE_STATUS_clk_vinnoc_axi_(_ezchip_macro_read_value_) { \
  2152. _ezchip_macro_read_value_=MA_INW(clk_vinnoc_axi_ctrl_REG_ADDR) >> 31; \
  2153. _ezchip_macro_read_value_ &= 0x1;\
  2154. }
  2155. #define _ENABLE_CLOCK_clk_vout_src_ { \
  2156. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vout_src_ctrl_REG_ADDR); \
  2157. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2158. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2159. MA_OUTW(clk_vout_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2160. }
  2161. #define _DISABLE_CLOCK_clk_vout_src_ { \
  2162. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vout_src_ctrl_REG_ADDR); \
  2163. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2164. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2165. MA_OUTW(clk_vout_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2166. }
  2167. #define _GET_CLOCK_ENABLE_STATUS_clk_vout_src_(_ezchip_macro_read_value_) { \
  2168. _ezchip_macro_read_value_=MA_INW(clk_vout_src_ctrl_REG_ADDR) >> 31; \
  2169. _ezchip_macro_read_value_ &= 0x1;\
  2170. }
  2171. #define _DIVIDE_CLOCK_clk_vout_src_(div) { \
  2172. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vout_src_ctrl_REG_ADDR); \
  2173. _ezchip_macro_read_value_ &= ~(0x7); \
  2174. _ezchip_macro_read_value_ |= (div&0x7); \
  2175. MA_OUTW(clk_vout_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2176. }
  2177. #define _GET_CLOCK_DIVIDE_STATUS_clk_vout_src_(_ezchip_macro_read_value_) { \
  2178. _ezchip_macro_read_value_=MA_INW(clk_vout_src_ctrl_REG_ADDR); \
  2179. _ezchip_macro_read_value_ &= 0x7;\
  2180. }
  2181. #define _ENABLE_CLOCK_clk_dispbus_src_ {}
  2182. #define _DIVIDE_CLOCK_clk_dispbus_src_(div) { \
  2183. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dispbus_src_ctrl_REG_ADDR); \
  2184. _ezchip_macro_read_value_ &= ~(0x7); \
  2185. _ezchip_macro_read_value_ |= (div&0x7); \
  2186. MA_OUTW(clk_dispbus_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2187. }
  2188. #define _GET_CLOCK_DIVIDE_STATUS_clk_dispbus_src_(_ezchip_macro_read_value_) { \
  2189. _ezchip_macro_read_value_=MA_INW(clk_dispbus_src_ctrl_REG_ADDR); \
  2190. _ezchip_macro_read_value_ &= 0x7;\
  2191. }
  2192. #define _ENABLE_CLOCK_clk_disp_bus_ {}
  2193. #define _DIVIDE_CLOCK_clk_disp_bus_(div) { \
  2194. uint32_t _ezchip_macro_read_value_=MA_INW(clk_disp_bus_ctrl_REG_ADDR); \
  2195. _ezchip_macro_read_value_ &= ~(0x7); \
  2196. _ezchip_macro_read_value_ |= (div&0x7); \
  2197. MA_OUTW(clk_disp_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2198. }
  2199. #define _GET_CLOCK_DIVIDE_STATUS_clk_disp_bus_(_ezchip_macro_read_value_) { \
  2200. _ezchip_macro_read_value_=MA_INW(clk_disp_bus_ctrl_REG_ADDR); \
  2201. _ezchip_macro_read_value_ &= 0x7;\
  2202. }
  2203. #define _ENABLE_CLOCK_clk_disp_axi_ { \
  2204. uint32_t _ezchip_macro_read_value_=MA_INW(clk_disp_axi_ctrl_REG_ADDR); \
  2205. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2206. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2207. MA_OUTW(clk_disp_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2208. }
  2209. #define _DISABLE_CLOCK_clk_disp_axi_ { \
  2210. uint32_t _ezchip_macro_read_value_=MA_INW(clk_disp_axi_ctrl_REG_ADDR); \
  2211. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2212. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2213. MA_OUTW(clk_disp_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2214. }
  2215. #define _GET_CLOCK_ENABLE_STATUS_clk_disp_axi_(_ezchip_macro_read_value_) { \
  2216. _ezchip_macro_read_value_=MA_INW(clk_disp_axi_ctrl_REG_ADDR) >> 31; \
  2217. _ezchip_macro_read_value_ &= 0x1;\
  2218. }
  2219. #define _ENABLE_CLOCK_clk_dispnoc_axi_ { \
  2220. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dispnoc_axi_ctrl_REG_ADDR); \
  2221. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2222. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2223. MA_OUTW(clk_dispnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2224. }
  2225. #define _DISABLE_CLOCK_clk_dispnoc_axi_ { \
  2226. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dispnoc_axi_ctrl_REG_ADDR); \
  2227. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2228. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2229. MA_OUTW(clk_dispnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2230. }
  2231. #define _GET_CLOCK_ENABLE_STATUS_clk_dispnoc_axi_(_ezchip_macro_read_value_) { \
  2232. _ezchip_macro_read_value_=MA_INW(clk_dispnoc_axi_ctrl_REG_ADDR) >> 31; \
  2233. _ezchip_macro_read_value_ &= 0x1;\
  2234. }
  2235. #define _ENABLE_CLOCK_clk_sdio0_ahb_ { \
  2236. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio0_ahb_ctrl_REG_ADDR); \
  2237. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2238. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2239. MA_OUTW(clk_sdio0_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2240. }
  2241. #define _DISABLE_CLOCK_clk_sdio0_ahb_ { \
  2242. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio0_ahb_ctrl_REG_ADDR); \
  2243. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2244. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2245. MA_OUTW(clk_sdio0_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2246. }
  2247. #define _GET_CLOCK_ENABLE_STATUS_clk_sdio0_ahb_(_ezchip_macro_read_value_) { \
  2248. _ezchip_macro_read_value_=MA_INW(clk_sdio0_ahb_ctrl_REG_ADDR) >> 31; \
  2249. _ezchip_macro_read_value_ &= 0x1;\
  2250. }
  2251. #define _ENABLE_CLOCK_clk_sdio0_cclkint_ { \
  2252. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_ctrl_REG_ADDR); \
  2253. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2254. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2255. MA_OUTW(clk_sdio0_cclkint_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2256. }
  2257. #define _DISABLE_CLOCK_clk_sdio0_cclkint_ { \
  2258. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_ctrl_REG_ADDR); \
  2259. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2260. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2261. MA_OUTW(clk_sdio0_cclkint_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2262. }
  2263. #define _GET_CLOCK_ENABLE_STATUS_clk_sdio0_cclkint_(_ezchip_macro_read_value_) { \
  2264. _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_ctrl_REG_ADDR) >> 31; \
  2265. _ezchip_macro_read_value_ &= 0x1;\
  2266. }
  2267. #define _DIVIDE_CLOCK_clk_sdio0_cclkint_(div) { \
  2268. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_ctrl_REG_ADDR); \
  2269. _ezchip_macro_read_value_ &= ~(0x1F); \
  2270. _ezchip_macro_read_value_ |= (div&0x1F); \
  2271. MA_OUTW(clk_sdio0_cclkint_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2272. }
  2273. #define _GET_CLOCK_DIVIDE_STATUS_clk_sdio0_cclkint_(_ezchip_macro_read_value_) { \
  2274. _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_ctrl_REG_ADDR); \
  2275. _ezchip_macro_read_value_ &= 0x1f;\
  2276. }
  2277. #define _ENABLE_CLOCK_clk_sdio0_cclkint_inv_ {}
  2278. #define _SET_CLOCK_clk_sdio0_cclkint_inv_POLARITY_ { \
  2279. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_inv_ctrl_REG_ADDR); \
  2280. _ezchip_macro_read_value_ &= ~(0x1<<30); \
  2281. _ezchip_macro_read_value_ |= (0x1&0x1)<<30; \
  2282. MA_OUTW(clk_sdio0_cclkint_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2283. }
  2284. #define _UNSET_CLOCK_clk_sdio0_cclkint_inv_POLARITY_ { \
  2285. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_inv_ctrl_REG_ADDR); \
  2286. _ezchip_macro_read_value_ &= ~(0x1<<30); \
  2287. _ezchip_macro_read_value_ |= (0x0&0x1)<<30; \
  2288. MA_OUTW(clk_sdio0_cclkint_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2289. }
  2290. #define _GET_CLOCK_POLARITY_STATUS_clk_sdio0_cclkint_inv_(_ezchip_macro_read_value_) { \
  2291. _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_inv_ctrl_REG_ADDR) >> 30; \
  2292. _ezchip_macro_read_value_ &= 0x1;\
  2293. }
  2294. #define _ENABLE_CLOCK_clk_sdio1_ahb_ { \
  2295. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio1_ahb_ctrl_REG_ADDR); \
  2296. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2297. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2298. MA_OUTW(clk_sdio1_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2299. }
  2300. #define _DISABLE_CLOCK_clk_sdio1_ahb_ { \
  2301. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio1_ahb_ctrl_REG_ADDR); \
  2302. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2303. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2304. MA_OUTW(clk_sdio1_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2305. }
  2306. #define _GET_CLOCK_ENABLE_STATUS_clk_sdio1_ahb_(_ezchip_macro_read_value_) { \
  2307. _ezchip_macro_read_value_=MA_INW(clk_sdio1_ahb_ctrl_REG_ADDR) >> 31; \
  2308. _ezchip_macro_read_value_ &= 0x1;\
  2309. }
  2310. #define _ENABLE_CLOCK_clk_sdio1_cclkint_ { \
  2311. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_ctrl_REG_ADDR); \
  2312. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2313. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2314. MA_OUTW(clk_sdio1_cclkint_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2315. }
  2316. #define _DISABLE_CLOCK_clk_sdio1_cclkint_ { \
  2317. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_ctrl_REG_ADDR); \
  2318. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2319. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2320. MA_OUTW(clk_sdio1_cclkint_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2321. }
  2322. #define _GET_CLOCK_ENABLE_STATUS_clk_sdio1_cclkint_(_ezchip_macro_read_value_) { \
  2323. _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_ctrl_REG_ADDR) >> 31; \
  2324. _ezchip_macro_read_value_ &= 0x1;\
  2325. }
  2326. #define _DIVIDE_CLOCK_clk_sdio1_cclkint_(div) { \
  2327. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_ctrl_REG_ADDR); \
  2328. _ezchip_macro_read_value_ &= ~(0x1F); \
  2329. _ezchip_macro_read_value_ |= (div&0x1F); \
  2330. MA_OUTW(clk_sdio1_cclkint_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2331. }
  2332. #define _GET_CLOCK_DIVIDE_STATUS_clk_sdio1_cclkint_(_ezchip_macro_read_value_) { \
  2333. _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_ctrl_REG_ADDR); \
  2334. _ezchip_macro_read_value_ &= 0x1f;\
  2335. }
  2336. #define _ENABLE_CLOCK_clk_sdio1_cclkint_inv_ {}
  2337. #define _SET_CLOCK_clk_sdio1_cclkint_inv_POLARITY_ { \
  2338. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_inv_ctrl_REG_ADDR); \
  2339. _ezchip_macro_read_value_ &= ~(0x1<<30); \
  2340. _ezchip_macro_read_value_ |= (0x1&0x1)<<30; \
  2341. MA_OUTW(clk_sdio1_cclkint_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2342. }
  2343. #define _UNSET_CLOCK_clk_sdio1_cclkint_inv_POLARITY_ { \
  2344. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_inv_ctrl_REG_ADDR); \
  2345. _ezchip_macro_read_value_ &= ~(0x1<<30); \
  2346. _ezchip_macro_read_value_ |= (0x0&0x1)<<30; \
  2347. MA_OUTW(clk_sdio1_cclkint_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2348. }
  2349. #define _GET_CLOCK_POLARITY_STATUS_clk_sdio1_cclkint_inv_(_ezchip_macro_read_value_) { \
  2350. _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_inv_ctrl_REG_ADDR) >> 30; \
  2351. _ezchip_macro_read_value_ &= 0x1;\
  2352. }
  2353. #define _ENABLE_CLOCK_clk_gmac_ahb_ { \
  2354. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_ahb_ctrl_REG_ADDR); \
  2355. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2356. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2357. MA_OUTW(clk_gmac_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2358. }
  2359. #define _DISABLE_CLOCK_clk_gmac_ahb_ { \
  2360. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_ahb_ctrl_REG_ADDR); \
  2361. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2362. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2363. MA_OUTW(clk_gmac_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2364. }
  2365. #define _GET_CLOCK_ENABLE_STATUS_clk_gmac_ahb_(_ezchip_macro_read_value_) { \
  2366. _ezchip_macro_read_value_=MA_INW(clk_gmac_ahb_ctrl_REG_ADDR) >> 31; \
  2367. _ezchip_macro_read_value_ &= 0x1;\
  2368. }
  2369. #define _ENABLE_CLOCK_clk_gmac_root_div_ {}
  2370. #define _DIVIDE_CLOCK_clk_gmac_root_div_(div) { \
  2371. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_root_div_ctrl_REG_ADDR); \
  2372. _ezchip_macro_read_value_ &= ~(0xF); \
  2373. _ezchip_macro_read_value_ |= (div&0xF); \
  2374. MA_OUTW(clk_gmac_root_div_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2375. }
  2376. #define _GET_CLOCK_DIVIDE_STATUS_clk_gmac_root_div_(_ezchip_macro_read_value_) { \
  2377. _ezchip_macro_read_value_=MA_INW(clk_gmac_root_div_ctrl_REG_ADDR); \
  2378. _ezchip_macro_read_value_ &= 0xf;\
  2379. }
  2380. #define _ENABLE_CLOCK_clk_gmac_ptp_refclk_ { \
  2381. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_ptp_refclk_ctrl_REG_ADDR); \
  2382. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2383. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2384. MA_OUTW(clk_gmac_ptp_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2385. }
  2386. #define _DISABLE_CLOCK_clk_gmac_ptp_refclk_ { \
  2387. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_ptp_refclk_ctrl_REG_ADDR); \
  2388. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2389. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2390. MA_OUTW(clk_gmac_ptp_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2391. }
  2392. #define _GET_CLOCK_ENABLE_STATUS_clk_gmac_ptp_refclk_(_ezchip_macro_read_value_) { \
  2393. _ezchip_macro_read_value_=MA_INW(clk_gmac_ptp_refclk_ctrl_REG_ADDR) >> 31; \
  2394. _ezchip_macro_read_value_ &= 0x1;\
  2395. }
  2396. #define _DIVIDE_CLOCK_clk_gmac_ptp_refclk_(div) { \
  2397. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_ptp_refclk_ctrl_REG_ADDR); \
  2398. _ezchip_macro_read_value_ &= ~(0x1F); \
  2399. _ezchip_macro_read_value_ |= (div&0x1F); \
  2400. MA_OUTW(clk_gmac_ptp_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2401. }
  2402. #define _GET_CLOCK_DIVIDE_STATUS_clk_gmac_ptp_refclk_(_ezchip_macro_read_value_) { \
  2403. _ezchip_macro_read_value_=MA_INW(clk_gmac_ptp_refclk_ctrl_REG_ADDR); \
  2404. _ezchip_macro_read_value_ &= 0x1f;\
  2405. }
  2406. #define _ENABLE_CLOCK_clk_gmac_gtxclk_ { \
  2407. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_gtxclk_ctrl_REG_ADDR); \
  2408. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2409. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2410. MA_OUTW(clk_gmac_gtxclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2411. }
  2412. #define _DISABLE_CLOCK_clk_gmac_gtxclk_ { \
  2413. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_gtxclk_ctrl_REG_ADDR); \
  2414. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2415. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2416. MA_OUTW(clk_gmac_gtxclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2417. }
  2418. #define _GET_CLOCK_ENABLE_STATUS_clk_gmac_gtxclk_(_ezchip_macro_read_value_) { \
  2419. _ezchip_macro_read_value_=MA_INW(clk_gmac_gtxclk_ctrl_REG_ADDR) >> 31; \
  2420. _ezchip_macro_read_value_ &= 0x1;\
  2421. }
  2422. #define _DIVIDE_CLOCK_clk_gmac_gtxclk_(div) { \
  2423. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_gtxclk_ctrl_REG_ADDR); \
  2424. _ezchip_macro_read_value_ &= ~(0xFF); \
  2425. _ezchip_macro_read_value_ |= (div&0xFF); \
  2426. MA_OUTW(clk_gmac_gtxclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2427. }
  2428. #define _GET_CLOCK_DIVIDE_STATUS_clk_gmac_gtxclk_(_ezchip_macro_read_value_) { \
  2429. _ezchip_macro_read_value_=MA_INW(clk_gmac_gtxclk_ctrl_REG_ADDR); \
  2430. _ezchip_macro_read_value_ &= 0xff;\
  2431. }
  2432. #define _ENABLE_CLOCK_clk_gmac_rmii_txclk_ { \
  2433. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_txclk_ctrl_REG_ADDR); \
  2434. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2435. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2436. MA_OUTW(clk_gmac_rmii_txclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2437. }
  2438. #define _DISABLE_CLOCK_clk_gmac_rmii_txclk_ { \
  2439. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_txclk_ctrl_REG_ADDR); \
  2440. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2441. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2442. MA_OUTW(clk_gmac_rmii_txclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2443. }
  2444. #define _GET_CLOCK_ENABLE_STATUS_clk_gmac_rmii_txclk_(_ezchip_macro_read_value_) { \
  2445. _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_txclk_ctrl_REG_ADDR) >> 31; \
  2446. _ezchip_macro_read_value_ &= 0x1;\
  2447. }
  2448. #define _DIVIDE_CLOCK_clk_gmac_rmii_txclk_(div) { \
  2449. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_txclk_ctrl_REG_ADDR); \
  2450. _ezchip_macro_read_value_ &= ~(0xF); \
  2451. _ezchip_macro_read_value_ |= (div&0xF); \
  2452. MA_OUTW(clk_gmac_rmii_txclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2453. }
  2454. #define _GET_CLOCK_DIVIDE_STATUS_clk_gmac_rmii_txclk_(_ezchip_macro_read_value_) { \
  2455. _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_txclk_ctrl_REG_ADDR); \
  2456. _ezchip_macro_read_value_ &= 0xf;\
  2457. }
  2458. #define _ENABLE_CLOCK_clk_gmac_rmii_rxclk_ { \
  2459. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR); \
  2460. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2461. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2462. MA_OUTW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2463. }
  2464. #define _DISABLE_CLOCK_clk_gmac_rmii_rxclk_ { \
  2465. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR); \
  2466. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2467. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2468. MA_OUTW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2469. }
  2470. #define _GET_CLOCK_ENABLE_STATUS_clk_gmac_rmii_rxclk_(_ezchip_macro_read_value_) { \
  2471. _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR) >> 31; \
  2472. _ezchip_macro_read_value_ &= 0x1;\
  2473. }
  2474. #define _DIVIDE_CLOCK_clk_gmac_rmii_rxclk_(div) { \
  2475. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR); \
  2476. _ezchip_macro_read_value_ &= ~(0xF); \
  2477. _ezchip_macro_read_value_ |= (div&0xF); \
  2478. MA_OUTW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2479. }
  2480. #define _GET_CLOCK_DIVIDE_STATUS_clk_gmac_rmii_rxclk_(_ezchip_macro_read_value_) { \
  2481. _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR); \
  2482. _ezchip_macro_read_value_ &= 0xf;\
  2483. }
  2484. #define _ENABLE_CLOCK_clk_gmac_tx_ {}
  2485. #define _SWITCH_CLOCK_clk_gmac_tx_SOURCE_clk_gmac_gtxclk_ { \
  2486. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tx_ctrl_REG_ADDR); \
  2487. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  2488. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  2489. MA_OUTW(clk_gmac_tx_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2490. }
  2491. #define _SWITCH_CLOCK_clk_gmac_tx_SOURCE_clk_gmac_mii_txclk_ { \
  2492. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tx_ctrl_REG_ADDR); \
  2493. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  2494. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  2495. MA_OUTW(clk_gmac_tx_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2496. }
  2497. #define _SWITCH_CLOCK_clk_gmac_tx_SOURCE_clk_gmac_rmii_txclk_ { \
  2498. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tx_ctrl_REG_ADDR); \
  2499. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  2500. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  2501. MA_OUTW(clk_gmac_tx_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2502. }
  2503. #define _GET_CLOCK_SOURCE_STATUS_clk_gmac_tx_(_ezchip_macro_read_value_) { \
  2504. _ezchip_macro_read_value_=MA_INW(clk_gmac_tx_ctrl_REG_ADDR) >> 24; \
  2505. _ezchip_macro_read_value_ &= 0x3;\
  2506. }
  2507. #define _ENABLE_CLOCK_clk_gmac_tx_inv_ {}
  2508. #define _SET_CLOCK_clk_gmac_tx_inv_POLARITY_ { \
  2509. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tx_inv_ctrl_REG_ADDR); \
  2510. _ezchip_macro_read_value_ &= ~(0x1<<30); \
  2511. _ezchip_macro_read_value_ |= (0x1&0x1)<<30; \
  2512. MA_OUTW(clk_gmac_tx_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2513. }
  2514. #define _UNSET_CLOCK_clk_gmac_tx_inv_POLARITY_ { \
  2515. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tx_inv_ctrl_REG_ADDR); \
  2516. _ezchip_macro_read_value_ &= ~(0x1<<30); \
  2517. _ezchip_macro_read_value_ |= (0x0&0x1)<<30; \
  2518. MA_OUTW(clk_gmac_tx_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2519. }
  2520. #define _GET_CLOCK_POLARITY_STATUS_clk_gmac_tx_inv_(_ezchip_macro_read_value_) { \
  2521. _ezchip_macro_read_value_=MA_INW(clk_gmac_tx_inv_ctrl_REG_ADDR) >> 30; \
  2522. _ezchip_macro_read_value_ &= 0x1;\
  2523. }
  2524. #define _ENABLE_CLOCK_clk_gmac_rx_pre_ {}
  2525. #define _SWITCH_CLOCK_clk_gmac_rx_pre_SOURCE_clk_gmac_gr_mii_rxclk_ { \
  2526. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rx_pre_ctrl_REG_ADDR); \
  2527. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  2528. _ezchip_macro_read_value_ |= (0x0&0x1)<<24; \
  2529. MA_OUTW(clk_gmac_rx_pre_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2530. }
  2531. #define _SWITCH_CLOCK_clk_gmac_rx_pre_SOURCE_clk_gmac_rmii_rxclk_ { \
  2532. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rx_pre_ctrl_REG_ADDR); \
  2533. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  2534. _ezchip_macro_read_value_ |= (0x1&0x1)<<24; \
  2535. MA_OUTW(clk_gmac_rx_pre_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2536. }
  2537. #define _GET_CLOCK_SOURCE_STATUS_clk_gmac_rx_pre_(_ezchip_macro_read_value_) { \
  2538. _ezchip_macro_read_value_=MA_INW(clk_gmac_rx_pre_ctrl_REG_ADDR) >> 24; \
  2539. _ezchip_macro_read_value_ &= 0x1;\
  2540. }
  2541. #define _ENABLE_CLOCK_clk_gmac_rx_inv_ {}
  2542. #define _SET_CLOCK_clk_gmac_rx_inv_POLARITY_ { \
  2543. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rx_inv_ctrl_REG_ADDR); \
  2544. _ezchip_macro_read_value_ &= ~(0x1<<30); \
  2545. _ezchip_macro_read_value_ |= (0x1&0x1)<<30; \
  2546. MA_OUTW(clk_gmac_rx_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2547. }
  2548. #define _UNSET_CLOCK_clk_gmac_rx_inv_POLARITY_ { \
  2549. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rx_inv_ctrl_REG_ADDR); \
  2550. _ezchip_macro_read_value_ &= ~(0x1<<30); \
  2551. _ezchip_macro_read_value_ |= (0x0&0x1)<<30; \
  2552. MA_OUTW(clk_gmac_rx_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2553. }
  2554. #define _GET_CLOCK_POLARITY_STATUS_clk_gmac_rx_inv_(_ezchip_macro_read_value_) { \
  2555. _ezchip_macro_read_value_=MA_INW(clk_gmac_rx_inv_ctrl_REG_ADDR) >> 30; \
  2556. _ezchip_macro_read_value_ &= 0x1;\
  2557. }
  2558. #define _ENABLE_CLOCK_clk_gmac_rmii_ { \
  2559. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_ctrl_REG_ADDR); \
  2560. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2561. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2562. MA_OUTW(clk_gmac_rmii_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2563. }
  2564. #define _DISABLE_CLOCK_clk_gmac_rmii_ { \
  2565. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_ctrl_REG_ADDR); \
  2566. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2567. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2568. MA_OUTW(clk_gmac_rmii_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2569. }
  2570. #define _GET_CLOCK_ENABLE_STATUS_clk_gmac_rmii_(_ezchip_macro_read_value_) { \
  2571. _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_ctrl_REG_ADDR) >> 31; \
  2572. _ezchip_macro_read_value_ &= 0x1;\
  2573. }
  2574. #define _ENABLE_CLOCK_clk_gmac_tophyref_ { \
  2575. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tophyref_ctrl_REG_ADDR); \
  2576. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2577. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2578. MA_OUTW(clk_gmac_tophyref_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2579. }
  2580. #define _DISABLE_CLOCK_clk_gmac_tophyref_ { \
  2581. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tophyref_ctrl_REG_ADDR); \
  2582. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2583. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2584. MA_OUTW(clk_gmac_tophyref_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2585. }
  2586. #define _GET_CLOCK_ENABLE_STATUS_clk_gmac_tophyref_(_ezchip_macro_read_value_) { \
  2587. _ezchip_macro_read_value_=MA_INW(clk_gmac_tophyref_ctrl_REG_ADDR) >> 31; \
  2588. _ezchip_macro_read_value_ &= 0x1;\
  2589. }
  2590. #define _DIVIDE_CLOCK_clk_gmac_tophyref_(div) { \
  2591. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tophyref_ctrl_REG_ADDR); \
  2592. _ezchip_macro_read_value_ &= ~(0x7F); \
  2593. _ezchip_macro_read_value_ |= (div&0x7F); \
  2594. MA_OUTW(clk_gmac_tophyref_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2595. }
  2596. #define _GET_CLOCK_DIVIDE_STATUS_clk_gmac_tophyref_(_ezchip_macro_read_value_) { \
  2597. _ezchip_macro_read_value_=MA_INW(clk_gmac_tophyref_ctrl_REG_ADDR); \
  2598. _ezchip_macro_read_value_ &= 0x7f;\
  2599. }
  2600. #define _ENABLE_CLOCK_clk_spi2ahb_ahb_ { \
  2601. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_ahb_ctrl_REG_ADDR); \
  2602. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2603. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2604. MA_OUTW(clk_spi2ahb_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2605. }
  2606. #define _DISABLE_CLOCK_clk_spi2ahb_ahb_ { \
  2607. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_ahb_ctrl_REG_ADDR); \
  2608. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2609. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2610. MA_OUTW(clk_spi2ahb_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2611. }
  2612. #define _GET_CLOCK_ENABLE_STATUS_clk_spi2ahb_ahb_(_ezchip_macro_read_value_) { \
  2613. _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_ahb_ctrl_REG_ADDR) >> 31; \
  2614. _ezchip_macro_read_value_ &= 0x1;\
  2615. }
  2616. #define _ENABLE_CLOCK_clk_spi2ahb_core_ { \
  2617. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_core_ctrl_REG_ADDR); \
  2618. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2619. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2620. MA_OUTW(clk_spi2ahb_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2621. }
  2622. #define _DISABLE_CLOCK_clk_spi2ahb_core_ { \
  2623. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_core_ctrl_REG_ADDR); \
  2624. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2625. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2626. MA_OUTW(clk_spi2ahb_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2627. }
  2628. #define _GET_CLOCK_ENABLE_STATUS_clk_spi2ahb_core_(_ezchip_macro_read_value_) { \
  2629. _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_core_ctrl_REG_ADDR) >> 31; \
  2630. _ezchip_macro_read_value_ &= 0x1;\
  2631. }
  2632. #define _DIVIDE_CLOCK_clk_spi2ahb_core_(div) { \
  2633. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_core_ctrl_REG_ADDR); \
  2634. _ezchip_macro_read_value_ &= ~(0x1F); \
  2635. _ezchip_macro_read_value_ |= (div&0x1F); \
  2636. MA_OUTW(clk_spi2ahb_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2637. }
  2638. #define _GET_CLOCK_DIVIDE_STATUS_clk_spi2ahb_core_(_ezchip_macro_read_value_) { \
  2639. _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_core_ctrl_REG_ADDR); \
  2640. _ezchip_macro_read_value_ &= 0x1f;\
  2641. }
  2642. #define _ENABLE_CLOCK_clk_ezmaster_ahb_ { \
  2643. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ezmaster_ahb_ctrl_REG_ADDR); \
  2644. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2645. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2646. MA_OUTW(clk_ezmaster_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2647. }
  2648. #define _DISABLE_CLOCK_clk_ezmaster_ahb_ { \
  2649. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ezmaster_ahb_ctrl_REG_ADDR); \
  2650. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2651. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2652. MA_OUTW(clk_ezmaster_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2653. }
  2654. #define _GET_CLOCK_ENABLE_STATUS_clk_ezmaster_ahb_(_ezchip_macro_read_value_) { \
  2655. _ezchip_macro_read_value_=MA_INW(clk_ezmaster_ahb_ctrl_REG_ADDR) >> 31; \
  2656. _ezchip_macro_read_value_ &= 0x1;\
  2657. }
  2658. #define _ENABLE_CLOCK_clk_e24_ahb_ { \
  2659. uint32_t _ezchip_macro_read_value_=MA_INW(clk_e24_ahb_ctrl_REG_ADDR); \
  2660. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2661. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2662. MA_OUTW(clk_e24_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2663. }
  2664. #define _DISABLE_CLOCK_clk_e24_ahb_ { \
  2665. uint32_t _ezchip_macro_read_value_=MA_INW(clk_e24_ahb_ctrl_REG_ADDR); \
  2666. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2667. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2668. MA_OUTW(clk_e24_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2669. }
  2670. #define _GET_CLOCK_ENABLE_STATUS_clk_e24_ahb_(_ezchip_macro_read_value_) { \
  2671. _ezchip_macro_read_value_=MA_INW(clk_e24_ahb_ctrl_REG_ADDR) >> 31; \
  2672. _ezchip_macro_read_value_ &= 0x1;\
  2673. }
  2674. #define _ENABLE_CLOCK_clk_e24rtc_toggle_ { \
  2675. uint32_t _ezchip_macro_read_value_=MA_INW(clk_e24rtc_toggle_ctrl_REG_ADDR); \
  2676. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2677. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2678. MA_OUTW(clk_e24rtc_toggle_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2679. }
  2680. #define _DISABLE_CLOCK_clk_e24rtc_toggle_ { \
  2681. uint32_t _ezchip_macro_read_value_=MA_INW(clk_e24rtc_toggle_ctrl_REG_ADDR); \
  2682. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2683. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2684. MA_OUTW(clk_e24rtc_toggle_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2685. }
  2686. #define _GET_CLOCK_ENABLE_STATUS_clk_e24rtc_toggle_(_ezchip_macro_read_value_) { \
  2687. _ezchip_macro_read_value_=MA_INW(clk_e24rtc_toggle_ctrl_REG_ADDR) >> 31; \
  2688. _ezchip_macro_read_value_ &= 0x1;\
  2689. }
  2690. #define _ENABLE_CLOCK_clk_qspi_ahb_ { \
  2691. uint32_t _ezchip_macro_read_value_=MA_INW(clk_qspi_ahb_ctrl_REG_ADDR); \
  2692. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2693. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2694. MA_OUTW(clk_qspi_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2695. }
  2696. #define _DISABLE_CLOCK_clk_qspi_ahb_ { \
  2697. uint32_t _ezchip_macro_read_value_=MA_INW(clk_qspi_ahb_ctrl_REG_ADDR); \
  2698. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2699. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2700. MA_OUTW(clk_qspi_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2701. }
  2702. #define _GET_CLOCK_ENABLE_STATUS_clk_qspi_ahb_(_ezchip_macro_read_value_) { \
  2703. _ezchip_macro_read_value_=MA_INW(clk_qspi_ahb_ctrl_REG_ADDR) >> 31; \
  2704. _ezchip_macro_read_value_ &= 0x1;\
  2705. }
  2706. #define _ENABLE_CLOCK_clk_qspi_apb_ { \
  2707. uint32_t _ezchip_macro_read_value_=MA_INW(clk_qspi_apb_ctrl_REG_ADDR); \
  2708. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2709. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2710. MA_OUTW(clk_qspi_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2711. }
  2712. #define _DISABLE_CLOCK_clk_qspi_apb_ { \
  2713. uint32_t _ezchip_macro_read_value_=MA_INW(clk_qspi_apb_ctrl_REG_ADDR); \
  2714. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2715. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2716. MA_OUTW(clk_qspi_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2717. }
  2718. #define _GET_CLOCK_ENABLE_STATUS_clk_qspi_apb_(_ezchip_macro_read_value_) { \
  2719. _ezchip_macro_read_value_=MA_INW(clk_qspi_apb_ctrl_REG_ADDR) >> 31; \
  2720. _ezchip_macro_read_value_ &= 0x1;\
  2721. }
  2722. #define _ENABLE_CLOCK_clk_qspi_refclk_ { \
  2723. uint32_t _ezchip_macro_read_value_=MA_INW(clk_qspi_refclk_ctrl_REG_ADDR); \
  2724. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2725. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2726. MA_OUTW(clk_qspi_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2727. }
  2728. #define _DISABLE_CLOCK_clk_qspi_refclk_ { \
  2729. uint32_t _ezchip_macro_read_value_=MA_INW(clk_qspi_refclk_ctrl_REG_ADDR); \
  2730. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2731. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2732. MA_OUTW(clk_qspi_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2733. }
  2734. #define _GET_CLOCK_ENABLE_STATUS_clk_qspi_refclk_(_ezchip_macro_read_value_) { \
  2735. _ezchip_macro_read_value_=MA_INW(clk_qspi_refclk_ctrl_REG_ADDR) >> 31; \
  2736. _ezchip_macro_read_value_ &= 0x1;\
  2737. }
  2738. #define _DIVIDE_CLOCK_clk_qspi_refclk_(div) { \
  2739. uint32_t _ezchip_macro_read_value_=MA_INW(clk_qspi_refclk_ctrl_REG_ADDR); \
  2740. _ezchip_macro_read_value_ &= ~(0x1F); \
  2741. _ezchip_macro_read_value_ |= (div&0x1F); \
  2742. MA_OUTW(clk_qspi_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2743. }
  2744. #define _GET_CLOCK_DIVIDE_STATUS_clk_qspi_refclk_(_ezchip_macro_read_value_) { \
  2745. _ezchip_macro_read_value_=MA_INW(clk_qspi_refclk_ctrl_REG_ADDR); \
  2746. _ezchip_macro_read_value_ &= 0x1f;\
  2747. }
  2748. #define _ENABLE_CLOCK_clk_sec_ahb_ { \
  2749. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sec_ahb_ctrl_REG_ADDR); \
  2750. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2751. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2752. MA_OUTW(clk_sec_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2753. }
  2754. #define _DISABLE_CLOCK_clk_sec_ahb_ { \
  2755. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sec_ahb_ctrl_REG_ADDR); \
  2756. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2757. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2758. MA_OUTW(clk_sec_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2759. }
  2760. #define _GET_CLOCK_ENABLE_STATUS_clk_sec_ahb_(_ezchip_macro_read_value_) { \
  2761. _ezchip_macro_read_value_=MA_INW(clk_sec_ahb_ctrl_REG_ADDR) >> 31; \
  2762. _ezchip_macro_read_value_ &= 0x1;\
  2763. }
  2764. #define _ENABLE_CLOCK_clk_aes_clk_ { \
  2765. uint32_t _ezchip_macro_read_value_=MA_INW(clk_aes_clk_ctrl_REG_ADDR); \
  2766. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2767. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2768. MA_OUTW(clk_aes_clk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2769. }
  2770. #define _DISABLE_CLOCK_clk_aes_clk_ { \
  2771. uint32_t _ezchip_macro_read_value_=MA_INW(clk_aes_clk_ctrl_REG_ADDR); \
  2772. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2773. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2774. MA_OUTW(clk_aes_clk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2775. }
  2776. #define _GET_CLOCK_ENABLE_STATUS_clk_aes_clk_(_ezchip_macro_read_value_) { \
  2777. _ezchip_macro_read_value_=MA_INW(clk_aes_clk_ctrl_REG_ADDR) >> 31; \
  2778. _ezchip_macro_read_value_ &= 0x1;\
  2779. }
  2780. #define _ENABLE_CLOCK_clk_sha_clk_ { \
  2781. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sha_clk_ctrl_REG_ADDR); \
  2782. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2783. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2784. MA_OUTW(clk_sha_clk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2785. }
  2786. #define _DISABLE_CLOCK_clk_sha_clk_ { \
  2787. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sha_clk_ctrl_REG_ADDR); \
  2788. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2789. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2790. MA_OUTW(clk_sha_clk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2791. }
  2792. #define _GET_CLOCK_ENABLE_STATUS_clk_sha_clk_(_ezchip_macro_read_value_) { \
  2793. _ezchip_macro_read_value_=MA_INW(clk_sha_clk_ctrl_REG_ADDR) >> 31; \
  2794. _ezchip_macro_read_value_ &= 0x1;\
  2795. }
  2796. #define _ENABLE_CLOCK_clk_pka_clk_ { \
  2797. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pka_clk_ctrl_REG_ADDR); \
  2798. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2799. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2800. MA_OUTW(clk_pka_clk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2801. }
  2802. #define _DISABLE_CLOCK_clk_pka_clk_ { \
  2803. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pka_clk_ctrl_REG_ADDR); \
  2804. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2805. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2806. MA_OUTW(clk_pka_clk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2807. }
  2808. #define _GET_CLOCK_ENABLE_STATUS_clk_pka_clk_(_ezchip_macro_read_value_) { \
  2809. _ezchip_macro_read_value_=MA_INW(clk_pka_clk_ctrl_REG_ADDR) >> 31; \
  2810. _ezchip_macro_read_value_ &= 0x1;\
  2811. }
  2812. #define _ENABLE_CLOCK_clk_trng_apb_ { \
  2813. uint32_t _ezchip_macro_read_value_=MA_INW(clk_trng_apb_ctrl_REG_ADDR); \
  2814. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2815. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2816. MA_OUTW(clk_trng_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2817. }
  2818. #define _DISABLE_CLOCK_clk_trng_apb_ { \
  2819. uint32_t _ezchip_macro_read_value_=MA_INW(clk_trng_apb_ctrl_REG_ADDR); \
  2820. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2821. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2822. MA_OUTW(clk_trng_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2823. }
  2824. #define _GET_CLOCK_ENABLE_STATUS_clk_trng_apb_(_ezchip_macro_read_value_) { \
  2825. _ezchip_macro_read_value_=MA_INW(clk_trng_apb_ctrl_REG_ADDR) >> 31; \
  2826. _ezchip_macro_read_value_ &= 0x1;\
  2827. }
  2828. #define _ENABLE_CLOCK_clk_otp_apb_ { \
  2829. uint32_t _ezchip_macro_read_value_=MA_INW(clk_otp_apb_ctrl_REG_ADDR); \
  2830. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2831. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2832. MA_OUTW(clk_otp_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2833. }
  2834. #define _DISABLE_CLOCK_clk_otp_apb_ { \
  2835. uint32_t _ezchip_macro_read_value_=MA_INW(clk_otp_apb_ctrl_REG_ADDR); \
  2836. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2837. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2838. MA_OUTW(clk_otp_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2839. }
  2840. #define _GET_CLOCK_ENABLE_STATUS_clk_otp_apb_(_ezchip_macro_read_value_) { \
  2841. _ezchip_macro_read_value_=MA_INW(clk_otp_apb_ctrl_REG_ADDR) >> 31; \
  2842. _ezchip_macro_read_value_ &= 0x1;\
  2843. }
  2844. #define _ENABLE_CLOCK_clk_uart0_apb_ { \
  2845. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart0_apb_ctrl_REG_ADDR); \
  2846. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2847. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2848. MA_OUTW(clk_uart0_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2849. }
  2850. #define _DISABLE_CLOCK_clk_uart0_apb_ { \
  2851. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart0_apb_ctrl_REG_ADDR); \
  2852. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2853. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2854. MA_OUTW(clk_uart0_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2855. }
  2856. #define _GET_CLOCK_ENABLE_STATUS_clk_uart0_apb_(_ezchip_macro_read_value_) { \
  2857. _ezchip_macro_read_value_=MA_INW(clk_uart0_apb_ctrl_REG_ADDR) >> 31; \
  2858. _ezchip_macro_read_value_ &= 0x1;\
  2859. }
  2860. #define _ENABLE_CLOCK_clk_uart0_core_ { \
  2861. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart0_core_ctrl_REG_ADDR); \
  2862. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2863. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2864. MA_OUTW(clk_uart0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2865. }
  2866. #define _DISABLE_CLOCK_clk_uart0_core_ { \
  2867. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart0_core_ctrl_REG_ADDR); \
  2868. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2869. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2870. MA_OUTW(clk_uart0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2871. }
  2872. #define _GET_CLOCK_ENABLE_STATUS_clk_uart0_core_(_ezchip_macro_read_value_) { \
  2873. _ezchip_macro_read_value_=MA_INW(clk_uart0_core_ctrl_REG_ADDR) >> 31; \
  2874. _ezchip_macro_read_value_ &= 0x1;\
  2875. }
  2876. #define _DIVIDE_CLOCK_clk_uart0_core_(div) { \
  2877. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart0_core_ctrl_REG_ADDR); \
  2878. _ezchip_macro_read_value_ &= ~(0x3F); \
  2879. _ezchip_macro_read_value_ |= (div&0x3F); \
  2880. MA_OUTW(clk_uart0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2881. }
  2882. #define _GET_CLOCK_DIVIDE_STATUS_clk_uart0_core_(_ezchip_macro_read_value_) { \
  2883. _ezchip_macro_read_value_=MA_INW(clk_uart0_core_ctrl_REG_ADDR); \
  2884. _ezchip_macro_read_value_ &= 0x3f;\
  2885. }
  2886. #define _ENABLE_CLOCK_clk_uart1_apb_ { \
  2887. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart1_apb_ctrl_REG_ADDR); \
  2888. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2889. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2890. MA_OUTW(clk_uart1_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2891. }
  2892. #define _DISABLE_CLOCK_clk_uart1_apb_ { \
  2893. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart1_apb_ctrl_REG_ADDR); \
  2894. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2895. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2896. MA_OUTW(clk_uart1_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2897. }
  2898. #define _GET_CLOCK_ENABLE_STATUS_clk_uart1_apb_(_ezchip_macro_read_value_) { \
  2899. _ezchip_macro_read_value_=MA_INW(clk_uart1_apb_ctrl_REG_ADDR) >> 31; \
  2900. _ezchip_macro_read_value_ &= 0x1;\
  2901. }
  2902. #define _ENABLE_CLOCK_clk_uart1_core_ { \
  2903. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart1_core_ctrl_REG_ADDR); \
  2904. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2905. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2906. MA_OUTW(clk_uart1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2907. }
  2908. #define _DISABLE_CLOCK_clk_uart1_core_ { \
  2909. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart1_core_ctrl_REG_ADDR); \
  2910. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2911. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2912. MA_OUTW(clk_uart1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2913. }
  2914. #define _GET_CLOCK_ENABLE_STATUS_clk_uart1_core_(_ezchip_macro_read_value_) { \
  2915. _ezchip_macro_read_value_=MA_INW(clk_uart1_core_ctrl_REG_ADDR) >> 31; \
  2916. _ezchip_macro_read_value_ &= 0x1;\
  2917. }
  2918. #define _DIVIDE_CLOCK_clk_uart1_core_(div) { \
  2919. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart1_core_ctrl_REG_ADDR); \
  2920. _ezchip_macro_read_value_ &= ~(0x3F); \
  2921. _ezchip_macro_read_value_ |= (div&0x3F); \
  2922. MA_OUTW(clk_uart1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2923. }
  2924. #define _GET_CLOCK_DIVIDE_STATUS_clk_uart1_core_(_ezchip_macro_read_value_) { \
  2925. _ezchip_macro_read_value_=MA_INW(clk_uart1_core_ctrl_REG_ADDR); \
  2926. _ezchip_macro_read_value_ &= 0x3f;\
  2927. }
  2928. #define _ENABLE_CLOCK_clk_spi0_apb_ { \
  2929. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi0_apb_ctrl_REG_ADDR); \
  2930. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2931. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2932. MA_OUTW(clk_spi0_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2933. }
  2934. #define _DISABLE_CLOCK_clk_spi0_apb_ { \
  2935. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi0_apb_ctrl_REG_ADDR); \
  2936. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2937. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2938. MA_OUTW(clk_spi0_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2939. }
  2940. #define _GET_CLOCK_ENABLE_STATUS_clk_spi0_apb_(_ezchip_macro_read_value_) { \
  2941. _ezchip_macro_read_value_=MA_INW(clk_spi0_apb_ctrl_REG_ADDR) >> 31; \
  2942. _ezchip_macro_read_value_ &= 0x1;\
  2943. }
  2944. #define _ENABLE_CLOCK_clk_spi0_core_ { \
  2945. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi0_core_ctrl_REG_ADDR); \
  2946. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2947. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2948. MA_OUTW(clk_spi0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2949. }
  2950. #define _DISABLE_CLOCK_clk_spi0_core_ { \
  2951. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi0_core_ctrl_REG_ADDR); \
  2952. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2953. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2954. MA_OUTW(clk_spi0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2955. }
  2956. #define _GET_CLOCK_ENABLE_STATUS_clk_spi0_core_(_ezchip_macro_read_value_) { \
  2957. _ezchip_macro_read_value_=MA_INW(clk_spi0_core_ctrl_REG_ADDR) >> 31; \
  2958. _ezchip_macro_read_value_ &= 0x1;\
  2959. }
  2960. #define _DIVIDE_CLOCK_clk_spi0_core_(div) { \
  2961. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi0_core_ctrl_REG_ADDR); \
  2962. _ezchip_macro_read_value_ &= ~(0x3F); \
  2963. _ezchip_macro_read_value_ |= (div&0x3F); \
  2964. MA_OUTW(clk_spi0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2965. }
  2966. #define _GET_CLOCK_DIVIDE_STATUS_clk_spi0_core_(_ezchip_macro_read_value_) { \
  2967. _ezchip_macro_read_value_=MA_INW(clk_spi0_core_ctrl_REG_ADDR); \
  2968. _ezchip_macro_read_value_ &= 0x3f;\
  2969. }
  2970. #define _ENABLE_CLOCK_clk_spi1_apb_ { \
  2971. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi1_apb_ctrl_REG_ADDR); \
  2972. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2973. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2974. MA_OUTW(clk_spi1_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2975. }
  2976. #define _DISABLE_CLOCK_clk_spi1_apb_ { \
  2977. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi1_apb_ctrl_REG_ADDR); \
  2978. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2979. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2980. MA_OUTW(clk_spi1_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2981. }
  2982. #define _GET_CLOCK_ENABLE_STATUS_clk_spi1_apb_(_ezchip_macro_read_value_) { \
  2983. _ezchip_macro_read_value_=MA_INW(clk_spi1_apb_ctrl_REG_ADDR) >> 31; \
  2984. _ezchip_macro_read_value_ &= 0x1;\
  2985. }
  2986. #define _ENABLE_CLOCK_clk_spi1_core_ { \
  2987. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi1_core_ctrl_REG_ADDR); \
  2988. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2989. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2990. MA_OUTW(clk_spi1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2991. }
  2992. #define _DISABLE_CLOCK_clk_spi1_core_ { \
  2993. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi1_core_ctrl_REG_ADDR); \
  2994. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2995. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2996. MA_OUTW(clk_spi1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2997. }
  2998. #define _GET_CLOCK_ENABLE_STATUS_clk_spi1_core_(_ezchip_macro_read_value_) { \
  2999. _ezchip_macro_read_value_=MA_INW(clk_spi1_core_ctrl_REG_ADDR) >> 31; \
  3000. _ezchip_macro_read_value_ &= 0x1;\
  3001. }
  3002. #define _DIVIDE_CLOCK_clk_spi1_core_(div) { \
  3003. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi1_core_ctrl_REG_ADDR); \
  3004. _ezchip_macro_read_value_ &= ~(0x3F); \
  3005. _ezchip_macro_read_value_ |= (div&0x3F); \
  3006. MA_OUTW(clk_spi1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3007. }
  3008. #define _GET_CLOCK_DIVIDE_STATUS_clk_spi1_core_(_ezchip_macro_read_value_) { \
  3009. _ezchip_macro_read_value_=MA_INW(clk_spi1_core_ctrl_REG_ADDR); \
  3010. _ezchip_macro_read_value_ &= 0x3f;\
  3011. }
  3012. #define _ENABLE_CLOCK_clk_i2c0_apb_ { \
  3013. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c0_apb_ctrl_REG_ADDR); \
  3014. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3015. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3016. MA_OUTW(clk_i2c0_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3017. }
  3018. #define _DISABLE_CLOCK_clk_i2c0_apb_ { \
  3019. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c0_apb_ctrl_REG_ADDR); \
  3020. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3021. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3022. MA_OUTW(clk_i2c0_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3023. }
  3024. #define _GET_CLOCK_ENABLE_STATUS_clk_i2c0_apb_(_ezchip_macro_read_value_) { \
  3025. _ezchip_macro_read_value_=MA_INW(clk_i2c0_apb_ctrl_REG_ADDR) >> 31; \
  3026. _ezchip_macro_read_value_ &= 0x1;\
  3027. }
  3028. #define _ENABLE_CLOCK_clk_i2c0_core_ { \
  3029. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c0_core_ctrl_REG_ADDR); \
  3030. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3031. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3032. MA_OUTW(clk_i2c0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3033. }
  3034. #define _DISABLE_CLOCK_clk_i2c0_core_ { \
  3035. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c0_core_ctrl_REG_ADDR); \
  3036. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3037. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3038. MA_OUTW(clk_i2c0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3039. }
  3040. #define _GET_CLOCK_ENABLE_STATUS_clk_i2c0_core_(_ezchip_macro_read_value_) { \
  3041. _ezchip_macro_read_value_=MA_INW(clk_i2c0_core_ctrl_REG_ADDR) >> 31; \
  3042. _ezchip_macro_read_value_ &= 0x1;\
  3043. }
  3044. #define _DIVIDE_CLOCK_clk_i2c0_core_(div) { \
  3045. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c0_core_ctrl_REG_ADDR); \
  3046. _ezchip_macro_read_value_ &= ~(0x3F); \
  3047. _ezchip_macro_read_value_ |= (div&0x3F); \
  3048. MA_OUTW(clk_i2c0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3049. }
  3050. #define _GET_CLOCK_DIVIDE_STATUS_clk_i2c0_core_(_ezchip_macro_read_value_) { \
  3051. _ezchip_macro_read_value_=MA_INW(clk_i2c0_core_ctrl_REG_ADDR); \
  3052. _ezchip_macro_read_value_ &= 0x3f;\
  3053. }
  3054. #define _ENABLE_CLOCK_clk_i2c1_apb_ { \
  3055. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c1_apb_ctrl_REG_ADDR); \
  3056. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3057. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3058. MA_OUTW(clk_i2c1_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3059. }
  3060. #define _DISABLE_CLOCK_clk_i2c1_apb_ { \
  3061. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c1_apb_ctrl_REG_ADDR); \
  3062. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3063. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3064. MA_OUTW(clk_i2c1_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3065. }
  3066. #define _GET_CLOCK_ENABLE_STATUS_clk_i2c1_apb_(_ezchip_macro_read_value_) { \
  3067. _ezchip_macro_read_value_=MA_INW(clk_i2c1_apb_ctrl_REG_ADDR) >> 31; \
  3068. _ezchip_macro_read_value_ &= 0x1;\
  3069. }
  3070. #define _ENABLE_CLOCK_clk_i2c1_core_ { \
  3071. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c1_core_ctrl_REG_ADDR); \
  3072. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3073. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3074. MA_OUTW(clk_i2c1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3075. }
  3076. #define _DISABLE_CLOCK_clk_i2c1_core_ { \
  3077. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c1_core_ctrl_REG_ADDR); \
  3078. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3079. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3080. MA_OUTW(clk_i2c1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3081. }
  3082. #define _GET_CLOCK_ENABLE_STATUS_clk_i2c1_core_(_ezchip_macro_read_value_) { \
  3083. _ezchip_macro_read_value_=MA_INW(clk_i2c1_core_ctrl_REG_ADDR) >> 31; \
  3084. _ezchip_macro_read_value_ &= 0x1;\
  3085. }
  3086. #define _DIVIDE_CLOCK_clk_i2c1_core_(div) { \
  3087. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c1_core_ctrl_REG_ADDR); \
  3088. _ezchip_macro_read_value_ &= ~(0x3F); \
  3089. _ezchip_macro_read_value_ |= (div&0x3F); \
  3090. MA_OUTW(clk_i2c1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3091. }
  3092. #define _GET_CLOCK_DIVIDE_STATUS_clk_i2c1_core_(_ezchip_macro_read_value_) { \
  3093. _ezchip_macro_read_value_=MA_INW(clk_i2c1_core_ctrl_REG_ADDR); \
  3094. _ezchip_macro_read_value_ &= 0x3f;\
  3095. }
  3096. #define _ENABLE_CLOCK_clk_gpio_apb_ { \
  3097. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gpio_apb_ctrl_REG_ADDR); \
  3098. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3099. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3100. MA_OUTW(clk_gpio_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3101. }
  3102. #define _DISABLE_CLOCK_clk_gpio_apb_ { \
  3103. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gpio_apb_ctrl_REG_ADDR); \
  3104. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3105. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3106. MA_OUTW(clk_gpio_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3107. }
  3108. #define _GET_CLOCK_ENABLE_STATUS_clk_gpio_apb_(_ezchip_macro_read_value_) { \
  3109. _ezchip_macro_read_value_=MA_INW(clk_gpio_apb_ctrl_REG_ADDR) >> 31; \
  3110. _ezchip_macro_read_value_ &= 0x1;\
  3111. }
  3112. #define _ENABLE_CLOCK_clk_uart2_apb_ { \
  3113. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart2_apb_ctrl_REG_ADDR); \
  3114. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3115. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3116. MA_OUTW(clk_uart2_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3117. }
  3118. #define _DISABLE_CLOCK_clk_uart2_apb_ { \
  3119. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart2_apb_ctrl_REG_ADDR); \
  3120. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3121. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3122. MA_OUTW(clk_uart2_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3123. }
  3124. #define _GET_CLOCK_ENABLE_STATUS_clk_uart2_apb_(_ezchip_macro_read_value_) { \
  3125. _ezchip_macro_read_value_=MA_INW(clk_uart2_apb_ctrl_REG_ADDR) >> 31; \
  3126. _ezchip_macro_read_value_ &= 0x1;\
  3127. }
  3128. #define _ENABLE_CLOCK_clk_uart2_core_ { \
  3129. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart2_core_ctrl_REG_ADDR); \
  3130. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3131. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3132. MA_OUTW(clk_uart2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3133. }
  3134. #define _DISABLE_CLOCK_clk_uart2_core_ { \
  3135. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart2_core_ctrl_REG_ADDR); \
  3136. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3137. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3138. MA_OUTW(clk_uart2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3139. }
  3140. #define _GET_CLOCK_ENABLE_STATUS_clk_uart2_core_(_ezchip_macro_read_value_) { \
  3141. _ezchip_macro_read_value_=MA_INW(clk_uart2_core_ctrl_REG_ADDR) >> 31; \
  3142. _ezchip_macro_read_value_ &= 0x1;\
  3143. }
  3144. #define _DIVIDE_CLOCK_clk_uart2_core_(div) { \
  3145. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart2_core_ctrl_REG_ADDR); \
  3146. _ezchip_macro_read_value_ &= ~(0x3F); \
  3147. _ezchip_macro_read_value_ |= (div&0x3F); \
  3148. MA_OUTW(clk_uart2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3149. }
  3150. #define _GET_CLOCK_DIVIDE_STATUS_clk_uart2_core_(_ezchip_macro_read_value_) { \
  3151. _ezchip_macro_read_value_=MA_INW(clk_uart2_core_ctrl_REG_ADDR); \
  3152. _ezchip_macro_read_value_ &= 0x3f;\
  3153. }
  3154. #define _ENABLE_CLOCK_clk_uart3_apb_ { \
  3155. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart3_apb_ctrl_REG_ADDR); \
  3156. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3157. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3158. MA_OUTW(clk_uart3_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3159. }
  3160. #define _DISABLE_CLOCK_clk_uart3_apb_ { \
  3161. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart3_apb_ctrl_REG_ADDR); \
  3162. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3163. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3164. MA_OUTW(clk_uart3_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3165. }
  3166. #define _GET_CLOCK_ENABLE_STATUS_clk_uart3_apb_(_ezchip_macro_read_value_) { \
  3167. _ezchip_macro_read_value_=MA_INW(clk_uart3_apb_ctrl_REG_ADDR) >> 31; \
  3168. _ezchip_macro_read_value_ &= 0x1;\
  3169. }
  3170. #define _ENABLE_CLOCK_clk_uart3_core_ { \
  3171. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart3_core_ctrl_REG_ADDR); \
  3172. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3173. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3174. MA_OUTW(clk_uart3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3175. }
  3176. #define _DISABLE_CLOCK_clk_uart3_core_ { \
  3177. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart3_core_ctrl_REG_ADDR); \
  3178. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3179. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3180. MA_OUTW(clk_uart3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3181. }
  3182. #define _GET_CLOCK_ENABLE_STATUS_clk_uart3_core_(_ezchip_macro_read_value_) { \
  3183. _ezchip_macro_read_value_=MA_INW(clk_uart3_core_ctrl_REG_ADDR) >> 31; \
  3184. _ezchip_macro_read_value_ &= 0x1;\
  3185. }
  3186. #define _DIVIDE_CLOCK_clk_uart3_core_(div) { \
  3187. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart3_core_ctrl_REG_ADDR); \
  3188. _ezchip_macro_read_value_ &= ~(0x3F); \
  3189. _ezchip_macro_read_value_ |= (div&0x3F); \
  3190. MA_OUTW(clk_uart3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3191. }
  3192. #define _GET_CLOCK_DIVIDE_STATUS_clk_uart3_core_(_ezchip_macro_read_value_) { \
  3193. _ezchip_macro_read_value_=MA_INW(clk_uart3_core_ctrl_REG_ADDR); \
  3194. _ezchip_macro_read_value_ &= 0x3f;\
  3195. }
  3196. #define _ENABLE_CLOCK_clk_spi2_apb_ { \
  3197. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2_apb_ctrl_REG_ADDR); \
  3198. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3199. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3200. MA_OUTW(clk_spi2_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3201. }
  3202. #define _DISABLE_CLOCK_clk_spi2_apb_ { \
  3203. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2_apb_ctrl_REG_ADDR); \
  3204. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3205. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3206. MA_OUTW(clk_spi2_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3207. }
  3208. #define _GET_CLOCK_ENABLE_STATUS_clk_spi2_apb_(_ezchip_macro_read_value_) { \
  3209. _ezchip_macro_read_value_=MA_INW(clk_spi2_apb_ctrl_REG_ADDR) >> 31; \
  3210. _ezchip_macro_read_value_ &= 0x1;\
  3211. }
  3212. #define _ENABLE_CLOCK_clk_spi2_core_ { \
  3213. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2_core_ctrl_REG_ADDR); \
  3214. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3215. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3216. MA_OUTW(clk_spi2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3217. }
  3218. #define _DISABLE_CLOCK_clk_spi2_core_ { \
  3219. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2_core_ctrl_REG_ADDR); \
  3220. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3221. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3222. MA_OUTW(clk_spi2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3223. }
  3224. #define _GET_CLOCK_ENABLE_STATUS_clk_spi2_core_(_ezchip_macro_read_value_) { \
  3225. _ezchip_macro_read_value_=MA_INW(clk_spi2_core_ctrl_REG_ADDR) >> 31; \
  3226. _ezchip_macro_read_value_ &= 0x1;\
  3227. }
  3228. #define _DIVIDE_CLOCK_clk_spi2_core_(div) { \
  3229. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2_core_ctrl_REG_ADDR); \
  3230. _ezchip_macro_read_value_ &= ~(0x3F); \
  3231. _ezchip_macro_read_value_ |= (div&0x3F); \
  3232. MA_OUTW(clk_spi2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3233. }
  3234. #define _GET_CLOCK_DIVIDE_STATUS_clk_spi2_core_(_ezchip_macro_read_value_) { \
  3235. _ezchip_macro_read_value_=MA_INW(clk_spi2_core_ctrl_REG_ADDR); \
  3236. _ezchip_macro_read_value_ &= 0x3f;\
  3237. }
  3238. #define _ENABLE_CLOCK_clk_spi3_apb_ { \
  3239. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi3_apb_ctrl_REG_ADDR); \
  3240. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3241. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3242. MA_OUTW(clk_spi3_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3243. }
  3244. #define _DISABLE_CLOCK_clk_spi3_apb_ { \
  3245. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi3_apb_ctrl_REG_ADDR); \
  3246. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3247. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3248. MA_OUTW(clk_spi3_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3249. }
  3250. #define _GET_CLOCK_ENABLE_STATUS_clk_spi3_apb_(_ezchip_macro_read_value_) { \
  3251. _ezchip_macro_read_value_=MA_INW(clk_spi3_apb_ctrl_REG_ADDR) >> 31; \
  3252. _ezchip_macro_read_value_ &= 0x1;\
  3253. }
  3254. #define _ENABLE_CLOCK_clk_spi3_core_ { \
  3255. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi3_core_ctrl_REG_ADDR); \
  3256. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3257. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3258. MA_OUTW(clk_spi3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3259. }
  3260. #define _DISABLE_CLOCK_clk_spi3_core_ { \
  3261. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi3_core_ctrl_REG_ADDR); \
  3262. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3263. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3264. MA_OUTW(clk_spi3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3265. }
  3266. #define _GET_CLOCK_ENABLE_STATUS_clk_spi3_core_(_ezchip_macro_read_value_) { \
  3267. _ezchip_macro_read_value_=MA_INW(clk_spi3_core_ctrl_REG_ADDR) >> 31; \
  3268. _ezchip_macro_read_value_ &= 0x1;\
  3269. }
  3270. #define _DIVIDE_CLOCK_clk_spi3_core_(div) { \
  3271. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi3_core_ctrl_REG_ADDR); \
  3272. _ezchip_macro_read_value_ &= ~(0x3F); \
  3273. _ezchip_macro_read_value_ |= (div&0x3F); \
  3274. MA_OUTW(clk_spi3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3275. }
  3276. #define _GET_CLOCK_DIVIDE_STATUS_clk_spi3_core_(_ezchip_macro_read_value_) { \
  3277. _ezchip_macro_read_value_=MA_INW(clk_spi3_core_ctrl_REG_ADDR); \
  3278. _ezchip_macro_read_value_ &= 0x3f;\
  3279. }
  3280. #define _ENABLE_CLOCK_clk_i2c2_apb_ { \
  3281. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c2_apb_ctrl_REG_ADDR); \
  3282. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3283. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3284. MA_OUTW(clk_i2c2_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3285. }
  3286. #define _DISABLE_CLOCK_clk_i2c2_apb_ { \
  3287. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c2_apb_ctrl_REG_ADDR); \
  3288. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3289. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3290. MA_OUTW(clk_i2c2_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3291. }
  3292. #define _GET_CLOCK_ENABLE_STATUS_clk_i2c2_apb_(_ezchip_macro_read_value_) { \
  3293. _ezchip_macro_read_value_=MA_INW(clk_i2c2_apb_ctrl_REG_ADDR) >> 31; \
  3294. _ezchip_macro_read_value_ &= 0x1;\
  3295. }
  3296. #define _ENABLE_CLOCK_clk_i2c2_core_ { \
  3297. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c2_core_ctrl_REG_ADDR); \
  3298. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3299. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3300. MA_OUTW(clk_i2c2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3301. }
  3302. #define _DISABLE_CLOCK_clk_i2c2_core_ { \
  3303. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c2_core_ctrl_REG_ADDR); \
  3304. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3305. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3306. MA_OUTW(clk_i2c2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3307. }
  3308. #define _GET_CLOCK_ENABLE_STATUS_clk_i2c2_core_(_ezchip_macro_read_value_) { \
  3309. _ezchip_macro_read_value_=MA_INW(clk_i2c2_core_ctrl_REG_ADDR) >> 31; \
  3310. _ezchip_macro_read_value_ &= 0x1;\
  3311. }
  3312. #define _DIVIDE_CLOCK_clk_i2c2_core_(div) { \
  3313. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c2_core_ctrl_REG_ADDR); \
  3314. _ezchip_macro_read_value_ &= ~(0x3F); \
  3315. _ezchip_macro_read_value_ |= (div&0x3F); \
  3316. MA_OUTW(clk_i2c2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3317. }
  3318. #define _GET_CLOCK_DIVIDE_STATUS_clk_i2c2_core_(_ezchip_macro_read_value_) { \
  3319. _ezchip_macro_read_value_=MA_INW(clk_i2c2_core_ctrl_REG_ADDR); \
  3320. _ezchip_macro_read_value_ &= 0x3f;\
  3321. }
  3322. #define _ENABLE_CLOCK_clk_i2c3_apb_ { \
  3323. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c3_apb_ctrl_REG_ADDR); \
  3324. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3325. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3326. MA_OUTW(clk_i2c3_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3327. }
  3328. #define _DISABLE_CLOCK_clk_i2c3_apb_ { \
  3329. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c3_apb_ctrl_REG_ADDR); \
  3330. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3331. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3332. MA_OUTW(clk_i2c3_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3333. }
  3334. #define _GET_CLOCK_ENABLE_STATUS_clk_i2c3_apb_(_ezchip_macro_read_value_) { \
  3335. _ezchip_macro_read_value_=MA_INW(clk_i2c3_apb_ctrl_REG_ADDR) >> 31; \
  3336. _ezchip_macro_read_value_ &= 0x1;\
  3337. }
  3338. #define _ENABLE_CLOCK_clk_i2c3_core_ { \
  3339. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c3_core_ctrl_REG_ADDR); \
  3340. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3341. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3342. MA_OUTW(clk_i2c3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3343. }
  3344. #define _DISABLE_CLOCK_clk_i2c3_core_ { \
  3345. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c3_core_ctrl_REG_ADDR); \
  3346. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3347. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3348. MA_OUTW(clk_i2c3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3349. }
  3350. #define _GET_CLOCK_ENABLE_STATUS_clk_i2c3_core_(_ezchip_macro_read_value_) { \
  3351. _ezchip_macro_read_value_=MA_INW(clk_i2c3_core_ctrl_REG_ADDR) >> 31; \
  3352. _ezchip_macro_read_value_ &= 0x1;\
  3353. }
  3354. #define _DIVIDE_CLOCK_clk_i2c3_core_(div) { \
  3355. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c3_core_ctrl_REG_ADDR); \
  3356. _ezchip_macro_read_value_ &= ~(0x3F); \
  3357. _ezchip_macro_read_value_ |= (div&0x3F); \
  3358. MA_OUTW(clk_i2c3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3359. }
  3360. #define _GET_CLOCK_DIVIDE_STATUS_clk_i2c3_core_(_ezchip_macro_read_value_) { \
  3361. _ezchip_macro_read_value_=MA_INW(clk_i2c3_core_ctrl_REG_ADDR); \
  3362. _ezchip_macro_read_value_ &= 0x3f;\
  3363. }
  3364. #define _ENABLE_CLOCK_clk_wdtimer_apb_ { \
  3365. uint32_t _ezchip_macro_read_value_=MA_INW(clk_wdtimer_apb_ctrl_REG_ADDR); \
  3366. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3367. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3368. MA_OUTW(clk_wdtimer_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3369. }
  3370. #define _DISABLE_CLOCK_clk_wdtimer_apb_ { \
  3371. uint32_t _ezchip_macro_read_value_=MA_INW(clk_wdtimer_apb_ctrl_REG_ADDR); \
  3372. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3373. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3374. MA_OUTW(clk_wdtimer_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3375. }
  3376. #define _GET_CLOCK_ENABLE_STATUS_clk_wdtimer_apb_(_ezchip_macro_read_value_) { \
  3377. _ezchip_macro_read_value_=MA_INW(clk_wdtimer_apb_ctrl_REG_ADDR) >> 31; \
  3378. _ezchip_macro_read_value_ &= 0x1;\
  3379. }
  3380. #define _ENABLE_CLOCK_clk_wdt_coreclk_ { \
  3381. uint32_t _ezchip_macro_read_value_=MA_INW(clk_wdt_coreclk_ctrl_REG_ADDR); \
  3382. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3383. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3384. MA_OUTW(clk_wdt_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3385. }
  3386. #define _DISABLE_CLOCK_clk_wdt_coreclk_ { \
  3387. uint32_t _ezchip_macro_read_value_=MA_INW(clk_wdt_coreclk_ctrl_REG_ADDR); \
  3388. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3389. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3390. MA_OUTW(clk_wdt_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3391. }
  3392. #define _GET_CLOCK_ENABLE_STATUS_clk_wdt_coreclk_(_ezchip_macro_read_value_) { \
  3393. _ezchip_macro_read_value_=MA_INW(clk_wdt_coreclk_ctrl_REG_ADDR) >> 31; \
  3394. _ezchip_macro_read_value_ &= 0x1;\
  3395. }
  3396. #define _DIVIDE_CLOCK_clk_wdt_coreclk_(div) { \
  3397. uint32_t _ezchip_macro_read_value_=MA_INW(clk_wdt_coreclk_ctrl_REG_ADDR); \
  3398. _ezchip_macro_read_value_ &= ~(0x3F); \
  3399. _ezchip_macro_read_value_ |= (div&0x3F); \
  3400. MA_OUTW(clk_wdt_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3401. }
  3402. #define _GET_CLOCK_DIVIDE_STATUS_clk_wdt_coreclk_(_ezchip_macro_read_value_) { \
  3403. _ezchip_macro_read_value_=MA_INW(clk_wdt_coreclk_ctrl_REG_ADDR); \
  3404. _ezchip_macro_read_value_ &= 0x3f;\
  3405. }
  3406. #define _ENABLE_CLOCK_clk_timer0_coreclk_ { \
  3407. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer0_coreclk_ctrl_REG_ADDR); \
  3408. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3409. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3410. MA_OUTW(clk_timer0_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3411. }
  3412. #define _DISABLE_CLOCK_clk_timer0_coreclk_ { \
  3413. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer0_coreclk_ctrl_REG_ADDR); \
  3414. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3415. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3416. MA_OUTW(clk_timer0_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3417. }
  3418. #define _GET_CLOCK_ENABLE_STATUS_clk_timer0_coreclk_(_ezchip_macro_read_value_) { \
  3419. _ezchip_macro_read_value_=MA_INW(clk_timer0_coreclk_ctrl_REG_ADDR) >> 31; \
  3420. _ezchip_macro_read_value_ &= 0x1;\
  3421. }
  3422. #define _DIVIDE_CLOCK_clk_timer0_coreclk_(div) { \
  3423. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer0_coreclk_ctrl_REG_ADDR); \
  3424. _ezchip_macro_read_value_ &= ~(0x3F); \
  3425. _ezchip_macro_read_value_ |= (div&0x3F); \
  3426. MA_OUTW(clk_timer0_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3427. }
  3428. #define _GET_CLOCK_DIVIDE_STATUS_clk_timer0_coreclk_(_ezchip_macro_read_value_) { \
  3429. _ezchip_macro_read_value_=MA_INW(clk_timer0_coreclk_ctrl_REG_ADDR); \
  3430. _ezchip_macro_read_value_ &= 0x3f;\
  3431. }
  3432. #define _ENABLE_CLOCK_clk_timer1_coreclk_ { \
  3433. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer1_coreclk_ctrl_REG_ADDR); \
  3434. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3435. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3436. MA_OUTW(clk_timer1_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3437. }
  3438. #define _DISABLE_CLOCK_clk_timer1_coreclk_ { \
  3439. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer1_coreclk_ctrl_REG_ADDR); \
  3440. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3441. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3442. MA_OUTW(clk_timer1_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3443. }
  3444. #define _GET_CLOCK_ENABLE_STATUS_clk_timer1_coreclk_(_ezchip_macro_read_value_) { \
  3445. _ezchip_macro_read_value_=MA_INW(clk_timer1_coreclk_ctrl_REG_ADDR) >> 31; \
  3446. _ezchip_macro_read_value_ &= 0x1;\
  3447. }
  3448. #define _DIVIDE_CLOCK_clk_timer1_coreclk_(div) { \
  3449. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer1_coreclk_ctrl_REG_ADDR); \
  3450. _ezchip_macro_read_value_ &= ~(0x3F); \
  3451. _ezchip_macro_read_value_ |= (div&0x3F); \
  3452. MA_OUTW(clk_timer1_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3453. }
  3454. #define _GET_CLOCK_DIVIDE_STATUS_clk_timer1_coreclk_(_ezchip_macro_read_value_) { \
  3455. _ezchip_macro_read_value_=MA_INW(clk_timer1_coreclk_ctrl_REG_ADDR); \
  3456. _ezchip_macro_read_value_ &= 0x3f;\
  3457. }
  3458. #define _ENABLE_CLOCK_clk_timer2_coreclk_ { \
  3459. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer2_coreclk_ctrl_REG_ADDR); \
  3460. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3461. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3462. MA_OUTW(clk_timer2_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3463. }
  3464. #define _DISABLE_CLOCK_clk_timer2_coreclk_ { \
  3465. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer2_coreclk_ctrl_REG_ADDR); \
  3466. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3467. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3468. MA_OUTW(clk_timer2_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3469. }
  3470. #define _GET_CLOCK_ENABLE_STATUS_clk_timer2_coreclk_(_ezchip_macro_read_value_) { \
  3471. _ezchip_macro_read_value_=MA_INW(clk_timer2_coreclk_ctrl_REG_ADDR) >> 31; \
  3472. _ezchip_macro_read_value_ &= 0x1;\
  3473. }
  3474. #define _DIVIDE_CLOCK_clk_timer2_coreclk_(div) { \
  3475. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer2_coreclk_ctrl_REG_ADDR); \
  3476. _ezchip_macro_read_value_ &= ~(0x3F); \
  3477. _ezchip_macro_read_value_ |= (div&0x3F); \
  3478. MA_OUTW(clk_timer2_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3479. }
  3480. #define _GET_CLOCK_DIVIDE_STATUS_clk_timer2_coreclk_(_ezchip_macro_read_value_) { \
  3481. _ezchip_macro_read_value_=MA_INW(clk_timer2_coreclk_ctrl_REG_ADDR); \
  3482. _ezchip_macro_read_value_ &= 0x3f;\
  3483. }
  3484. #define _ENABLE_CLOCK_clk_timer3_coreclk_ { \
  3485. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer3_coreclk_ctrl_REG_ADDR); \
  3486. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3487. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3488. MA_OUTW(clk_timer3_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3489. }
  3490. #define _DISABLE_CLOCK_clk_timer3_coreclk_ { \
  3491. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer3_coreclk_ctrl_REG_ADDR); \
  3492. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3493. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3494. MA_OUTW(clk_timer3_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3495. }
  3496. #define _GET_CLOCK_ENABLE_STATUS_clk_timer3_coreclk_(_ezchip_macro_read_value_) { \
  3497. _ezchip_macro_read_value_=MA_INW(clk_timer3_coreclk_ctrl_REG_ADDR) >> 31; \
  3498. _ezchip_macro_read_value_ &= 0x1;\
  3499. }
  3500. #define _DIVIDE_CLOCK_clk_timer3_coreclk_(div) { \
  3501. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer3_coreclk_ctrl_REG_ADDR); \
  3502. _ezchip_macro_read_value_ &= ~(0x3F); \
  3503. _ezchip_macro_read_value_ |= (div&0x3F); \
  3504. MA_OUTW(clk_timer3_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3505. }
  3506. #define _GET_CLOCK_DIVIDE_STATUS_clk_timer3_coreclk_(_ezchip_macro_read_value_) { \
  3507. _ezchip_macro_read_value_=MA_INW(clk_timer3_coreclk_ctrl_REG_ADDR); \
  3508. _ezchip_macro_read_value_ &= 0x3f;\
  3509. }
  3510. #define _ENABLE_CLOCK_clk_timer4_coreclk_ { \
  3511. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer4_coreclk_ctrl_REG_ADDR); \
  3512. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3513. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3514. MA_OUTW(clk_timer4_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3515. }
  3516. #define _DISABLE_CLOCK_clk_timer4_coreclk_ { \
  3517. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer4_coreclk_ctrl_REG_ADDR); \
  3518. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3519. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3520. MA_OUTW(clk_timer4_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3521. }
  3522. #define _GET_CLOCK_ENABLE_STATUS_clk_timer4_coreclk_(_ezchip_macro_read_value_) { \
  3523. _ezchip_macro_read_value_=MA_INW(clk_timer4_coreclk_ctrl_REG_ADDR) >> 31; \
  3524. _ezchip_macro_read_value_ &= 0x1;\
  3525. }
  3526. #define _DIVIDE_CLOCK_clk_timer4_coreclk_(div) { \
  3527. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer4_coreclk_ctrl_REG_ADDR); \
  3528. _ezchip_macro_read_value_ &= ~(0x3F); \
  3529. _ezchip_macro_read_value_ |= (div&0x3F); \
  3530. MA_OUTW(clk_timer4_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3531. }
  3532. #define _GET_CLOCK_DIVIDE_STATUS_clk_timer4_coreclk_(_ezchip_macro_read_value_) { \
  3533. _ezchip_macro_read_value_=MA_INW(clk_timer4_coreclk_ctrl_REG_ADDR); \
  3534. _ezchip_macro_read_value_ &= 0x3f;\
  3535. }
  3536. #define _ENABLE_CLOCK_clk_timer5_coreclk_ { \
  3537. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer5_coreclk_ctrl_REG_ADDR); \
  3538. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3539. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3540. MA_OUTW(clk_timer5_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3541. }
  3542. #define _DISABLE_CLOCK_clk_timer5_coreclk_ { \
  3543. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer5_coreclk_ctrl_REG_ADDR); \
  3544. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3545. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3546. MA_OUTW(clk_timer5_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3547. }
  3548. #define _GET_CLOCK_ENABLE_STATUS_clk_timer5_coreclk_(_ezchip_macro_read_value_) { \
  3549. _ezchip_macro_read_value_=MA_INW(clk_timer5_coreclk_ctrl_REG_ADDR) >> 31; \
  3550. _ezchip_macro_read_value_ &= 0x1;\
  3551. }
  3552. #define _DIVIDE_CLOCK_clk_timer5_coreclk_(div) { \
  3553. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer5_coreclk_ctrl_REG_ADDR); \
  3554. _ezchip_macro_read_value_ &= ~(0x3F); \
  3555. _ezchip_macro_read_value_ |= (div&0x3F); \
  3556. MA_OUTW(clk_timer5_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3557. }
  3558. #define _GET_CLOCK_DIVIDE_STATUS_clk_timer5_coreclk_(_ezchip_macro_read_value_) { \
  3559. _ezchip_macro_read_value_=MA_INW(clk_timer5_coreclk_ctrl_REG_ADDR); \
  3560. _ezchip_macro_read_value_ &= 0x3f;\
  3561. }
  3562. #define _ENABLE_CLOCK_clk_timer6_coreclk_ { \
  3563. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer6_coreclk_ctrl_REG_ADDR); \
  3564. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3565. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3566. MA_OUTW(clk_timer6_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3567. }
  3568. #define _DISABLE_CLOCK_clk_timer6_coreclk_ { \
  3569. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer6_coreclk_ctrl_REG_ADDR); \
  3570. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3571. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3572. MA_OUTW(clk_timer6_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3573. }
  3574. #define _GET_CLOCK_ENABLE_STATUS_clk_timer6_coreclk_(_ezchip_macro_read_value_) { \
  3575. _ezchip_macro_read_value_=MA_INW(clk_timer6_coreclk_ctrl_REG_ADDR) >> 31; \
  3576. _ezchip_macro_read_value_ &= 0x1;\
  3577. }
  3578. #define _DIVIDE_CLOCK_clk_timer6_coreclk_(div) { \
  3579. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer6_coreclk_ctrl_REG_ADDR); \
  3580. _ezchip_macro_read_value_ &= ~(0x3F); \
  3581. _ezchip_macro_read_value_ |= (div&0x3F); \
  3582. MA_OUTW(clk_timer6_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3583. }
  3584. #define _GET_CLOCK_DIVIDE_STATUS_clk_timer6_coreclk_(_ezchip_macro_read_value_) { \
  3585. _ezchip_macro_read_value_=MA_INW(clk_timer6_coreclk_ctrl_REG_ADDR); \
  3586. _ezchip_macro_read_value_ &= 0x3f;\
  3587. }
  3588. #define _ENABLE_CLOCK_clk_vp6intc_apb_ { \
  3589. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6intc_apb_ctrl_REG_ADDR); \
  3590. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3591. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3592. MA_OUTW(clk_vp6intc_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3593. }
  3594. #define _DISABLE_CLOCK_clk_vp6intc_apb_ { \
  3595. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6intc_apb_ctrl_REG_ADDR); \
  3596. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3597. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3598. MA_OUTW(clk_vp6intc_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3599. }
  3600. #define _GET_CLOCK_ENABLE_STATUS_clk_vp6intc_apb_(_ezchip_macro_read_value_) { \
  3601. _ezchip_macro_read_value_=MA_INW(clk_vp6intc_apb_ctrl_REG_ADDR) >> 31; \
  3602. _ezchip_macro_read_value_ &= 0x1;\
  3603. }
  3604. #define _ENABLE_CLOCK_clk_pwm_apb_ { \
  3605. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pwm_apb_ctrl_REG_ADDR); \
  3606. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3607. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3608. MA_OUTW(clk_pwm_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3609. }
  3610. #define _DISABLE_CLOCK_clk_pwm_apb_ { \
  3611. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pwm_apb_ctrl_REG_ADDR); \
  3612. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3613. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3614. MA_OUTW(clk_pwm_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3615. }
  3616. #define _GET_CLOCK_ENABLE_STATUS_clk_pwm_apb_(_ezchip_macro_read_value_) { \
  3617. _ezchip_macro_read_value_=MA_INW(clk_pwm_apb_ctrl_REG_ADDR) >> 31; \
  3618. _ezchip_macro_read_value_ &= 0x1;\
  3619. }
  3620. #define _ENABLE_CLOCK_clk_msi_apb_ { \
  3621. uint32_t _ezchip_macro_read_value_=MA_INW(clk_msi_apb_ctrl_REG_ADDR); \
  3622. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3623. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3624. MA_OUTW(clk_msi_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3625. }
  3626. #define _DISABLE_CLOCK_clk_msi_apb_ { \
  3627. uint32_t _ezchip_macro_read_value_=MA_INW(clk_msi_apb_ctrl_REG_ADDR); \
  3628. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3629. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3630. MA_OUTW(clk_msi_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3631. }
  3632. #define _GET_CLOCK_ENABLE_STATUS_clk_msi_apb_(_ezchip_macro_read_value_) { \
  3633. _ezchip_macro_read_value_=MA_INW(clk_msi_apb_ctrl_REG_ADDR) >> 31; \
  3634. _ezchip_macro_read_value_ &= 0x1;\
  3635. }
  3636. #define _ENABLE_CLOCK_clk_temp_apb_ { \
  3637. uint32_t _ezchip_macro_read_value_=MA_INW(clk_temp_apb_ctrl_REG_ADDR); \
  3638. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3639. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3640. MA_OUTW(clk_temp_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3641. }
  3642. #define _DISABLE_CLOCK_clk_temp_apb_ { \
  3643. uint32_t _ezchip_macro_read_value_=MA_INW(clk_temp_apb_ctrl_REG_ADDR); \
  3644. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3645. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3646. MA_OUTW(clk_temp_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3647. }
  3648. #define _GET_CLOCK_ENABLE_STATUS_clk_temp_apb_(_ezchip_macro_read_value_) { \
  3649. _ezchip_macro_read_value_=MA_INW(clk_temp_apb_ctrl_REG_ADDR) >> 31; \
  3650. _ezchip_macro_read_value_ &= 0x1;\
  3651. }
  3652. #define _ENABLE_CLOCK_clk_temp_sense_ { \
  3653. uint32_t _ezchip_macro_read_value_=MA_INW(clk_temp_sense_ctrl_REG_ADDR); \
  3654. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3655. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3656. MA_OUTW(clk_temp_sense_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3657. }
  3658. #define _DISABLE_CLOCK_clk_temp_sense_ { \
  3659. uint32_t _ezchip_macro_read_value_=MA_INW(clk_temp_sense_ctrl_REG_ADDR); \
  3660. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3661. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3662. MA_OUTW(clk_temp_sense_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3663. }
  3664. #define _GET_CLOCK_ENABLE_STATUS_clk_temp_sense_(_ezchip_macro_read_value_) { \
  3665. _ezchip_macro_read_value_=MA_INW(clk_temp_sense_ctrl_REG_ADDR) >> 31; \
  3666. _ezchip_macro_read_value_ &= 0x1;\
  3667. }
  3668. #define _DIVIDE_CLOCK_clk_temp_sense_(div) { \
  3669. uint32_t _ezchip_macro_read_value_=MA_INW(clk_temp_sense_ctrl_REG_ADDR); \
  3670. _ezchip_macro_read_value_ &= ~(0x1F); \
  3671. _ezchip_macro_read_value_ |= (div&0x1F); \
  3672. MA_OUTW(clk_temp_sense_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3673. }
  3674. #define _GET_CLOCK_DIVIDE_STATUS_clk_temp_sense_(_ezchip_macro_read_value_) { \
  3675. _ezchip_macro_read_value_=MA_INW(clk_temp_sense_ctrl_REG_ADDR); \
  3676. _ezchip_macro_read_value_ &= 0x1f;\
  3677. }
  3678. #define _ENABLE_CLOCK_clk_syserr_apb_ { \
  3679. uint32_t _ezchip_macro_read_value_=MA_INW(clk_syserr_apb_ctrl_REG_ADDR); \
  3680. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3681. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3682. MA_OUTW(clk_syserr_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3683. }
  3684. #define _DISABLE_CLOCK_clk_syserr_apb_ { \
  3685. uint32_t _ezchip_macro_read_value_=MA_INW(clk_syserr_apb_ctrl_REG_ADDR); \
  3686. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3687. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3688. MA_OUTW(clk_syserr_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3689. }
  3690. #define _GET_CLOCK_ENABLE_STATUS_clk_syserr_apb_(_ezchip_macro_read_value_) { \
  3691. _ezchip_macro_read_value_=MA_INW(clk_syserr_apb_ctrl_REG_ADDR) >> 31; \
  3692. _ezchip_macro_read_value_ &= 0x1;\
  3693. }
  3694. #endif //_CLKGEN_MACRO_H_