bootmain.c 4.2 KB

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  1. #include "sys.h"
  2. #include "spi_flash.h"
  3. #include "spi.h"
  4. #include "encoding.h"
  5. #include "clkgen_ctrl_macro.h"
  6. #include "rstgen_ctrl_macro.h"
  7. #include "syscon_iopad_ctrl_macro.h"
  8. #if defined(BEAGLEV)
  9. #include <syscon_sysmain_ctrl_macro.h>
  10. #include <ezGPIO_fullMux_ctrl_macro.h>
  11. #include <rstgen_ctrl_macro.h>
  12. #endif
  13. typedef void ( *STARTRUNNING )( unsigned int par1 );
  14. /*
  15. To run a procedure from the address:start
  16. start: start address of runing in armmode, not do address align checking
  17. */
  18. void start2run32(unsigned int start)
  19. {
  20. (( STARTRUNNING )(start))(0);
  21. }
  22. #define SPIBOOT_LOAD_ADDR_OFFSET 252
  23. /*read data from flash to the destination address
  24. *
  25. *spi_flash: flash device informations
  26. *des_addr: store the data read from flash
  27. *page_offset:Offset of data stored in flash
  28. *mode:flash work mode
  29. */
  30. static int load_data(struct spi_flash* spi_flash,unsigned int des_addr,unsigned int page_offset,int mode)
  31. {
  32. u8 dataBuf[260];
  33. u32 startPage,endPage;
  34. u32 pageSize;
  35. u32 fileSize;
  36. u8 *addr;
  37. int ret;
  38. int i;
  39. u32 offset;
  40. pageSize = spi_flash->page_size;
  41. addr = (u8 *)des_addr;
  42. offset = page_offset*pageSize;
  43. /*read first page,get the file size*/
  44. ret = spi_flash->read(spi_flash,offset,pageSize,dataBuf,mode);
  45. if(ret != 0)
  46. {
  47. printk("read fail#\r\n");
  48. return -1;
  49. }
  50. /*calculate file size*/
  51. fileSize = (dataBuf[3] << 24) | (dataBuf[2] << 16) | (dataBuf[1] << 8) | (dataBuf[0]) ;
  52. if(fileSize == 0)
  53. return -1;
  54. endPage = ((fileSize + 255) >> 8);//page align
  55. /*copy the first page data*/
  56. sys_memcpy(addr, &dataBuf[4], SPIBOOT_LOAD_ADDR_OFFSET);
  57. offset += pageSize;
  58. addr += SPIBOOT_LOAD_ADDR_OFFSET;
  59. /*read Remaining pages data*/
  60. for(i=1; i<=endPage; i++)
  61. {
  62. ret = spi_flash->read(spi_flash,offset,pageSize, addr, mode);
  63. if(ret != 0)
  64. {
  65. printk("read fail##\r\n");
  66. return -1;
  67. }
  68. offset += pageSize;
  69. addr +=pageSize;
  70. }
  71. return 0;
  72. }
  73. void load_and_run_ddr(struct spi_flash* spi_flash,int mode)
  74. {
  75. unsigned int addr;
  76. int ret;
  77. addr = DEFAULT_DDR_ADDR;
  78. ret = load_data(spi_flash,addr,DEFAULT_DDR_OFFSET,mode);
  79. printk("bootloader version:%s\n\n",VERSION);
  80. if(!ret)
  81. {
  82. writel(0x1, 0x2000004);
  83. start2run32(addr);
  84. }
  85. else
  86. printk("\nload ddr bin fail.\n");
  87. /*never run to here*/
  88. while(1);
  89. }
  90. void boot_from_spi(int mode)
  91. {
  92. struct spi_flash* spi_flash;
  93. int ret;
  94. u32 *addr;
  95. u32 val;
  96. cadence_qspi_init(0, mode);
  97. spi_flash = spi_flash_probe(0, 0, 31250000, 0, (u32)SPI_DATAMODE_8);
  98. /*init ddr*/
  99. load_and_run_ddr(spi_flash,mode);
  100. }
  101. static void chip_clk_init()
  102. {
  103. _SWITCH_CLOCK_clk_cpundbus_root_SOURCE_clk_pll0_out_;
  104. _SWITCH_CLOCK_clk_dla_root_SOURCE_clk_pll1_out_;
  105. _SWITCH_CLOCK_clk_dsp_root_SOURCE_clk_pll2_out_;
  106. _SWITCH_CLOCK_clk_perh0_root_SOURCE_clk_pll0_out_;
  107. // slow down nne bus can fix nne50 & vp6 ram scan issue,
  108. // as well as vin_subsys reg scan issue.
  109. // _SWITCH_CLOCK_clk_nne_bus_SOURCE_clk_cpu_axi_;
  110. }
  111. /*only hartid 0 call this function*/
  112. void BootMain(void)
  113. {
  114. int boot_mode = 0;
  115. /*switch to pll mode*/
  116. chip_clk_init();
  117. //for illegal instruction exception
  118. _SET_SYSCON_REG_register50_SCFG_funcshare_pad_ctrl_18(0x00c000c0);
  119. _CLEAR_RESET_rstgen_rstn_usbnoc_axi_;
  120. _CLEAR_RESET_rstgen_rstn_hifi4noc_axi_;
  121. _ENABLE_CLOCK_clk_x2c_axi_;
  122. _CLEAR_RESET_rstgen_rstn_x2c_axi_;
  123. _CLEAR_RESET_rstgen_rstn_dspx2c_axi_;
  124. _CLEAR_RESET_rstgen_rstn_dma1p_axi_;
  125. _ENABLE_CLOCK_clk_msi_apb_;
  126. _CLEAR_RESET_rstgen_rstn_msi_apb_;
  127. _ASSERT_RESET_rstgen_rstn_x2c_axi_;
  128. _CLEAR_RESET_rstgen_rstn_x2c_axi_;
  129. //end for illegal instruction exception
  130. #if defined(BEAGLEV)
  131. _SET_SYSCON_REG_register69_core1_en(1);
  132. _SET_SYSCON_REG_register104_SCFG_io_padshare_sel(6);
  133. _SET_SYSCON_REG_register32_SCFG_funcshare_pad_ctrl_0(0x00c00000);
  134. _SET_SYSCON_REG_register33_SCFG_funcshare_pad_ctrl_1(0x00c000c0);
  135. _SET_SYSCON_REG_register34_SCFG_funcshare_pad_ctrl_2(0x00c000c0);
  136. _SET_SYSCON_REG_register35_SCFG_funcshare_pad_ctrl_3(0x00c000c0);
  137. _SET_SYSCON_REG_register39_SCFG_funcshare_pad_ctrl_7(0x00c300c3);
  138. _SET_SYSCON_REG_register38_SCFG_funcshare_pad_ctrl_6(0x00c00000);
  139. #endif
  140. uart_init(3);
  141. writel(0x18000000, 0x1801fffc);
  142. writel(0x1, 0x2000004); /*从bootrom中恢复hart1*/
  143. boot_from_spi(1);
  144. /*never run to heare*/
  145. }