12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968396939703971397239733974397539763977397839793980398139823983398439853986398739883989399039913992399339943995399639973998399940004001400240034004400540064007400840094010401140124013401440154016401740184019402040214022402340244025402640274028402940304031403240334034403540364037403840394040404140424043404440454046404740484049405040514052405340544055405640574058405940604061406240634064406540664067406840694070407140724073407440754076407740784079408040814082408340844085408640874088408940904091409240934094409540964097409840994100410141024103410441054106410741084109411041114112411341144115411641174118411941204121412241234124412541264127412841294130413141324133413441354136413741384139414041414142414341444145414641474148414941504151415241534154415541564157415841594160416141624163416441654166416741684169417041714172417341744175417641774178417941804181418241834184418541864187418841894190419141924193419441954196419741984199420042014202420342044205420642074208420942104211421242134214421542164217421842194220422142224223422442254226422742284229423042314232423342344235423642374238423942404241424242434244424542464247424842494250425142524253425442554256425742584259426042614262426342644265426642674268426942704271427242734274427542764277427842794280428142824283428442854286428742884289429042914292429342944295429642974298429943004301430243034304430543064307430843094310431143124313431443154316431743184319432043214322432343244325432643274328432943304331433243334334433543364337433843394340434143424343434443454346434743484349435043514352435343544355435643574358435943604361436243634364436543664367436843694370437143724373437443754376437743784379438043814382438343844385438643874388438943904391439243934394439543964397439843994400440144024403440444054406440744084409441044114412441344144415441644174418 |
- /* SPDX-License-Identifier: GPL-2.0-or-later */
- /**
- ******************************************************************************
- * @file clkgen_ctrl_macro.h
- * @author StarFive Technology
- * @version V1.0
- * @date 06/25/2020
- * @brief
- ******************************************************************************
- * @copy
- *
- * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
- */
- #ifndef _CLKGEN_MACRO_H_
- #define _CLKGEN_MACRO_H_
- //#define CLKGEN_BASE_ADDR 0x0
- #define clk_cpundbus_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x0
- #define clk_dla_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x4
- #define clk_dsp_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x8
- #define clk_gmacusb_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xC
- #define clk_perh0_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x10
- #define clk_perh1_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x14
- #define clk_vin_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x18
- #define clk_vout_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1C
- #define clk_audio_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x20
- #define clk_cdechifi4_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x24
- #define clk_cdec_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x28
- #define clk_voutbus_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2C
- #define clk_cpunbus_root_div_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x30
- #define clk_dsp_root_div_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x34
- #define clk_perh0_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x38
- #define clk_perh1_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x3C
- #define clk_pll0_testout_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x40
- #define clk_pll1_testout_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x44
- #define clk_pll2_testout_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x48
- #define clk_pll2_refclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x4C
- #define clk_cpu_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x50
- #define clk_cpu_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x54
- #define clk_ahb_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x58
- #define clk_apb1_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x5C
- #define clk_apb2_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x60
- #define clk_dom3ahb_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x64
- #define clk_dom7ahb_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x68
- #define clk_u74_core0_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x6C
- #define clk_u74_core1_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x70
- #define clk_u74_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x74
- #define clk_u74rtc_toggle_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x78
- #define clk_sgdma2p_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x7C
- #define clk_dma2pnoc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x80
- #define clk_sgdma2p_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x84
- #define clk_dla_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x88
- #define clk_dla_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x8C
- #define clk_dlanoc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x90
- #define clk_dla_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x94
- #define clk_vp6_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x98
- #define clk_vp6bus_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x9C
- #define clk_vp6_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xA0
- #define clk_vcdecbus_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xA4
- #define clk_vdec_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xA8
- #define clk_vdec_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xAC
- #define clk_vdecbrg_mainclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xB0
- #define clk_vdec_bclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xB4
- #define clk_vdec_cclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xB8
- #define clk_vdec_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xBC
- #define clk_jpeg_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xC0
- #define clk_jpeg_cclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xC4
- #define clk_jpeg_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xC8
- #define clk_gc300_2x_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xCC
- #define clk_gc300_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xD0
- #define clk_jpcgc300_axibus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xD4
- #define clk_gc300_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xD8
- #define clk_jpcgc300_mainclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xDC
- #define clk_venc_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xE0
- #define clk_venc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xE4
- #define clk_vencbrg_mainclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xE8
- #define clk_venc_bclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xEC
- #define clk_venc_cclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xF0
- #define clk_venc_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xF4
- #define clk_ddrpll_div2_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xF8
- #define clk_ddrpll_div4_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xFC
- #define clk_ddrpll_div8_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x100
- #define clk_ddrosc_div2_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x104
- #define clk_ddrc0_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x108
- #define clk_ddrc1_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x10C
- #define clk_ddrphy_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x110
- #define clk_noc_rob_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x114
- #define clk_noc_cog_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x118
- #define clk_nne_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x11C
- #define clk_nnebus_src1_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x120
- #define clk_nne_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x124
- #define clk_nne_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x128
- #define clk_nnenoc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x12C
- #define clk_dlaslv_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x130
- #define clk_dspx2c_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x134
- #define clk_hifi4_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x138
- #define clk_hifi4_corefree_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x13C
- #define clk_hifi4_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x140
- #define clk_hifi4_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x144
- #define clk_hifi4_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x148
- #define clk_hifi4noc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x14C
- #define clk_sgdma1p_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x150
- #define clk_sgdma1p_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x154
- #define clk_dma1p_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x158
- #define clk_x2c_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x15C
- #define clk_usb_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x160
- #define clk_usb_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x164
- #define clk_usbnoc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x168
- #define clk_usbphy_rootdiv_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x16C
- #define clk_usbphy_125m_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x170
- #define clk_usbphy_plldiv25m_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x174
- #define clk_usbphy_25m_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x178
- #define clk_audio_div_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x17C
- #define clk_audio_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x180
- #define clk_audio_12288_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x184
- #define clk_vin_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x188
- #define clk_isp0_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x18C
- #define clk_isp0_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x190
- #define clk_isp0noc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x194
- #define clk_ispslv_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x198
- #define clk_isp1_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x19C
- #define clk_isp1_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1A0
- #define clk_isp1noc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1A4
- #define clk_vin_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1A8
- #define clk_vin_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1AC
- #define clk_vinnoc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1B0
- #define clk_vout_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1B4
- #define clk_dispbus_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1B8
- #define clk_disp_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1BC
- #define clk_disp_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1C0
- #define clk_dispnoc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1C4
- #define clk_sdio0_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1C8
- #define clk_sdio0_cclkint_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1CC
- #define clk_sdio0_cclkint_inv_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1D0
- #define clk_sdio1_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1D4
- #define clk_sdio1_cclkint_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1D8
- #define clk_sdio1_cclkint_inv_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1DC
- #define clk_gmac_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1E0
- #define clk_gmac_root_div_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1E4
- #define clk_gmac_ptp_refclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1E8
- #define clk_gmac_gtxclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1EC
- #define clk_gmac_rmii_txclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1F0
- #define clk_gmac_rmii_rxclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1F4
- #define clk_gmac_tx_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1F8
- #define clk_gmac_tx_inv_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1FC
- #define clk_gmac_rx_pre_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x200
- #define clk_gmac_rx_inv_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x204
- #define clk_gmac_rmii_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x208
- #define clk_gmac_tophyref_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x20C
- #define clk_spi2ahb_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x210
- #define clk_spi2ahb_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x214
- #define clk_ezmaster_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x218
- #define clk_e24_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x21C
- #define clk_e24rtc_toggle_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x220
- #define clk_qspi_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x224
- #define clk_qspi_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x228
- #define clk_qspi_refclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x22C
- #define clk_sec_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x230
- #define clk_aes_clk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x234
- #define clk_sha_clk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x238
- #define clk_pka_clk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x23C
- #define clk_trng_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x240
- #define clk_otp_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x244
- #define clk_uart0_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x248
- #define clk_uart0_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x24C
- #define clk_uart1_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x250
- #define clk_uart1_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x254
- #define clk_spi0_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x258
- #define clk_spi0_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x25C
- #define clk_spi1_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x260
- #define clk_spi1_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x264
- #define clk_i2c0_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x268
- #define clk_i2c0_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x26C
- #define clk_i2c1_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x270
- #define clk_i2c1_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x274
- #define clk_gpio_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x278
- #define clk_uart2_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x27C
- #define clk_uart2_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x280
- #define clk_uart3_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x284
- #define clk_uart3_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x288
- #define clk_spi2_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x28C
- #define clk_spi2_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x290
- #define clk_spi3_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x294
- #define clk_spi3_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x298
- #define clk_i2c2_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x29C
- #define clk_i2c2_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2A0
- #define clk_i2c3_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2A4
- #define clk_i2c3_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2A8
- #define clk_wdtimer_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2AC
- #define clk_wdt_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2B0
- #define clk_timer0_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2B4
- #define clk_timer1_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2B8
- #define clk_timer2_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2BC
- #define clk_timer3_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2C0
- #define clk_timer4_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2C4
- #define clk_timer5_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2C8
- #define clk_timer6_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2CC
- #define clk_vp6intc_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2D0
- #define clk_pwm_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2D4
- #define clk_msi_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2D8
- #define clk_temp_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2DC
- #define clk_temp_sense_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2E0
- #define clk_syserr_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2E4
- #define _ENABLE_CLOCK_clk_cpundbus_root_ {}
- #define _SWITCH_CLOCK_clk_cpundbus_root_SOURCE_clk_osc_sys_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_cpundbus_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
- MA_OUTW(clk_cpundbus_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_cpundbus_root_SOURCE_clk_pll0_out_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_cpundbus_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
- MA_OUTW(clk_cpundbus_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_cpundbus_root_SOURCE_clk_pll1_out_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_cpundbus_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
- MA_OUTW(clk_cpundbus_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_cpundbus_root_SOURCE_clk_pll2_out_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_cpundbus_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x3&0x3)<<24; \
- MA_OUTW(clk_cpundbus_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_SOURCE_STATUS_clk_cpundbus_root_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_cpundbus_root_ctrl_REG_ADDR) >> 24; \
- _ezchip_macro_read_value_ &= 0x3;\
- }
- #define _ENABLE_CLOCK_clk_dla_root_ {}
- #define _SWITCH_CLOCK_clk_dla_root_SOURCE_clk_osc_sys_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
- MA_OUTW(clk_dla_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_dla_root_SOURCE_clk_pll1_out_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
- MA_OUTW(clk_dla_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_dla_root_SOURCE_clk_pll2_out_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
- MA_OUTW(clk_dla_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_SOURCE_STATUS_clk_dla_root_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_dla_root_ctrl_REG_ADDR) >> 24; \
- _ezchip_macro_read_value_ &= 0x3;\
- }
- #define _ENABLE_CLOCK_clk_dsp_root_ {}
- #define _SWITCH_CLOCK_clk_dsp_root_SOURCE_clk_osc_sys_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dsp_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
- MA_OUTW(clk_dsp_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_dsp_root_SOURCE_clk_pll0_out_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dsp_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
- MA_OUTW(clk_dsp_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_dsp_root_SOURCE_clk_pll1_out_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dsp_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
- MA_OUTW(clk_dsp_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_dsp_root_SOURCE_clk_pll2_out_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dsp_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x3&0x3)<<24; \
- MA_OUTW(clk_dsp_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_SOURCE_STATUS_clk_dsp_root_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_dsp_root_ctrl_REG_ADDR) >> 24; \
- _ezchip_macro_read_value_ &= 0x3;\
- }
- #define _ENABLE_CLOCK_clk_gmacusb_root_ {}
- #define _SWITCH_CLOCK_clk_gmacusb_root_SOURCE_clk_osc_sys_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmacusb_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
- MA_OUTW(clk_gmacusb_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_gmacusb_root_SOURCE_clk_pll0_out_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmacusb_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
- MA_OUTW(clk_gmacusb_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_gmacusb_root_SOURCE_clk_pll2_out_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmacusb_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
- MA_OUTW(clk_gmacusb_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_SOURCE_STATUS_clk_gmacusb_root_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_gmacusb_root_ctrl_REG_ADDR) >> 24; \
- _ezchip_macro_read_value_ &= 0x3;\
- }
- #define _ENABLE_CLOCK_clk_perh0_root_ {}
- #define _SWITCH_CLOCK_clk_perh0_root_SOURCE_clk_osc_sys_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_perh0_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<24); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<24; \
- MA_OUTW(clk_perh0_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_perh0_root_SOURCE_clk_pll0_out_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_perh0_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<24); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<24; \
- MA_OUTW(clk_perh0_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_SOURCE_STATUS_clk_perh0_root_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_perh0_root_ctrl_REG_ADDR) >> 24; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_perh1_root_ {}
- #define _SWITCH_CLOCK_clk_perh1_root_SOURCE_clk_osc_sys_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_perh1_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<24); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<24; \
- MA_OUTW(clk_perh1_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_perh1_root_SOURCE_clk_pll2_out_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_perh1_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<24); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<24; \
- MA_OUTW(clk_perh1_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_SOURCE_STATUS_clk_perh1_root_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_perh1_root_ctrl_REG_ADDR) >> 24; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_vin_root_ {}
- #define _SWITCH_CLOCK_clk_vin_root_SOURCE_clk_osc_sys_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
- MA_OUTW(clk_vin_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_vin_root_SOURCE_clk_pll1_out_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
- MA_OUTW(clk_vin_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_vin_root_SOURCE_clk_pll2_out_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
- MA_OUTW(clk_vin_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_SOURCE_STATUS_clk_vin_root_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_vin_root_ctrl_REG_ADDR) >> 24; \
- _ezchip_macro_read_value_ &= 0x3;\
- }
- #define _ENABLE_CLOCK_clk_vout_root_ {}
- #define _SWITCH_CLOCK_clk_vout_root_SOURCE_clk_osc_aud_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vout_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
- MA_OUTW(clk_vout_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_vout_root_SOURCE_clk_pll0_out_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vout_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
- MA_OUTW(clk_vout_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_vout_root_SOURCE_clk_pll2_out_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vout_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
- MA_OUTW(clk_vout_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_SOURCE_STATUS_clk_vout_root_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_vout_root_ctrl_REG_ADDR) >> 24; \
- _ezchip_macro_read_value_ &= 0x3;\
- }
- #define _ENABLE_CLOCK_clk_audio_root_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_audio_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_audio_root_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_audio_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_audio_root_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_audio_root_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_audio_root_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_audio_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_audio_root_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_audio_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_cdechifi4_root_ {}
- #define _SWITCH_CLOCK_clk_cdechifi4_root_SOURCE_clk_osc_sys_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_cdechifi4_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
- MA_OUTW(clk_cdechifi4_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_cdechifi4_root_SOURCE_clk_pll1_out_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_cdechifi4_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
- MA_OUTW(clk_cdechifi4_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_cdechifi4_root_SOURCE_clk_pll2_out_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_cdechifi4_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
- MA_OUTW(clk_cdechifi4_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_SOURCE_STATUS_clk_cdechifi4_root_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_cdechifi4_root_ctrl_REG_ADDR) >> 24; \
- _ezchip_macro_read_value_ &= 0x3;\
- }
- #define _ENABLE_CLOCK_clk_cdec_root_ {}
- #define _SWITCH_CLOCK_clk_cdec_root_SOURCE_clk_osc_sys_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_cdec_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
- MA_OUTW(clk_cdec_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_cdec_root_SOURCE_clk_pll0_out_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_cdec_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
- MA_OUTW(clk_cdec_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_cdec_root_SOURCE_clk_pll1_out_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_cdec_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
- MA_OUTW(clk_cdec_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_SOURCE_STATUS_clk_cdec_root_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_cdec_root_ctrl_REG_ADDR) >> 24; \
- _ezchip_macro_read_value_ &= 0x3;\
- }
- #define _ENABLE_CLOCK_clk_voutbus_root_ {}
- #define _SWITCH_CLOCK_clk_voutbus_root_SOURCE_clk_osc_aud_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_voutbus_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
- MA_OUTW(clk_voutbus_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_voutbus_root_SOURCE_clk_pll0_out_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_voutbus_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
- MA_OUTW(clk_voutbus_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_voutbus_root_SOURCE_clk_pll2_out_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_voutbus_root_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
- MA_OUTW(clk_voutbus_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_SOURCE_STATUS_clk_voutbus_root_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_voutbus_root_ctrl_REG_ADDR) >> 24; \
- _ezchip_macro_read_value_ &= 0x3;\
- }
- #define _ENABLE_CLOCK_clk_cpunbus_root_div_ {}
- #define _DIVIDE_CLOCK_clk_cpunbus_root_div_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_cpunbus_root_div_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3); \
- _ezchip_macro_read_value_ |= (div&0x3); \
- MA_OUTW(clk_cpunbus_root_div_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_cpunbus_root_div_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_cpunbus_root_div_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x3;\
- }
- #define _ENABLE_CLOCK_clk_dsp_root_div_ {}
- #define _DIVIDE_CLOCK_clk_dsp_root_div_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dsp_root_div_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x7); \
- _ezchip_macro_read_value_ |= (div&0x7); \
- MA_OUTW(clk_dsp_root_div_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_dsp_root_div_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_dsp_root_div_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x7;\
- }
- #define _ENABLE_CLOCK_clk_perh0_src_ {}
- #define _DIVIDE_CLOCK_clk_perh0_src_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_perh0_src_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x7); \
- _ezchip_macro_read_value_ |= (div&0x7); \
- MA_OUTW(clk_perh0_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_perh0_src_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_perh0_src_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x7;\
- }
- #define _ENABLE_CLOCK_clk_perh1_src_ {}
- #define _DIVIDE_CLOCK_clk_perh1_src_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_perh1_src_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x7); \
- _ezchip_macro_read_value_ |= (div&0x7); \
- MA_OUTW(clk_perh1_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_perh1_src_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_perh1_src_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x7;\
- }
- #define _ENABLE_CLOCK_clk_pll0_testout_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll0_testout_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_pll0_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_pll0_testout_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll0_testout_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_pll0_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_pll0_testout_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_pll0_testout_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_pll0_testout_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll0_testout_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1F); \
- _ezchip_macro_read_value_ |= (div&0x1F); \
- MA_OUTW(clk_pll0_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_pll0_testout_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_pll0_testout_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x1f;\
- }
- #define _ENABLE_CLOCK_clk_pll1_testout_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll1_testout_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_pll1_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_pll1_testout_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll1_testout_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_pll1_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_pll1_testout_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_pll1_testout_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_pll1_testout_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll1_testout_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1F); \
- _ezchip_macro_read_value_ |= (div&0x1F); \
- MA_OUTW(clk_pll1_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_pll1_testout_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_pll1_testout_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x1f;\
- }
- #define _ENABLE_CLOCK_clk_pll2_testout_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll2_testout_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_pll2_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_pll2_testout_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll2_testout_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_pll2_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_pll2_testout_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_pll2_testout_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_pll2_testout_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll2_testout_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1F); \
- _ezchip_macro_read_value_ |= (div&0x1F); \
- MA_OUTW(clk_pll2_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_pll2_testout_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_pll2_testout_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x1f;\
- }
- #define _ENABLE_CLOCK_clk_pll2_refclk_ {}
- #define _SWITCH_CLOCK_clk_pll2_refclk_SOURCE_clk_osc_sys_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll2_refclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<24); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<24; \
- MA_OUTW(clk_pll2_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_pll2_refclk_SOURCE_clk_osc_aud_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll2_refclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<24); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<24; \
- MA_OUTW(clk_pll2_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_SOURCE_STATUS_clk_pll2_refclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_pll2_refclk_ctrl_REG_ADDR) >> 24; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_cpu_core_ {}
- #define _DIVIDE_CLOCK_clk_cpu_core_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_cpu_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_cpu_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_cpu_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_cpu_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_cpu_axi_ {}
- #define _DIVIDE_CLOCK_clk_cpu_axi_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_cpu_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_cpu_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_cpu_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_cpu_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_ahb_bus_ {}
- #define _DIVIDE_CLOCK_clk_ahb_bus_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ahb_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_ahb_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_ahb_bus_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_ahb_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_apb1_bus_ {}
- #define _DIVIDE_CLOCK_clk_apb1_bus_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_apb1_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_apb1_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_apb1_bus_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_apb1_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_apb2_bus_ {}
- #define _DIVIDE_CLOCK_clk_apb2_bus_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_apb2_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_apb2_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_apb2_bus_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_apb2_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_dom3ahb_bus_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dom3ahb_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_dom3ahb_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_dom3ahb_bus_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dom3ahb_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_dom3ahb_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_dom3ahb_bus_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_dom3ahb_bus_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_dom7ahb_bus_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dom7ahb_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_dom7ahb_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_dom7ahb_bus_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dom7ahb_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_dom7ahb_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_dom7ahb_bus_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_dom7ahb_bus_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_u74_core0_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74_core0_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_u74_core0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_u74_core0_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74_core0_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_u74_core0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_u74_core0_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_u74_core0_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_u74_core1_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74_core1_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_u74_core1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_u74_core1_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74_core1_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_u74_core1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_u74_core1_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_u74_core1_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_u74_core1_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74_core1_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_u74_core1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_u74_core1_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_u74_core1_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_u74_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_u74_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_u74_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_u74_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_u74_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_u74_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_u74rtc_toggle_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74rtc_toggle_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_u74rtc_toggle_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_u74rtc_toggle_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74rtc_toggle_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_u74rtc_toggle_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_u74rtc_toggle_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_u74rtc_toggle_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_sgdma2p_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_sgdma2p_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_sgdma2p_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_sgdma2p_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_sgdma2p_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_sgdma2p_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_sgdma2p_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_sgdma2p_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_dma2pnoc_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dma2pnoc_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_dma2pnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_dma2pnoc_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dma2pnoc_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_dma2pnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_dma2pnoc_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_dma2pnoc_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_sgdma2p_ahb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_sgdma2p_ahb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_sgdma2p_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_sgdma2p_ahb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_sgdma2p_ahb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_sgdma2p_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_sgdma2p_ahb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_sgdma2p_ahb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_dla_bus_ {}
- #define _DIVIDE_CLOCK_clk_dla_bus_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x7); \
- _ezchip_macro_read_value_ |= (div&0x7); \
- MA_OUTW(clk_dla_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_dla_bus_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_dla_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x7;\
- }
- #define _ENABLE_CLOCK_clk_dla_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_dla_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_dla_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_dla_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_dla_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_dla_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_dlanoc_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dlanoc_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_dlanoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_dlanoc_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dlanoc_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_dlanoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_dlanoc_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_dlanoc_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_dla_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_dla_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_dla_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_dla_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_dla_apb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_dla_apb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_vp6_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_vp6_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_vp6_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_vp6_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_vp6_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_vp6_core_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_vp6_core_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x7); \
- _ezchip_macro_read_value_ |= (div&0x7); \
- MA_OUTW(clk_vp6_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_vp6_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_vp6_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x7;\
- }
- #define _ENABLE_CLOCK_clk_vp6bus_src_ {}
- #define _DIVIDE_CLOCK_clk_vp6bus_src_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6bus_src_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x7); \
- _ezchip_macro_read_value_ |= (div&0x7); \
- MA_OUTW(clk_vp6bus_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_vp6bus_src_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_vp6bus_src_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x7;\
- }
- #define _ENABLE_CLOCK_clk_vp6_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_vp6_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_vp6_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_vp6_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_vp6_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_vp6_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_vp6_axi_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x7); \
- _ezchip_macro_read_value_ |= (div&0x7); \
- MA_OUTW(clk_vp6_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_vp6_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_vp6_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x7;\
- }
- #define _ENABLE_CLOCK_clk_vcdecbus_src_ {}
- #define _DIVIDE_CLOCK_clk_vcdecbus_src_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vcdecbus_src_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x7); \
- _ezchip_macro_read_value_ |= (div&0x7); \
- MA_OUTW(clk_vcdecbus_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_vcdecbus_src_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_vcdecbus_src_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x7;\
- }
- #define _ENABLE_CLOCK_clk_vdec_bus_ {}
- #define _DIVIDE_CLOCK_clk_vdec_bus_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_vdec_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_vdec_bus_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_vdec_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_vdec_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_vdec_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_vdec_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_vdec_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_vdec_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_vdec_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_vdecbrg_mainclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdecbrg_mainclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_vdecbrg_mainclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_vdecbrg_mainclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdecbrg_mainclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_vdecbrg_mainclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_vdecbrg_mainclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_vdecbrg_mainclk_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_vdec_bclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_bclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_vdec_bclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_vdec_bclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_bclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_vdec_bclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_vdec_bclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_vdec_bclk_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_vdec_bclk_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_bclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_vdec_bclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_vdec_bclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_vdec_bclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_vdec_cclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_cclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_vdec_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_vdec_cclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_cclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_vdec_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_vdec_cclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_vdec_cclk_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_vdec_cclk_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_cclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_vdec_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_vdec_cclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_vdec_cclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_vdec_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_vdec_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_vdec_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_vdec_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_vdec_apb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_vdec_apb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_jpeg_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_jpeg_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_jpeg_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_jpeg_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_jpeg_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_jpeg_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_jpeg_axi_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_jpeg_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_jpeg_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_jpeg_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_jpeg_cclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_cclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_jpeg_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_jpeg_cclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_cclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_jpeg_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_jpeg_cclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_jpeg_cclk_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_jpeg_cclk_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_cclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_jpeg_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_jpeg_cclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_jpeg_cclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_jpeg_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_jpeg_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_jpeg_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_jpeg_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_jpeg_apb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_jpeg_apb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_gc300_2x_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gc300_2x_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_gc300_2x_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_gc300_2x_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gc300_2x_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_gc300_2x_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_gc300_2x_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_gc300_2x_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_gc300_2x_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gc300_2x_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_gc300_2x_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_gc300_2x_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_gc300_2x_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_gc300_ahb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gc300_ahb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_gc300_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_gc300_ahb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gc300_ahb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_gc300_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_gc300_ahb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_gc300_ahb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_jpcgc300_axibus_ {}
- #define _DIVIDE_CLOCK_clk_jpcgc300_axibus_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpcgc300_axibus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_jpcgc300_axibus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_jpcgc300_axibus_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_jpcgc300_axibus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_gc300_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gc300_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_gc300_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_gc300_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gc300_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_gc300_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_gc300_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_gc300_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_jpcgc300_mainclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpcgc300_mainclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_jpcgc300_mainclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_jpcgc300_mainclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpcgc300_mainclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_jpcgc300_mainclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_jpcgc300_mainclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_jpcgc300_mainclk_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_venc_bus_ {}
- #define _DIVIDE_CLOCK_clk_venc_bus_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_venc_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_venc_bus_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_venc_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_venc_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_venc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_venc_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_venc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_venc_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_venc_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_vencbrg_mainclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vencbrg_mainclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_vencbrg_mainclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_vencbrg_mainclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vencbrg_mainclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_vencbrg_mainclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_vencbrg_mainclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_vencbrg_mainclk_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_venc_bclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_bclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_venc_bclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_venc_bclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_bclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_venc_bclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_venc_bclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_venc_bclk_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_venc_bclk_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_bclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_venc_bclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_venc_bclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_venc_bclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_venc_cclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_cclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_venc_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_venc_cclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_cclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_venc_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_venc_cclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_venc_cclk_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_venc_cclk_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_cclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_venc_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_venc_cclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_venc_cclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_venc_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_venc_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_venc_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_venc_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_venc_apb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_venc_apb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_ddrpll_div2_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div2_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_ddrpll_div2_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_ddrpll_div2_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div2_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_ddrpll_div2_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_ddrpll_div2_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div2_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_ddrpll_div2_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div2_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3); \
- _ezchip_macro_read_value_ |= (div&0x3); \
- MA_OUTW(clk_ddrpll_div2_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_ddrpll_div2_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div2_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x3;\
- }
- #define _ENABLE_CLOCK_clk_ddrpll_div4_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div4_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_ddrpll_div4_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_ddrpll_div4_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div4_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_ddrpll_div4_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_ddrpll_div4_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div4_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_ddrpll_div4_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div4_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3); \
- _ezchip_macro_read_value_ |= (div&0x3); \
- MA_OUTW(clk_ddrpll_div4_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_ddrpll_div4_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div4_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x3;\
- }
- #define _ENABLE_CLOCK_clk_ddrpll_div8_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div8_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_ddrpll_div8_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_ddrpll_div8_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div8_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_ddrpll_div8_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_ddrpll_div8_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div8_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_ddrpll_div8_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div8_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3); \
- _ezchip_macro_read_value_ |= (div&0x3); \
- MA_OUTW(clk_ddrpll_div8_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_ddrpll_div8_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div8_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x3;\
- }
- #define _ENABLE_CLOCK_clk_ddrosc_div2_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrosc_div2_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_ddrosc_div2_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_ddrosc_div2_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrosc_div2_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_ddrosc_div2_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_ddrosc_div2_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_ddrosc_div2_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_ddrosc_div2_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrosc_div2_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3); \
- _ezchip_macro_read_value_ |= (div&0x3); \
- MA_OUTW(clk_ddrosc_div2_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_ddrosc_div2_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_ddrosc_div2_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x3;\
- }
- #define _ENABLE_CLOCK_clk_ddrc0_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_ddrc0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_ddrc0_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_ddrc0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_ddrc0_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrosc_div2_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
- MA_OUTW(clk_ddrc0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div2_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
- MA_OUTW(clk_ddrc0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div4_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
- MA_OUTW(clk_ddrc0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div8_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x3&0x3)<<24; \
- MA_OUTW(clk_ddrc0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_SOURCE_STATUS_clk_ddrc0_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR) >> 24; \
- _ezchip_macro_read_value_ &= 0x3;\
- }
- #define _ENABLE_CLOCK_clk_ddrc1_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_ddrc1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_ddrc1_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_ddrc1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_ddrc1_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrosc_div2_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
- MA_OUTW(clk_ddrc1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div2_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
- MA_OUTW(clk_ddrc1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div4_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
- MA_OUTW(clk_ddrc1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div8_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x3&0x3)<<24; \
- MA_OUTW(clk_ddrc1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_SOURCE_STATUS_clk_ddrc1_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR) >> 24; \
- _ezchip_macro_read_value_ &= 0x3;\
- }
- #define _ENABLE_CLOCK_clk_ddrphy_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrphy_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_ddrphy_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_ddrphy_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrphy_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_ddrphy_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_ddrphy_apb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_ddrphy_apb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_noc_rob_ {}
- #define _DIVIDE_CLOCK_clk_noc_rob_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_noc_rob_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_noc_rob_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_noc_rob_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_noc_rob_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_noc_cog_ {}
- #define _DIVIDE_CLOCK_clk_noc_cog_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_noc_cog_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_noc_cog_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_noc_cog_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_noc_cog_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_nne_ahb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_nne_ahb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_nne_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_nne_ahb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_nne_ahb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_nne_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_nne_ahb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_nne_ahb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_nnebus_src1_ {}
- #define _DIVIDE_CLOCK_clk_nnebus_src1_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_nnebus_src1_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x7); \
- _ezchip_macro_read_value_ |= (div&0x7); \
- MA_OUTW(clk_nnebus_src1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_nnebus_src1_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_nnebus_src1_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x7;\
- }
- #define _ENABLE_CLOCK_clk_nne_bus_ {}
- #define _SWITCH_CLOCK_clk_nne_bus_SOURCE_clk_cpu_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_nne_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<24); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<24; \
- MA_OUTW(clk_nne_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_nne_bus_SOURCE_clk_nnebus_src1_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_nne_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<24); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<24; \
- MA_OUTW(clk_nne_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_SOURCE_STATUS_clk_nne_bus_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_nne_bus_ctrl_REG_ADDR) >> 24; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_nne_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_nne_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_nne_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_nne_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_nne_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_nne_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_nne_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_nne_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_nnenoc_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_nnenoc_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_nnenoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_nnenoc_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_nnenoc_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_nnenoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_nnenoc_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_nnenoc_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_dlaslv_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dlaslv_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_dlaslv_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_dlaslv_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dlaslv_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_dlaslv_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_dlaslv_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_dlaslv_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_dspx2c_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dspx2c_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_dspx2c_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_dspx2c_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dspx2c_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_dspx2c_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_dspx2c_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_dspx2c_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_hifi4_src_ {}
- #define _DIVIDE_CLOCK_clk_hifi4_src_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4_src_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x7); \
- _ezchip_macro_read_value_ |= (div&0x7); \
- MA_OUTW(clk_hifi4_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_hifi4_src_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_hifi4_src_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x7;\
- }
- #define _ENABLE_CLOCK_clk_hifi4_corefree_ {}
- #define _DIVIDE_CLOCK_clk_hifi4_corefree_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4_corefree_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_hifi4_corefree_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_hifi4_corefree_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_hifi4_corefree_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_hifi4_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_hifi4_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_hifi4_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_hifi4_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_hifi4_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_hifi4_core_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_hifi4_bus_ {}
- #define _DIVIDE_CLOCK_clk_hifi4_bus_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_hifi4_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_hifi4_bus_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_hifi4_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_hifi4_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_hifi4_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_hifi4_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_hifi4_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_hifi4_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_hifi4_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_hifi4noc_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4noc_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_hifi4noc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_hifi4noc_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4noc_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_hifi4noc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_hifi4noc_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_hifi4noc_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_sgdma1p_bus_ {}
- #define _DIVIDE_CLOCK_clk_sgdma1p_bus_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_sgdma1p_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_sgdma1p_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_sgdma1p_bus_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_sgdma1p_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_sgdma1p_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_sgdma1p_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_sgdma1p_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_sgdma1p_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_sgdma1p_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_sgdma1p_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_sgdma1p_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_sgdma1p_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_dma1p_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dma1p_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_dma1p_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_dma1p_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dma1p_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_dma1p_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_dma1p_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_dma1p_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_x2c_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_x2c_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_x2c_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_x2c_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_x2c_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_x2c_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_x2c_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_x2c_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_x2c_axi_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_x2c_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_x2c_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_x2c_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_x2c_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_usb_bus_ {}
- #define _DIVIDE_CLOCK_clk_usb_bus_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_usb_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_usb_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_usb_bus_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_usb_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_usb_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_usb_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_usb_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_usb_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_usb_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_usb_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_usb_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_usb_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_usbnoc_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbnoc_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_usbnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_usbnoc_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbnoc_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_usbnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_usbnoc_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_usbnoc_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_usbphy_rootdiv_ {}
- #define _DIVIDE_CLOCK_clk_usbphy_rootdiv_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_rootdiv_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x7); \
- _ezchip_macro_read_value_ |= (div&0x7); \
- MA_OUTW(clk_usbphy_rootdiv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_usbphy_rootdiv_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_usbphy_rootdiv_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x7;\
- }
- #define _ENABLE_CLOCK_clk_usbphy_125m_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_125m_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_usbphy_125m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_usbphy_125m_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_125m_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_usbphy_125m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_usbphy_125m_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_usbphy_125m_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_usbphy_125m_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_125m_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_usbphy_125m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_usbphy_125m_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_usbphy_125m_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_usbphy_plldiv25m_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_plldiv25m_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_usbphy_plldiv25m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_usbphy_plldiv25m_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_plldiv25m_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_usbphy_plldiv25m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_usbphy_plldiv25m_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_usbphy_plldiv25m_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_usbphy_plldiv25m_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_plldiv25m_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3F); \
- _ezchip_macro_read_value_ |= (div&0x3F); \
- MA_OUTW(clk_usbphy_plldiv25m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_usbphy_plldiv25m_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_usbphy_plldiv25m_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x3f;\
- }
- #define _ENABLE_CLOCK_clk_usbphy_25m_ {}
- #define _SWITCH_CLOCK_clk_usbphy_25m_SOURCE_clk_osc_sys_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_25m_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<24); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<24; \
- MA_OUTW(clk_usbphy_25m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_usbphy_25m_SOURCE_clk_usbphy_plldiv25m_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_25m_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<24); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<24; \
- MA_OUTW(clk_usbphy_25m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_SOURCE_STATUS_clk_usbphy_25m_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_usbphy_25m_ctrl_REG_ADDR) >> 24; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_audio_div_ {}
- #define _DIVIDE_CLOCK_clk_audio_div_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_div_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3FFFF); \
- _ezchip_macro_read_value_ |= (div&0x3FFFF); \
- MA_OUTW(clk_audio_div_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_audio_div_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_audio_div_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x3ffff;\
- }
- #define _ENABLE_CLOCK_clk_audio_src_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_src_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_audio_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_audio_src_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_src_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_audio_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_audio_src_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_audio_src_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_audio_12288_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_12288_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_audio_12288_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_audio_12288_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_12288_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_audio_12288_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_audio_12288_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_audio_12288_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_vin_src_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_src_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_vin_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_vin_src_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_src_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_vin_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_vin_src_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_vin_src_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_vin_src_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_src_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x7); \
- _ezchip_macro_read_value_ |= (div&0x7); \
- MA_OUTW(clk_vin_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_vin_src_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_vin_src_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x7;\
- }
- #define _ENABLE_CLOCK_clk_isp0_bus_ {}
- #define _DIVIDE_CLOCK_clk_isp0_bus_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp0_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_isp0_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_isp0_bus_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_isp0_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_isp0_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp0_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_isp0_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_isp0_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp0_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_isp0_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_isp0_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_isp0_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_isp0noc_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp0noc_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_isp0noc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_isp0noc_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp0noc_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_isp0noc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_isp0noc_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_isp0noc_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_ispslv_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ispslv_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_ispslv_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_ispslv_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ispslv_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_ispslv_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_ispslv_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_ispslv_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_isp1_bus_ {}
- #define _DIVIDE_CLOCK_clk_isp1_bus_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp1_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_isp1_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_isp1_bus_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_isp1_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_isp1_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp1_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_isp1_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_isp1_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp1_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_isp1_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_isp1_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_isp1_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_isp1noc_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp1noc_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_isp1noc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_isp1noc_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp1noc_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_isp1noc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_isp1noc_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_isp1noc_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_vin_bus_ {}
- #define _DIVIDE_CLOCK_clk_vin_bus_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_vin_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_vin_bus_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_vin_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_vin_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_vin_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_vin_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_vin_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_vin_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_vin_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_vinnoc_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vinnoc_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_vinnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_vinnoc_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vinnoc_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_vinnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_vinnoc_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_vinnoc_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_vout_src_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vout_src_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_vout_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_vout_src_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vout_src_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_vout_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_vout_src_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_vout_src_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_vout_src_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vout_src_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x7); \
- _ezchip_macro_read_value_ |= (div&0x7); \
- MA_OUTW(clk_vout_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_vout_src_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_vout_src_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x7;\
- }
- #define _ENABLE_CLOCK_clk_dispbus_src_ {}
- #define _DIVIDE_CLOCK_clk_dispbus_src_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dispbus_src_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x7); \
- _ezchip_macro_read_value_ |= (div&0x7); \
- MA_OUTW(clk_dispbus_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_dispbus_src_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_dispbus_src_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x7;\
- }
- #define _ENABLE_CLOCK_clk_disp_bus_ {}
- #define _DIVIDE_CLOCK_clk_disp_bus_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_disp_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x7); \
- _ezchip_macro_read_value_ |= (div&0x7); \
- MA_OUTW(clk_disp_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_disp_bus_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_disp_bus_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x7;\
- }
- #define _ENABLE_CLOCK_clk_disp_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_disp_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_disp_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_disp_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_disp_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_disp_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_disp_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_disp_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_dispnoc_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dispnoc_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_dispnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_dispnoc_axi_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_dispnoc_axi_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_dispnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_dispnoc_axi_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_dispnoc_axi_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_sdio0_ahb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio0_ahb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_sdio0_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_sdio0_ahb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio0_ahb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_sdio0_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_sdio0_ahb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_sdio0_ahb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_sdio0_cclkint_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_sdio0_cclkint_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_sdio0_cclkint_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_sdio0_cclkint_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_sdio0_cclkint_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_sdio0_cclkint_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1F); \
- _ezchip_macro_read_value_ |= (div&0x1F); \
- MA_OUTW(clk_sdio0_cclkint_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_sdio0_cclkint_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x1f;\
- }
- #define _ENABLE_CLOCK_clk_sdio0_cclkint_inv_ {}
- #define _SET_CLOCK_clk_sdio0_cclkint_inv_POLARITY_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_inv_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<30); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<30; \
- MA_OUTW(clk_sdio0_cclkint_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _UNSET_CLOCK_clk_sdio0_cclkint_inv_POLARITY_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_inv_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<30); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<30; \
- MA_OUTW(clk_sdio0_cclkint_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_POLARITY_STATUS_clk_sdio0_cclkint_inv_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_inv_ctrl_REG_ADDR) >> 30; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_sdio1_ahb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio1_ahb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_sdio1_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_sdio1_ahb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio1_ahb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_sdio1_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_sdio1_ahb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_sdio1_ahb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_sdio1_cclkint_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_sdio1_cclkint_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_sdio1_cclkint_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_sdio1_cclkint_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_sdio1_cclkint_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_sdio1_cclkint_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1F); \
- _ezchip_macro_read_value_ |= (div&0x1F); \
- MA_OUTW(clk_sdio1_cclkint_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_sdio1_cclkint_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x1f;\
- }
- #define _ENABLE_CLOCK_clk_sdio1_cclkint_inv_ {}
- #define _SET_CLOCK_clk_sdio1_cclkint_inv_POLARITY_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_inv_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<30); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<30; \
- MA_OUTW(clk_sdio1_cclkint_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _UNSET_CLOCK_clk_sdio1_cclkint_inv_POLARITY_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_inv_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<30); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<30; \
- MA_OUTW(clk_sdio1_cclkint_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_POLARITY_STATUS_clk_sdio1_cclkint_inv_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_inv_ctrl_REG_ADDR) >> 30; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_gmac_ahb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_ahb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_gmac_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_gmac_ahb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_ahb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_gmac_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_gmac_ahb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_gmac_ahb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_gmac_root_div_ {}
- #define _DIVIDE_CLOCK_clk_gmac_root_div_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_root_div_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_gmac_root_div_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_gmac_root_div_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_gmac_root_div_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_gmac_ptp_refclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_ptp_refclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_gmac_ptp_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_gmac_ptp_refclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_ptp_refclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_gmac_ptp_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_gmac_ptp_refclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_gmac_ptp_refclk_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_gmac_ptp_refclk_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_ptp_refclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1F); \
- _ezchip_macro_read_value_ |= (div&0x1F); \
- MA_OUTW(clk_gmac_ptp_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_gmac_ptp_refclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_gmac_ptp_refclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x1f;\
- }
- #define _ENABLE_CLOCK_clk_gmac_gtxclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_gtxclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_gmac_gtxclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_gmac_gtxclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_gtxclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_gmac_gtxclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_gmac_gtxclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_gmac_gtxclk_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_gmac_gtxclk_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_gtxclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xFF); \
- _ezchip_macro_read_value_ |= (div&0xFF); \
- MA_OUTW(clk_gmac_gtxclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_gmac_gtxclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_gmac_gtxclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xff;\
- }
- #define _ENABLE_CLOCK_clk_gmac_rmii_txclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_txclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_gmac_rmii_txclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_gmac_rmii_txclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_txclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_gmac_rmii_txclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_gmac_rmii_txclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_txclk_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_gmac_rmii_txclk_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_txclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_gmac_rmii_txclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_gmac_rmii_txclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_txclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_gmac_rmii_rxclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_gmac_rmii_rxclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_gmac_rmii_rxclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_gmac_rmii_rxclk_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0xF); \
- _ezchip_macro_read_value_ |= (div&0xF); \
- MA_OUTW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_gmac_rmii_rxclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0xf;\
- }
- #define _ENABLE_CLOCK_clk_gmac_tx_ {}
- #define _SWITCH_CLOCK_clk_gmac_tx_SOURCE_clk_gmac_gtxclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tx_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
- MA_OUTW(clk_gmac_tx_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_gmac_tx_SOURCE_clk_gmac_mii_txclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tx_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
- MA_OUTW(clk_gmac_tx_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_gmac_tx_SOURCE_clk_gmac_rmii_txclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tx_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3<<24); \
- _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
- MA_OUTW(clk_gmac_tx_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_SOURCE_STATUS_clk_gmac_tx_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_gmac_tx_ctrl_REG_ADDR) >> 24; \
- _ezchip_macro_read_value_ &= 0x3;\
- }
- #define _ENABLE_CLOCK_clk_gmac_tx_inv_ {}
- #define _SET_CLOCK_clk_gmac_tx_inv_POLARITY_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tx_inv_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<30); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<30; \
- MA_OUTW(clk_gmac_tx_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _UNSET_CLOCK_clk_gmac_tx_inv_POLARITY_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tx_inv_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<30); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<30; \
- MA_OUTW(clk_gmac_tx_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_POLARITY_STATUS_clk_gmac_tx_inv_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_gmac_tx_inv_ctrl_REG_ADDR) >> 30; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_gmac_rx_pre_ {}
- #define _SWITCH_CLOCK_clk_gmac_rx_pre_SOURCE_clk_gmac_gr_mii_rxclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rx_pre_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<24); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<24; \
- MA_OUTW(clk_gmac_rx_pre_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _SWITCH_CLOCK_clk_gmac_rx_pre_SOURCE_clk_gmac_rmii_rxclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rx_pre_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<24); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<24; \
- MA_OUTW(clk_gmac_rx_pre_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_SOURCE_STATUS_clk_gmac_rx_pre_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_gmac_rx_pre_ctrl_REG_ADDR) >> 24; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_gmac_rx_inv_ {}
- #define _SET_CLOCK_clk_gmac_rx_inv_POLARITY_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rx_inv_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<30); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<30; \
- MA_OUTW(clk_gmac_rx_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _UNSET_CLOCK_clk_gmac_rx_inv_POLARITY_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rx_inv_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<30); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<30; \
- MA_OUTW(clk_gmac_rx_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_POLARITY_STATUS_clk_gmac_rx_inv_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_gmac_rx_inv_ctrl_REG_ADDR) >> 30; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_gmac_rmii_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_gmac_rmii_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_gmac_rmii_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_gmac_rmii_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_gmac_rmii_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_gmac_tophyref_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tophyref_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_gmac_tophyref_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_gmac_tophyref_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tophyref_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_gmac_tophyref_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_gmac_tophyref_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_gmac_tophyref_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_gmac_tophyref_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tophyref_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x7F); \
- _ezchip_macro_read_value_ |= (div&0x7F); \
- MA_OUTW(clk_gmac_tophyref_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_gmac_tophyref_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_gmac_tophyref_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x7f;\
- }
- #define _ENABLE_CLOCK_clk_spi2ahb_ahb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_ahb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_spi2ahb_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_spi2ahb_ahb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_ahb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_spi2ahb_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_spi2ahb_ahb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_ahb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_spi2ahb_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_spi2ahb_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_spi2ahb_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_spi2ahb_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_spi2ahb_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_core_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_spi2ahb_core_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1F); \
- _ezchip_macro_read_value_ |= (div&0x1F); \
- MA_OUTW(clk_spi2ahb_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_spi2ahb_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x1f;\
- }
- #define _ENABLE_CLOCK_clk_ezmaster_ahb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ezmaster_ahb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_ezmaster_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_ezmaster_ahb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_ezmaster_ahb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_ezmaster_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_ezmaster_ahb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_ezmaster_ahb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_e24_ahb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_e24_ahb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_e24_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_e24_ahb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_e24_ahb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_e24_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_e24_ahb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_e24_ahb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_e24rtc_toggle_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_e24rtc_toggle_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_e24rtc_toggle_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_e24rtc_toggle_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_e24rtc_toggle_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_e24rtc_toggle_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_e24rtc_toggle_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_e24rtc_toggle_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_qspi_ahb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_qspi_ahb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_qspi_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_qspi_ahb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_qspi_ahb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_qspi_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_qspi_ahb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_qspi_ahb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_qspi_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_qspi_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_qspi_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_qspi_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_qspi_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_qspi_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_qspi_apb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_qspi_apb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_qspi_refclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_qspi_refclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_qspi_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_qspi_refclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_qspi_refclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_qspi_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_qspi_refclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_qspi_refclk_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_qspi_refclk_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_qspi_refclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1F); \
- _ezchip_macro_read_value_ |= (div&0x1F); \
- MA_OUTW(clk_qspi_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_qspi_refclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_qspi_refclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x1f;\
- }
- #define _ENABLE_CLOCK_clk_sec_ahb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_sec_ahb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_sec_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_sec_ahb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_sec_ahb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_sec_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_sec_ahb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_sec_ahb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_aes_clk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_aes_clk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_aes_clk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_aes_clk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_aes_clk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_aes_clk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_aes_clk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_aes_clk_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_sha_clk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_sha_clk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_sha_clk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_sha_clk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_sha_clk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_sha_clk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_sha_clk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_sha_clk_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_pka_clk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_pka_clk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_pka_clk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_pka_clk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_pka_clk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_pka_clk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_pka_clk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_pka_clk_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_trng_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_trng_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_trng_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_trng_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_trng_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_trng_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_trng_apb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_trng_apb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_otp_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_otp_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_otp_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_otp_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_otp_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_otp_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_otp_apb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_otp_apb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_uart0_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart0_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_uart0_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_uart0_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart0_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_uart0_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_uart0_apb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_uart0_apb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_uart0_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart0_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_uart0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_uart0_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart0_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_uart0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_uart0_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_uart0_core_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_uart0_core_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart0_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3F); \
- _ezchip_macro_read_value_ |= (div&0x3F); \
- MA_OUTW(clk_uart0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_uart0_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_uart0_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x3f;\
- }
- #define _ENABLE_CLOCK_clk_uart1_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart1_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_uart1_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_uart1_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart1_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_uart1_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_uart1_apb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_uart1_apb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_uart1_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart1_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_uart1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_uart1_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart1_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_uart1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_uart1_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_uart1_core_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_uart1_core_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart1_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3F); \
- _ezchip_macro_read_value_ |= (div&0x3F); \
- MA_OUTW(clk_uart1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_uart1_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_uart1_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x3f;\
- }
- #define _ENABLE_CLOCK_clk_spi0_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi0_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_spi0_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_spi0_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi0_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_spi0_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_spi0_apb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_spi0_apb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_spi0_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi0_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_spi0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_spi0_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi0_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_spi0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_spi0_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_spi0_core_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_spi0_core_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi0_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3F); \
- _ezchip_macro_read_value_ |= (div&0x3F); \
- MA_OUTW(clk_spi0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_spi0_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_spi0_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x3f;\
- }
- #define _ENABLE_CLOCK_clk_spi1_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi1_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_spi1_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_spi1_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi1_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_spi1_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_spi1_apb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_spi1_apb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_spi1_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi1_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_spi1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_spi1_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi1_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_spi1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_spi1_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_spi1_core_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_spi1_core_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi1_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3F); \
- _ezchip_macro_read_value_ |= (div&0x3F); \
- MA_OUTW(clk_spi1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_spi1_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_spi1_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x3f;\
- }
- #define _ENABLE_CLOCK_clk_i2c0_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c0_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_i2c0_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_i2c0_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c0_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_i2c0_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_i2c0_apb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_i2c0_apb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_i2c0_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c0_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_i2c0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_i2c0_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c0_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_i2c0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_i2c0_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_i2c0_core_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_i2c0_core_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c0_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3F); \
- _ezchip_macro_read_value_ |= (div&0x3F); \
- MA_OUTW(clk_i2c0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_i2c0_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_i2c0_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x3f;\
- }
- #define _ENABLE_CLOCK_clk_i2c1_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c1_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_i2c1_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_i2c1_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c1_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_i2c1_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_i2c1_apb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_i2c1_apb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_i2c1_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c1_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_i2c1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_i2c1_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c1_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_i2c1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_i2c1_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_i2c1_core_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_i2c1_core_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c1_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3F); \
- _ezchip_macro_read_value_ |= (div&0x3F); \
- MA_OUTW(clk_i2c1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_i2c1_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_i2c1_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x3f;\
- }
- #define _ENABLE_CLOCK_clk_gpio_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gpio_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_gpio_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_gpio_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_gpio_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_gpio_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_gpio_apb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_gpio_apb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_uart2_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart2_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_uart2_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_uart2_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart2_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_uart2_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_uart2_apb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_uart2_apb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_uart2_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart2_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_uart2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_uart2_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart2_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_uart2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_uart2_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_uart2_core_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_uart2_core_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart2_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3F); \
- _ezchip_macro_read_value_ |= (div&0x3F); \
- MA_OUTW(clk_uart2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_uart2_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_uart2_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x3f;\
- }
- #define _ENABLE_CLOCK_clk_uart3_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart3_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_uart3_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_uart3_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart3_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_uart3_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_uart3_apb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_uart3_apb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_uart3_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart3_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_uart3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_uart3_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart3_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_uart3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_uart3_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_uart3_core_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_uart3_core_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart3_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3F); \
- _ezchip_macro_read_value_ |= (div&0x3F); \
- MA_OUTW(clk_uart3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_uart3_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_uart3_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x3f;\
- }
- #define _ENABLE_CLOCK_clk_spi2_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_spi2_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_spi2_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_spi2_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_spi2_apb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_spi2_apb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_spi2_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_spi2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_spi2_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_spi2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_spi2_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_spi2_core_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_spi2_core_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3F); \
- _ezchip_macro_read_value_ |= (div&0x3F); \
- MA_OUTW(clk_spi2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_spi2_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_spi2_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x3f;\
- }
- #define _ENABLE_CLOCK_clk_spi3_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi3_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_spi3_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_spi3_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi3_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_spi3_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_spi3_apb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_spi3_apb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_spi3_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi3_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_spi3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_spi3_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi3_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_spi3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_spi3_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_spi3_core_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_spi3_core_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi3_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3F); \
- _ezchip_macro_read_value_ |= (div&0x3F); \
- MA_OUTW(clk_spi3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_spi3_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_spi3_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x3f;\
- }
- #define _ENABLE_CLOCK_clk_i2c2_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c2_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_i2c2_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_i2c2_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c2_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_i2c2_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_i2c2_apb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_i2c2_apb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_i2c2_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c2_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_i2c2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_i2c2_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c2_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_i2c2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_i2c2_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_i2c2_core_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_i2c2_core_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c2_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3F); \
- _ezchip_macro_read_value_ |= (div&0x3F); \
- MA_OUTW(clk_i2c2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_i2c2_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_i2c2_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x3f;\
- }
- #define _ENABLE_CLOCK_clk_i2c3_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c3_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_i2c3_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_i2c3_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c3_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_i2c3_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_i2c3_apb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_i2c3_apb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_i2c3_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c3_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_i2c3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_i2c3_core_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c3_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_i2c3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_i2c3_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_i2c3_core_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_i2c3_core_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c3_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3F); \
- _ezchip_macro_read_value_ |= (div&0x3F); \
- MA_OUTW(clk_i2c3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_i2c3_core_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_i2c3_core_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x3f;\
- }
- #define _ENABLE_CLOCK_clk_wdtimer_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_wdtimer_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_wdtimer_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_wdtimer_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_wdtimer_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_wdtimer_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_wdtimer_apb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_wdtimer_apb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_wdt_coreclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_wdt_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_wdt_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_wdt_coreclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_wdt_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_wdt_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_wdt_coreclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_wdt_coreclk_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_wdt_coreclk_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_wdt_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3F); \
- _ezchip_macro_read_value_ |= (div&0x3F); \
- MA_OUTW(clk_wdt_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_wdt_coreclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_wdt_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x3f;\
- }
- #define _ENABLE_CLOCK_clk_timer0_coreclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer0_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_timer0_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_timer0_coreclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer0_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_timer0_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_timer0_coreclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_timer0_coreclk_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_timer0_coreclk_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer0_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3F); \
- _ezchip_macro_read_value_ |= (div&0x3F); \
- MA_OUTW(clk_timer0_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_timer0_coreclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_timer0_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x3f;\
- }
- #define _ENABLE_CLOCK_clk_timer1_coreclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer1_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_timer1_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_timer1_coreclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer1_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_timer1_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_timer1_coreclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_timer1_coreclk_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_timer1_coreclk_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer1_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3F); \
- _ezchip_macro_read_value_ |= (div&0x3F); \
- MA_OUTW(clk_timer1_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_timer1_coreclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_timer1_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x3f;\
- }
- #define _ENABLE_CLOCK_clk_timer2_coreclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer2_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_timer2_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_timer2_coreclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer2_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_timer2_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_timer2_coreclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_timer2_coreclk_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_timer2_coreclk_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer2_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3F); \
- _ezchip_macro_read_value_ |= (div&0x3F); \
- MA_OUTW(clk_timer2_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_timer2_coreclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_timer2_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x3f;\
- }
- #define _ENABLE_CLOCK_clk_timer3_coreclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer3_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_timer3_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_timer3_coreclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer3_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_timer3_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_timer3_coreclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_timer3_coreclk_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_timer3_coreclk_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer3_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3F); \
- _ezchip_macro_read_value_ |= (div&0x3F); \
- MA_OUTW(clk_timer3_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_timer3_coreclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_timer3_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x3f;\
- }
- #define _ENABLE_CLOCK_clk_timer4_coreclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer4_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_timer4_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_timer4_coreclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer4_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_timer4_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_timer4_coreclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_timer4_coreclk_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_timer4_coreclk_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer4_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3F); \
- _ezchip_macro_read_value_ |= (div&0x3F); \
- MA_OUTW(clk_timer4_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_timer4_coreclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_timer4_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x3f;\
- }
- #define _ENABLE_CLOCK_clk_timer5_coreclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer5_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_timer5_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_timer5_coreclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer5_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_timer5_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_timer5_coreclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_timer5_coreclk_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_timer5_coreclk_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer5_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3F); \
- _ezchip_macro_read_value_ |= (div&0x3F); \
- MA_OUTW(clk_timer5_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_timer5_coreclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_timer5_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x3f;\
- }
- #define _ENABLE_CLOCK_clk_timer6_coreclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer6_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_timer6_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_timer6_coreclk_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer6_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_timer6_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_timer6_coreclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_timer6_coreclk_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_timer6_coreclk_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer6_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x3F); \
- _ezchip_macro_read_value_ |= (div&0x3F); \
- MA_OUTW(clk_timer6_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_timer6_coreclk_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_timer6_coreclk_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x3f;\
- }
- #define _ENABLE_CLOCK_clk_vp6intc_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6intc_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_vp6intc_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_vp6intc_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6intc_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_vp6intc_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_vp6intc_apb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_vp6intc_apb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_pwm_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_pwm_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_pwm_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_pwm_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_pwm_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_pwm_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_pwm_apb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_pwm_apb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_msi_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_msi_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_msi_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_msi_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_msi_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_msi_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_msi_apb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_msi_apb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_temp_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_temp_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_temp_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_temp_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_temp_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_temp_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_temp_apb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_temp_apb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _ENABLE_CLOCK_clk_temp_sense_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_temp_sense_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_temp_sense_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_temp_sense_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_temp_sense_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_temp_sense_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_temp_sense_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_temp_sense_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #define _DIVIDE_CLOCK_clk_temp_sense_(div) { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_temp_sense_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1F); \
- _ezchip_macro_read_value_ |= (div&0x1F); \
- MA_OUTW(clk_temp_sense_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_DIVIDE_STATUS_clk_temp_sense_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_temp_sense_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= 0x1f;\
- }
- #define _ENABLE_CLOCK_clk_syserr_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_syserr_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
- MA_OUTW(clk_syserr_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _DISABLE_CLOCK_clk_syserr_apb_ { \
- uint32_t _ezchip_macro_read_value_=MA_INW(clk_syserr_apb_ctrl_REG_ADDR); \
- _ezchip_macro_read_value_ &= ~(0x1<<31); \
- _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
- MA_OUTW(clk_syserr_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
- }
- #define _GET_CLOCK_ENABLE_STATUS_clk_syserr_apb_(_ezchip_macro_read_value_) { \
- _ezchip_macro_read_value_=MA_INW(clk_syserr_apb_ctrl_REG_ADDR) >> 31; \
- _ezchip_macro_read_value_ &= 0x1;\
- }
- #endif //_CLKGEN_MACRO_H_
|