bootloader-BEAGLEV-210525.asm 237 KB

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  1. bootloader-BEAGLEV-210525.elf: file format elf64-littleriscv
  2. Disassembly of section .init:
  3. 0000000018000000 <_start>:
  4. .section .init
  5. .globl _start
  6. _start:
  7. la t0, trap_entry
  8. 18000000: 00000297 auipc t0,0x0
  9. 18000004: 44428293 addi t0,t0,1092 # 18000444 <trap_entry>
  10. csrw mtvec, t0
  11. 18000008: 30529073 csrw mtvec,t0
  12. csrwi mstatus, 0
  13. 1800000c: 30005073 csrwi mstatus,0
  14. csrwi mie, 0
  15. 18000010: 30405073 csrwi mie,0
  16. // Allocate 4 KiB stack for each hart
  17. csrr t0, mhartid
  18. 18000014: f14022f3 csrr t0,mhartid
  19. slli t0, t0, 12
  20. 18000018: 02b2 slli t0,t0,0xc
  21. la sp, _sp
  22. 1800001a: 00012117 auipc sp,0x12
  23. 1800001e: 14610113 addi sp,sp,326 # 18012160 <_sp>
  24. sub sp, sp, t0
  25. 18000022: 40510133 sub sp,sp,t0
  26. li a1, NONSMP_HART;
  27. 18000026: 4581 li a1,0
  28. csrr a0, mhartid;
  29. 18000028: f1402573 csrr a0,mhartid
  30. bne a0, a1, .LbootOtherHart //other hart
  31. 1800002c: 04b51c63 bne a0,a1,18000084 <_start+0x84>
  32. // Load data section
  33. la t0, _data_lma
  34. 18000030: 00002297 auipc t0,0x2
  35. 18000034: 4d028293 addi t0,t0,1232 # 18002500 <_data_lma>
  36. la t1, _data
  37. 18000038: 00010317 auipc t1,0x10
  38. 1800003c: fc830313 addi t1,t1,-56 # 18010000 <uart_id>
  39. beq t0, t1, 2f
  40. 18000040: 02628063 beq t0,t1,18000060 <_start+0x60>
  41. la t2, _edata
  42. 18000044: 00010397 auipc t2,0x10
  43. 18000048: fbc38393 addi t2,t2,-68 # 18010000 <uart_id>
  44. bgeu t1, t2, 2f
  45. 1800004c: 00737a63 bgeu t1,t2,18000060 <_start+0x60>
  46. 1:
  47. ld t3, 0(t0)
  48. 18000050: 0002be03 ld t3,0(t0)
  49. sd t3, 0(t1)
  50. 18000054: 01c33023 sd t3,0(t1)
  51. addi t0, t0, 8
  52. 18000058: 02a1 addi t0,t0,8
  53. addi t1, t1, 8
  54. 1800005a: 0321 addi t1,t1,8
  55. bltu t1, t2, 1b
  56. 1800005c: fe736ae3 bltu t1,t2,18000050 <_start+0x50>
  57. 2:
  58. /* Clear bss section */
  59. la t1, _bss_start
  60. 18000060: 00010317 auipc t1,0x10
  61. 18000064: fa030313 addi t1,t1,-96 # 18010000 <uart_id>
  62. la t2, _bss_end
  63. 18000068: 00010397 auipc t2,0x10
  64. 1800006c: 09838393 addi t2,t2,152 # 18010100 <_bss_end>
  65. bgeu t1, t2, 4f
  66. 18000070: 00737763 bgeu t1,t2,1800007e <_start+0x7e>
  67. 3:
  68. sd x0, 0(t1)
  69. 18000074: 00033023 sd zero,0(t1)
  70. addi t1, t1, 8
  71. 18000078: 0321 addi t1,t1,8
  72. blt t1, t2, 3b
  73. 1800007a: fe734de3 blt t1,t2,18000074 <_start+0x74>
  74. 4:
  75. /*only hart 0*/
  76. call BootMain
  77. 1800007e: 1de000ef jal ra,1800025c <BootMain>
  78. j .enter_uboot
  79. 18000082: a881 j 180000d2 <.enter_uboot>
  80. .LbootOtherHart:
  81. li s1, CLINT_CTRL_ADDR
  82. 18000084: 020004b7 lui s1,0x2000
  83. csrr a0, mhartid
  84. 18000088: f1402573 csrr a0,mhartid
  85. slli s2, a0, 2
  86. 1800008c: 00251913 slli s2,a0,0x2
  87. add s2, s2, s1
  88. 18000090: 9926 add s2,s2,s1
  89. sw zero, 0(s2)
  90. 18000092: 00092023 sw zero,0(s2)
  91. fence
  92. 18000096: 0ff0000f fence
  93. csrw mip, 0
  94. 1800009a: 34405073 csrwi mip,0
  95. # core 1 jumps to main_other_hart
  96. # Set MSIE bit to receive IPI
  97. li a2, MIP_MSIP
  98. 1800009e: 4621 li a2,8
  99. csrw mie, a2
  100. 180000a0: 30461073 csrw mie,a2
  101. .LwaitOtherHart:
  102. # Wait for an IPI to signal that its safe to boot
  103. // call second_hart
  104. wfi
  105. 180000a4: 10500073 wfi
  106. # Only start if MIP_MSIP is set
  107. csrr a2, mip
  108. 180000a8: 34402673 csrr a2,mip
  109. andi a2, a2, MIP_MSIP
  110. 180000ac: 8a21 andi a2,a2,8
  111. beqz a2, .LwaitOtherHart
  112. 180000ae: da7d beqz a2,180000a4 <_start+0xa4>
  113. li s1, CLINT_CTRL_ADDR
  114. 180000b0: 020004b7 lui s1,0x2000
  115. csrr a0, mhartid
  116. 180000b4: f1402573 csrr a0,mhartid
  117. slli s2, a0, 2
  118. 180000b8: 00251913 slli s2,a0,0x2
  119. add s2, s2, s1
  120. 180000bc: 9926 add s2,s2,s1
  121. sw zero, 0(s2)
  122. 180000be: 00092023 sw zero,0(s2)
  123. fence
  124. 180000c2: 0ff0000f fence
  125. csrw mip, 0
  126. 180000c6: 34405073 csrwi mip,0
  127. li a2, NUM_CORES
  128. 180000ca: 4609 li a2,2
  129. bltu a0, a2, .enter_uboot
  130. 180000cc: 00c56363 bltu a0,a2,180000d2 <.enter_uboot>
  131. j .LwaitOtherHart
  132. 180000d0: bfd1 j 180000a4 <_start+0xa4>
  133. 00000000180000d2 <.enter_uboot>:
  134. .enter_uboot:
  135. li t0, DEFAULT_DDR_ADDR
  136. 180000d2: 180802b7 lui t0,0x18080
  137. csrr a0, mhartid
  138. 180000d6: f1402573 csrr a0,mhartid
  139. la a1, 0
  140. 180000da: 0000059b sext.w a1,zero
  141. jr t0
  142. 180000de: 8282 jr t0
  143. Disassembly of section .text:
  144. 0000000018000100 <load_data.constprop.0>:
  145. *des_addr: store the data read from flash
  146. *page_offset:Offset of data stored in flash
  147. *mode:flash work mode
  148. */
  149. static int load_data(struct spi_flash* spi_flash,unsigned int des_addr,unsigned int page_offset,int mode)
  150. 18000100: 710d addi sp,sp,-352
  151. 18000102: f656 sd s5,296(sp)
  152. u8 *addr;
  153. int ret;
  154. int i;
  155. u32 offset;
  156. pageSize = spi_flash->page_size;
  157. 18000104: 01452a83 lw s5,20(a0)
  158. addr = (u8 *)des_addr;
  159. offset = page_offset*pageSize;
  160. /*read first page,get the file size*/
  161. ret = spi_flash->read(spi_flash,offset,pageSize,dataBuf,mode);
  162. 18000108: 711c ld a5,32(a0)
  163. static int load_data(struct spi_flash* spi_flash,unsigned int des_addr,unsigned int page_offset,int mode)
  164. 1800010a: f25a sd s6,288(sp)
  165. ret = spi_flash->read(spi_flash,offset,pageSize,dataBuf,mode);
  166. 1800010c: 8b2e mv s6,a1
  167. static int load_data(struct spi_flash* spi_flash,unsigned int des_addr,unsigned int page_offset,int mode)
  168. 1800010e: e2ca sd s2,320(sp)
  169. 18000110: fa52 sd s4,304(sp)
  170. 18000112: ee86 sd ra,344(sp)
  171. 18000114: eaa2 sd s0,336(sp)
  172. 18000116: e6a6 sd s1,328(sp)
  173. 18000118: fe4e sd s3,312(sp)
  174. 1800011a: ee5e sd s7,280(sp)
  175. 1800011c: ea62 sd s8,272(sp)
  176. offset = page_offset*pageSize;
  177. 1800011e: 008a959b slliw a1,s5,0x8
  178. ret = spi_flash->read(spi_flash,offset,pageSize,dataBuf,mode);
  179. 18000122: 875a mv a4,s6
  180. 18000124: 0034 addi a3,sp,8
  181. 18000126: 8656 mv a2,s5
  182. static int load_data(struct spi_flash* spi_flash,unsigned int des_addr,unsigned int page_offset,int mode)
  183. 18000128: 892a mv s2,a0
  184. offset = page_offset*pageSize;
  185. 1800012a: 8a2e mv s4,a1
  186. ret = spi_flash->read(spi_flash,offset,pageSize,dataBuf,mode);
  187. 1800012c: 9782 jalr a5
  188. if(ret != 0)
  189. 1800012e: e951 bnez a0,180001c2 <load_data.constprop.0+0xc2>
  190. printk("read fail#\r\n");
  191. return -1;
  192. }
  193. /*calculate file size*/
  194. fileSize = (dataBuf[3] << 24) | (dataBuf[2] << 16) | (dataBuf[1] << 8) | (dataBuf[0]) ;
  195. 18000130: 49a2 lw s3,8(sp)
  196. if(fileSize == 0)
  197. 18000132: 08098663 beqz s3,180001be <load_data.constprop.0+0xbe>
  198. return -1;
  199. endPage = ((fileSize + 255) >> 8);//page align
  200. 18000136: 0ff9899b addiw s3,s3,255
  201. 1800013a: 8baa mv s7,a0
  202. 1800013c: 0089d41b srliw s0,s3,0x8
  203. /*copy the first page data*/
  204. sys_memcpy(addr, &dataBuf[4], SPIBOOT_LOAD_ADDR_OFFSET);
  205. 18000140: 0fc00613 li a2,252
  206. 18000144: 006c addi a1,sp,12
  207. 18000146: 18080537 lui a0,0x18080
  208. endPage = ((fileSize + 255) >> 8);//page align
  209. 1800014a: 0089d99b srliw s3,s3,0x8
  210. sys_memcpy(addr, &dataBuf[4], SPIBOOT_LOAD_ADDR_OFFSET);
  211. 1800014e: 0c1000ef jal ra,18000a0e <sys_memcpy>
  212. offset += pageSize;
  213. 18000152: 015a0a3b addw s4,s4,s5
  214. addr += SPIBOOT_LOAD_ADDR_OFFSET;
  215. /*read Remaining pages data*/
  216. for(i=1; i<=endPage; i++)
  217. 18000156: c439 beqz s0,180001a4 <load_data.constprop.0+0xa4>
  218. {
  219. ret = spi_flash->read(spi_flash,offset,pageSize, addr, mode);
  220. 18000158: e7f807b7 lui a5,0xe7f80
  221. addr += SPIBOOT_LOAD_ADDR_OFFSET;
  222. 1800015c: 18080437 lui s0,0x18080
  223. ret = spi_flash->read(spi_flash,offset,pageSize, addr, mode);
  224. 18000160: f047879b addiw a5,a5,-252
  225. {
  226. printk("read fail##\r\n");
  227. return -1;
  228. }
  229. offset += pageSize;
  230. addr +=pageSize;
  231. 18000164: 020a9c13 slli s8,s5,0x20
  232. 18000168: 2985 addiw s3,s3,1
  233. for(i=1; i<=endPage; i++)
  234. 1800016a: 4485 li s1,1
  235. addr += SPIBOOT_LOAD_ADDR_OFFSET;
  236. 1800016c: 0fc40413 addi s0,s0,252 # 180800fc <_sp+0x6df9c>
  237. ret = spi_flash->read(spi_flash,offset,pageSize, addr, mode);
  238. 18000170: 00fa0a3b addw s4,s4,a5
  239. addr +=pageSize;
  240. 18000174: 020c5c13 srli s8,s8,0x20
  241. 18000178: a021 j 18000180 <load_data.constprop.0+0x80>
  242. 1800017a: 9462 add s0,s0,s8
  243. for(i=1; i<=endPage; i++)
  244. 1800017c: 02998463 beq s3,s1,180001a4 <load_data.constprop.0+0xa4>
  245. ret = spi_flash->read(spi_flash,offset,pageSize, addr, mode);
  246. 18000180: 02093783 ld a5,32(s2)
  247. 18000184: 86a2 mv a3,s0
  248. 18000186: 008a05bb addw a1,s4,s0
  249. 1800018a: 875a mv a4,s6
  250. 1800018c: 8656 mv a2,s5
  251. 1800018e: 854a mv a0,s2
  252. 18000190: 9782 jalr a5
  253. for(i=1; i<=endPage; i++)
  254. 18000192: 2485 addiw s1,s1,1
  255. if(ret != 0)
  256. 18000194: d17d beqz a0,1800017a <load_data.constprop.0+0x7a>
  257. printk("read fail##\r\n");
  258. 18000196: 00002517 auipc a0,0x2
  259. 1800019a: 1ba50513 addi a0,a0,442 # 18002350 <memset+0xce>
  260. 1800019e: 04d000ef jal ra,180009ea <printk>
  261. return -1;
  262. 180001a2: 5bfd li s7,-1
  263. }
  264. return 0;
  265. }
  266. 180001a4: 60f6 ld ra,344(sp)
  267. 180001a6: 6456 ld s0,336(sp)
  268. 180001a8: 64b6 ld s1,328(sp)
  269. 180001aa: 6916 ld s2,320(sp)
  270. 180001ac: 79f2 ld s3,312(sp)
  271. 180001ae: 7a52 ld s4,304(sp)
  272. 180001b0: 7ab2 ld s5,296(sp)
  273. 180001b2: 7b12 ld s6,288(sp)
  274. 180001b4: 6c52 ld s8,272(sp)
  275. 180001b6: 855e mv a0,s7
  276. 180001b8: 6bf2 ld s7,280(sp)
  277. 180001ba: 6135 addi sp,sp,352
  278. 180001bc: 8082 ret
  279. return -1;
  280. 180001be: 5bfd li s7,-1
  281. 180001c0: b7d5 j 180001a4 <load_data.constprop.0+0xa4>
  282. printk("read fail#\r\n");
  283. 180001c2: 00002517 auipc a0,0x2
  284. 180001c6: 17e50513 addi a0,a0,382 # 18002340 <memset+0xbe>
  285. 180001ca: 021000ef jal ra,180009ea <printk>
  286. return -1;
  287. 180001ce: 5bfd li s7,-1
  288. 180001d0: bfd1 j 180001a4 <load_data.constprop.0+0xa4>
  289. 00000000180001d2 <start2run32>:
  290. (( STARTRUNNING )(start))(0);
  291. 180001d2: 02051793 slli a5,a0,0x20
  292. 180001d6: 9381 srli a5,a5,0x20
  293. 180001d8: 4501 li a0,0
  294. 180001da: 8782 jr a5
  295. 00000000180001dc <load_and_run_ddr>:
  296. void load_and_run_ddr(struct spi_flash* spi_flash,int mode)
  297. {
  298. 180001dc: 1141 addi sp,sp,-16
  299. 180001de: e022 sd s0,0(sp)
  300. 180001e0: e406 sd ra,8(sp)
  301. unsigned int addr;
  302. int ret;
  303. addr = DEFAULT_DDR_ADDR;
  304. ret = load_data(spi_flash,addr,DEFAULT_DDR_OFFSET,mode);
  305. 180001e2: f1fff0ef jal ra,18000100 <load_data.constprop.0>
  306. 180001e6: 842a mv s0,a0
  307. printk("\r\ncurrent_hartid:%s\r\n",current_hartid());
  308. 180001e8: f14025f3 csrr a1,mhartid
  309. 180001ec: 00002517 auipc a0,0x2
  310. 180001f0: 17450513 addi a0,a0,372 # 18002360 <memset+0xde>
  311. 180001f4: 2581 sext.w a1,a1
  312. 180001f6: 7f4000ef jal ra,180009ea <printk>
  313. printk("\r\nbootloader version:%s\r\n",VERSION);
  314. 180001fa: 00002597 auipc a1,0x2
  315. 180001fe: 17e58593 addi a1,a1,382 # 18002378 <memset+0xf6>
  316. 18000202: 00002517 auipc a0,0x2
  317. 18000206: 18650513 addi a0,a0,390 # 18002388 <memset+0x106>
  318. 1800020a: 7e0000ef jal ra,180009ea <printk>
  319. if(!ret)
  320. 1800020e: e819 bnez s0,18000224 <load_and_run_ddr+0x48>
  321. #endif
  322. #ifndef writel
  323. static inline void writel(u32 val, volatile void *addr)
  324. {
  325. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  326. 18000210: 020007b7 lui a5,0x2000
  327. 18000214: 4705 li a4,1
  328. 18000216: 0791 addi a5,a5,4
  329. 18000218: c398 sw a4,0(a5)
  330. (( STARTRUNNING )(start))(0);
  331. 1800021a: 4501 li a0,0
  332. 1800021c: 180807b7 lui a5,0x18080
  333. 18000220: 9782 jalr a5
  334. }
  335. else
  336. printk("\nload ddr bin fail.\n");
  337. /*never run to here*/
  338. while(1);
  339. 18000222: a001 j 18000222 <load_and_run_ddr+0x46>
  340. printk("\nload ddr bin fail.\n");
  341. 18000224: 00002517 auipc a0,0x2
  342. 18000228: 18450513 addi a0,a0,388 # 180023a8 <memset+0x126>
  343. 1800022c: 7be000ef jal ra,180009ea <printk>
  344. 18000230: bfcd j 18000222 <load_and_run_ddr+0x46>
  345. 0000000018000232 <boot_from_spi>:
  346. }
  347. void boot_from_spi(int mode)
  348. {
  349. 18000232: 1141 addi sp,sp,-16
  350. struct spi_flash* spi_flash;
  351. int ret;
  352. u32 *addr;
  353. u32 val;
  354. cadence_qspi_init(0, mode);
  355. 18000234: 85aa mv a1,a0
  356. {
  357. 18000236: e022 sd s0,0(sp)
  358. 18000238: 842a mv s0,a0
  359. cadence_qspi_init(0, mode);
  360. 1800023a: 4501 li a0,0
  361. {
  362. 1800023c: e406 sd ra,8(sp)
  363. cadence_qspi_init(0, mode);
  364. 1800023e: 545000ef jal ra,18000f82 <cadence_qspi_init>
  365. spi_flash = spi_flash_probe(0, 0, 31250000, 0, (u32)SPI_DATAMODE_8);
  366. 18000242: 01dcd637 lui a2,0x1dcd
  367. 18000246: 4581 li a1,0
  368. 18000248: 4721 li a4,8
  369. 1800024a: 4681 li a3,0
  370. 1800024c: 65060613 addi a2,a2,1616 # 1dcd650 <__stack_size+0x1dcce50>
  371. 18000250: 4501 li a0,0
  372. 18000252: 173000ef jal ra,18000bc4 <spi_flash_probe>
  373. /*init ddr*/
  374. load_and_run_ddr(spi_flash,mode);
  375. 18000256: 85a2 mv a1,s0
  376. 18000258: f85ff0ef jal ra,180001dc <load_and_run_ddr>
  377. 000000001800025c <BootMain>:
  378. }
  379. static void chip_clk_init()
  380. {
  381. _SWITCH_CLOCK_clk_cpundbus_root_SOURCE_clk_pll0_out_;
  382. 1800025c: 118006b7 lui a3,0x11800
  383. 18000260: 4298 lw a4,0(a3)
  384. 18000262: fd000637 lui a2,0xfd000
  385. 18000266: 167d addi a2,a2,-1
  386. 18000268: 2701 sext.w a4,a4
  387. 1800026a: 010005b7 lui a1,0x1000
  388. 1800026e: 8f71 and a4,a4,a2
  389. // _SWITCH_CLOCK_clk_nne_bus_SOURCE_clk_cpu_axi_;
  390. }
  391. /*only hartid 0 call this function*/
  392. void BootMain(void)
  393. {
  394. 18000270: 1141 addi sp,sp,-16
  395. _SWITCH_CLOCK_clk_cpundbus_root_SOURCE_clk_pll0_out_;
  396. 18000272: 8f4d or a4,a4,a1
  397. {
  398. 18000274: e406 sd ra,8(sp)
  399. _SWITCH_CLOCK_clk_cpundbus_root_SOURCE_clk_pll0_out_;
  400. 18000276: 2701 sext.w a4,a4
  401. 18000278: c298 sw a4,0(a3)
  402. _SWITCH_CLOCK_clk_dla_root_SOURCE_clk_pll1_out_;
  403. 1800027a: 42d8 lw a4,4(a3)
  404. _SWITCH_CLOCK_clk_dsp_root_SOURCE_clk_pll2_out_;
  405. 1800027c: 030007b7 lui a5,0x3000
  406. _SWITCH_CLOCK_clk_dla_root_SOURCE_clk_pll1_out_;
  407. 18000280: 2701 sext.w a4,a4
  408. 18000282: 8f71 and a4,a4,a2
  409. 18000284: 8f4d or a4,a4,a1
  410. 18000286: 2701 sext.w a4,a4
  411. 18000288: c2d8 sw a4,4(a3)
  412. _SWITCH_CLOCK_clk_dsp_root_SOURCE_clk_pll2_out_;
  413. 1800028a: 4698 lw a4,8(a3)
  414. 1800028c: 2701 sext.w a4,a4
  415. 1800028e: 8f71 and a4,a4,a2
  416. 18000290: 8f5d or a4,a4,a5
  417. 18000292: c698 sw a4,8(a3)
  418. _SWITCH_CLOCK_clk_perh0_root_SOURCE_clk_pll0_out_;
  419. 18000294: 4a9c lw a5,16(a3)
  420. 18000296: ff000737 lui a4,0xff000
  421. 1800029a: 177d addi a4,a4,-1
  422. 1800029c: 2781 sext.w a5,a5
  423. 1800029e: 8ff9 and a5,a5,a4
  424. 180002a0: 8fcd or a5,a5,a1
  425. 180002a2: 2781 sext.w a5,a5
  426. 180002a4: ca9c sw a5,16(a3)
  427. /*switch to pll mode*/
  428. chip_clk_init();
  429. //for illegal instruction exception
  430. _SET_SYSCON_REG_register50_SCFG_funcshare_pad_ctrl_18(0x00c000c0);
  431. 180002a6: 11858637 lui a2,0x11858
  432. 180002aa: 0c862783 lw a5,200(a2) # 118580c8 <__stack_size+0x118578c8>
  433. _CLEAR_RESET_rstgen_rstn_usbnoc_axi_;
  434. 180002ae: 118406b7 lui a3,0x11840
  435. _SET_SYSCON_REG_register50_SCFG_funcshare_pad_ctrl_18(0x00c000c0);
  436. 180002b2: 00c007b7 lui a5,0xc00
  437. 180002b6: 0c078793 addi a5,a5,192 # c000c0 <__stack_size+0xbff8c0>
  438. 180002ba: 0cf62423 sw a5,200(a2)
  439. _CLEAR_RESET_rstgen_rstn_usbnoc_axi_;
  440. 180002be: 42dc lw a5,4(a3)
  441. 180002c0: 11840737 lui a4,0x11840
  442. 180002c4: 2781 sext.w a5,a5
  443. 180002c6: fbf7f793 andi a5,a5,-65
  444. 180002ca: c2dc sw a5,4(a3)
  445. 180002cc: 4b5c lw a5,20(a4)
  446. 180002ce: 0407f793 andi a5,a5,64
  447. 180002d2: dfed beqz a5,180002cc <BootMain+0x70>
  448. _CLEAR_RESET_rstgen_rstn_hifi4noc_axi_;
  449. 180002d4: 435c lw a5,4(a4)
  450. 180002d6: 118406b7 lui a3,0x11840
  451. 180002da: 2781 sext.w a5,a5
  452. 180002dc: 9bed andi a5,a5,-5
  453. 180002de: c35c sw a5,4(a4)
  454. 180002e0: 4adc lw a5,20(a3)
  455. 180002e2: 8b91 andi a5,a5,4
  456. 180002e4: dff5 beqz a5,180002e0 <BootMain+0x84>
  457. _ENABLE_CLOCK_clk_x2c_axi_;
  458. 180002e6: 11800637 lui a2,0x11800
  459. 180002ea: 15c62783 lw a5,348(a2) # 1180015c <__stack_size+0x117ff95c>
  460. 180002ee: 800005b7 lui a1,0x80000
  461. _CLEAR_RESET_rstgen_rstn_x2c_axi_;
  462. 180002f2: 11840737 lui a4,0x11840
  463. _ENABLE_CLOCK_clk_x2c_axi_;
  464. 180002f6: 8fcd or a5,a5,a1
  465. 180002f8: 14f62e23 sw a5,348(a2)
  466. _CLEAR_RESET_rstgen_rstn_x2c_axi_;
  467. 180002fc: 42dc lw a5,4(a3)
  468. 180002fe: 2781 sext.w a5,a5
  469. 18000300: dff7f793 andi a5,a5,-513
  470. 18000304: c2dc sw a5,4(a3)
  471. 18000306: 4b5c lw a5,20(a4)
  472. 18000308: 2007f793 andi a5,a5,512
  473. 1800030c: dfed beqz a5,18000306 <BootMain+0xaa>
  474. _CLEAR_RESET_rstgen_rstn_dspx2c_axi_;
  475. 1800030e: 435c lw a5,4(a4)
  476. 18000310: 76f1 lui a3,0xffffc
  477. 18000312: 16fd addi a3,a3,-1
  478. 18000314: 2781 sext.w a5,a5
  479. 18000316: 8ff5 and a5,a5,a3
  480. 18000318: c35c sw a5,4(a4)
  481. 1800031a: 118406b7 lui a3,0x11840
  482. 1800031e: 6711 lui a4,0x4
  483. 18000320: 4adc lw a5,20(a3)
  484. 18000322: 2781 sext.w a5,a5
  485. 18000324: 8ff9 and a5,a5,a4
  486. 18000326: 2781 sext.w a5,a5
  487. 18000328: dfe5 beqz a5,18000320 <BootMain+0xc4>
  488. _CLEAR_RESET_rstgen_rstn_dma1p_axi_;
  489. 1800032a: 42dc lw a5,4(a3)
  490. 1800032c: 11840737 lui a4,0x11840
  491. 18000330: 2781 sext.w a5,a5
  492. 18000332: eff7f793 andi a5,a5,-257
  493. 18000336: c2dc sw a5,4(a3)
  494. 18000338: 4b5c lw a5,20(a4)
  495. 1800033a: 1007f793 andi a5,a5,256
  496. 1800033e: dfed beqz a5,18000338 <BootMain+0xdc>
  497. _ENABLE_CLOCK_clk_msi_apb_;
  498. 18000340: 118006b7 lui a3,0x11800
  499. 18000344: 2d86a783 lw a5,728(a3) # 118002d8 <__stack_size+0x117ffad8>
  500. 18000348: 80000637 lui a2,0x80000
  501. 1800034c: 8fd1 or a5,a5,a2
  502. 1800034e: 2cf6ac23 sw a5,728(a3)
  503. _CLEAR_RESET_rstgen_rstn_msi_apb_;
  504. 18000352: 475c lw a5,12(a4)
  505. 18000354: 7671 lui a2,0xffffc
  506. 18000356: 167d addi a2,a2,-1
  507. 18000358: 2781 sext.w a5,a5
  508. 1800035a: 8ff1 and a5,a5,a2
  509. 1800035c: c75c sw a5,12(a4)
  510. 1800035e: 118406b7 lui a3,0x11840
  511. 18000362: 6711 lui a4,0x4
  512. 18000364: 4edc lw a5,28(a3)
  513. 18000366: 2781 sext.w a5,a5
  514. 18000368: 8ff9 and a5,a5,a4
  515. 1800036a: 2781 sext.w a5,a5
  516. 1800036c: dfe5 beqz a5,18000364 <BootMain+0x108>
  517. _ASSERT_RESET_rstgen_rstn_x2c_axi_;
  518. 1800036e: 42dc lw a5,4(a3)
  519. 18000370: 11840737 lui a4,0x11840
  520. 18000374: 2781 sext.w a5,a5
  521. 18000376: 2007e793 ori a5,a5,512
  522. 1800037a: c2dc sw a5,4(a3)
  523. 1800037c: 4b5c lw a5,20(a4)
  524. 1800037e: 2007f793 andi a5,a5,512
  525. 18000382: ffed bnez a5,1800037c <BootMain+0x120>
  526. _CLEAR_RESET_rstgen_rstn_x2c_axi_;
  527. 18000384: 435c lw a5,4(a4)
  528. 18000386: 118406b7 lui a3,0x11840
  529. 1800038a: 2781 sext.w a5,a5
  530. 1800038c: dff7f793 andi a5,a5,-513
  531. 18000390: c35c sw a5,4(a4)
  532. 18000392: 4adc lw a5,20(a3)
  533. 18000394: 2007f793 andi a5,a5,512
  534. 18000398: dfed beqz a5,18000392 <BootMain+0x136>
  535. //end for illegal instruction exception
  536. _SET_SYSCON_REG_register69_core1_en(1);
  537. 1800039a: 11850637 lui a2,0x11850
  538. 1800039e: 11862703 lw a4,280(a2) # 11850118 <__stack_size+0x1184f918>
  539. _SET_SYSCON_REG_register104_SCFG_io_padshare_sel(6);
  540. 180003a2: 118587b7 lui a5,0x11858
  541. _SET_SYSCON_REG_register32_SCFG_funcshare_pad_ctrl_0(0x00c00000);
  542. 180003a6: 00c006b7 lui a3,0xc00
  543. _SET_SYSCON_REG_register69_core1_en(1);
  544. 180003aa: 2701 sext.w a4,a4
  545. 180003ac: 00176713 ori a4,a4,1
  546. 180003b0: 10e62c23 sw a4,280(a2)
  547. _SET_SYSCON_REG_register104_SCFG_io_padshare_sel(6);
  548. 180003b4: 1a07a703 lw a4,416(a5) # 118581a0 <__stack_size+0x118579a0>
  549. _SET_SYSCON_REG_register33_SCFG_funcshare_pad_ctrl_1(0x00c000c0);
  550. 180003b8: 0c068613 addi a2,a3,192 # c000c0 <__stack_size+0xbff8c0>
  551. _SET_SYSCON_REG_register34_SCFG_funcshare_pad_ctrl_2(0x00c000c0);
  552. _SET_SYSCON_REG_register35_SCFG_funcshare_pad_ctrl_3(0x00c000c0);
  553. _SET_SYSCON_REG_register39_SCFG_funcshare_pad_ctrl_7(0x00c300c3);
  554. _SET_SYSCON_REG_register38_SCFG_funcshare_pad_ctrl_6(0x00c00000);
  555. uart_init(3);
  556. 180003bc: 450d li a0,3
  557. _SET_SYSCON_REG_register104_SCFG_io_padshare_sel(6);
  558. 180003be: 2701 sext.w a4,a4
  559. 180003c0: 9b61 andi a4,a4,-8
  560. 180003c2: 00676713 ori a4,a4,6
  561. 180003c6: 1ae7a023 sw a4,416(a5)
  562. _SET_SYSCON_REG_register32_SCFG_funcshare_pad_ctrl_0(0x00c00000);
  563. 180003ca: 0807a703 lw a4,128(a5)
  564. 180003ce: 08d7a023 sw a3,128(a5)
  565. _SET_SYSCON_REG_register33_SCFG_funcshare_pad_ctrl_1(0x00c000c0);
  566. 180003d2: 0847a703 lw a4,132(a5)
  567. 180003d6: 08c7a223 sw a2,132(a5)
  568. _SET_SYSCON_REG_register34_SCFG_funcshare_pad_ctrl_2(0x00c000c0);
  569. 180003da: 0887a703 lw a4,136(a5)
  570. 180003de: 08c7a423 sw a2,136(a5)
  571. _SET_SYSCON_REG_register35_SCFG_funcshare_pad_ctrl_3(0x00c000c0);
  572. 180003e2: 08c7a703 lw a4,140(a5)
  573. 180003e6: 08c7a623 sw a2,140(a5)
  574. _SET_SYSCON_REG_register39_SCFG_funcshare_pad_ctrl_7(0x00c300c3);
  575. 180003ea: 09c7a703 lw a4,156(a5)
  576. 180003ee: 00c30737 lui a4,0xc30
  577. 180003f2: 0c370713 addi a4,a4,195 # c300c3 <__stack_size+0xc2f8c3>
  578. 180003f6: 08e7ae23 sw a4,156(a5)
  579. _SET_SYSCON_REG_register38_SCFG_funcshare_pad_ctrl_6(0x00c00000);
  580. 180003fa: 0987a703 lw a4,152(a5)
  581. 180003fe: 08d7ac23 sw a3,152(a5)
  582. uart_init(3);
  583. 18000402: 094000ef jal ra,18000496 <uart_init>
  584. 18000406: 180207b7 lui a5,0x18020
  585. 1800040a: 18000737 lui a4,0x18000
  586. 1800040e: 17f1 addi a5,a5,-4
  587. 18000410: c398 sw a4,0(a5)
  588. 18000412: 020007b7 lui a5,0x2000
  589. 18000416: 4705 li a4,1
  590. 18000418: 0791 addi a5,a5,4
  591. 1800041a: c398 sw a4,0(a5)
  592. writel(0x18000000, 0x1801fffc);
  593. writel(0x1, 0x2000004); /*从bootrom中恢复hart1*/
  594. boot_from_spi(1);
  595. 1800041c: 4505 li a0,1
  596. 1800041e: e15ff0ef jal ra,18000232 <boot_from_spi>
  597. 0000000018000422 <handle_trap>:
  598. #define MCAUSE_CAUSE 0x00000000000003FFUL
  599. #endif
  600. uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
  601. {
  602. 18000422: 1141 addi sp,sp,-16
  603. 18000424: e022 sd s0,0(sp)
  604. 18000426: 842e mv s0,a1
  605. }
  606. else {
  607. rlSendString("unhandle trap.\n");
  608. }
  609. #endif
  610. printk("trap mcause:0x%x epc:0x%x\n",mcause,epc);
  611. 18000428: 8622 mv a2,s0
  612. {
  613. 1800042a: 85aa mv a1,a0
  614. printk("trap mcause:0x%x epc:0x%x\n",mcause,epc);
  615. 1800042c: 00002517 auipc a0,0x2
  616. 18000430: f9450513 addi a0,a0,-108 # 180023c0 <memset+0x13e>
  617. {
  618. 18000434: e406 sd ra,8(sp)
  619. printk("trap mcause:0x%x epc:0x%x\n",mcause,epc);
  620. 18000436: 5b4000ef jal ra,180009ea <printk>
  621. return epc;
  622. }
  623. 1800043a: 60a2 ld ra,8(sp)
  624. 1800043c: 8522 mv a0,s0
  625. 1800043e: 6402 ld s0,0(sp)
  626. 18000440: 0141 addi sp,sp,16
  627. 18000442: 8082 ret
  628. 0000000018000444 <trap_entry>:
  629. void trap_entry(void)
  630. {
  631. unsigned long mcause = read_csr(mcause);
  632. 18000444: 342025f3 csrr a1,mcause
  633. unsigned long mepc = read_csr(mepc);
  634. 18000448: 34102673 csrr a2,mepc
  635. printk("trap mcause:0x%x epc:0x%x\n",mcause,epc);
  636. 1800044c: 00002517 auipc a0,0x2
  637. 18000450: f7450513 addi a0,a0,-140 # 180023c0 <memset+0x13e>
  638. 18000454: ab59 j 180009ea <printk>
  639. 0000000018000456 <__serial_tstc>:
  640. };
  641. static unsigned int serial_in(int offset)
  642. {
  643. offset <<= 2;
  644. return readl((volatile void *)(uart_base[uart_id] + offset));
  645. 18000456: 00010797 auipc a5,0x10
  646. 1800045a: baa7e783 lwu a5,-1110(a5) # 18010000 <uart_id>
  647. 1800045e: 00379713 slli a4,a5,0x3
  648. 18000462: 00002797 auipc a5,0x2
  649. 18000466: fe678793 addi a5,a5,-26 # 18002448 <uart_base>
  650. 1800046a: 97ba add a5,a5,a4
  651. 1800046c: 6388 ld a0,0(a5)
  652. 1800046e: 0551 addi a0,a0,20
  653. #ifndef readl
  654. static inline u32 readl(volatile void *addr)
  655. {
  656. u32 val;
  657. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  658. 18000470: 4108 lw a0,0(a0)
  659. }
  660. int __serial_tstc()
  661. {
  662. return ((serial_in(REG_LSR)) & (1 << 0));
  663. }
  664. 18000472: 8905 andi a0,a0,1
  665. 18000474: 8082 ret
  666. 0000000018000476 <serial_tstc>:
  667. 18000476: 00010797 auipc a5,0x10
  668. 1800047a: b8a7e783 lwu a5,-1142(a5) # 18010000 <uart_id>
  669. 1800047e: 00379713 slli a4,a5,0x3
  670. 18000482: 00002797 auipc a5,0x2
  671. 18000486: fc678793 addi a5,a5,-58 # 18002448 <uart_base>
  672. 1800048a: 97ba add a5,a5,a4
  673. 1800048c: 6388 ld a0,0(a5)
  674. 1800048e: 0551 addi a0,a0,20
  675. 18000490: 4108 lw a0,0(a0)
  676. 18000492: 8905 andi a0,a0,1
  677. 18000494: 8082 ret
  678. 0000000018000496 <uart_init>:
  679. return readl((volatile void *)(uart_base[uart_id] + offset));
  680. 18000496: 02051793 slli a5,a0,0x20
  681. 1800049a: 01d7d713 srli a4,a5,0x1d
  682. 1800049e: 00002797 auipc a5,0x2
  683. 180004a2: faa78793 addi a5,a5,-86 # 18002448 <uart_base>
  684. 180004a6: 97ba add a5,a5,a4
  685. 180004a8: 639c ld a5,0(a5)
  686. default:
  687. return;
  688. }
  689. #endif
  690. uart_id = id;
  691. 180004aa: 00010717 auipc a4,0x10
  692. 180004ae: b4a72b23 sw a0,-1194(a4) # 18010000 <uart_id>
  693. return readl((volatile void *)(uart_base[uart_id] + offset));
  694. 180004b2: 00c78713 addi a4,a5,12
  695. 180004b6: 4314 lw a3,0(a4)
  696. divisor = (UART_CLK / UART_BUADRATE_32MCLK_115200) >> 4;
  697. lcr_cache = serial_in(REG_LCR);
  698. serial_out(REG_LCR, (LCR_DLAB | lcr_cache));
  699. 180004b8: 0ff6f613 zext.b a2,a3
  700. writel(value, (volatile void *)(uart_base[uart_id] + offset));
  701. 180004bc: 08066613 ori a2,a2,128
  702. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  703. 180004c0: c310 sw a2,0(a4)
  704. 180004c2: 03600613 li a2,54
  705. 180004c6: c390 sw a2,0(a5)
  706. 180004c8: 4601 li a2,0
  707. 180004ca: 00478593 addi a1,a5,4
  708. 180004ce: c190 sw a2,0(a1)
  709. 180004d0: 0ff6f693 zext.b a3,a3
  710. 180004d4: c314 sw a3,0(a4)
  711. 180004d6: 468d li a3,3
  712. 180004d8: c314 sw a3,0(a4)
  713. 180004da: 01078713 addi a4,a5,16
  714. 180004de: c310 sw a2,0(a4)
  715. 180004e0: 08f00713 li a4,143
  716. 180004e4: 07a1 addi a5,a5,8
  717. 180004e6: c398 sw a4,0(a5)
  718. 180004e8: c190 sw a2,0(a1)
  719. * Clear TX and RX FIFO
  720. */
  721. serial_out(REG_FCR, (FCR_FIFO | FCR_MODE1 | /*FCR_FIFO_1*/FCR_FIFO_8 | FCR_RCVRCLR | FCR_XMITCLR));
  722. serial_out(REG_IER, 0);//dis the ser interrupt
  723. }
  724. 180004ea: 8082 ret
  725. 00000000180004ec <_putc>:
  726. return readl((volatile void *)(uart_base[uart_id] + offset));
  727. 180004ec: 00010797 auipc a5,0x10
  728. 180004f0: b147e783 lwu a5,-1260(a5) # 18010000 <uart_id>
  729. 180004f4: 00379713 slli a4,a5,0x3
  730. 180004f8: 00002797 auipc a5,0x2
  731. 180004fc: f5078793 addi a5,a5,-176 # 18002448 <uart_base>
  732. 18000500: 97ba add a5,a5,a4
  733. 18000502: 6394 ld a3,0(a5)
  734. 18000504: 01468713 addi a4,a3,20
  735. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  736. 18000508: 431c lw a5,0(a4)
  737. int _putc(char c) {
  738. do
  739. {}while((serial_in(REG_LSR) & LSR_THRE) == 0);
  740. 1800050a: 0207f793 andi a5,a5,32
  741. 1800050e: dfed beqz a5,18000508 <_putc+0x1c>
  742. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  743. 18000510: c288 sw a0,0(a3)
  744. serial_out(REG_THR, c);
  745. return 0;
  746. }
  747. 18000512: 4501 li a0,0
  748. 18000514: 8082 ret
  749. 0000000018000516 <rlSendString>:
  750. void rlSendString(char *s)
  751. {
  752. while (*s){
  753. 18000516: 00054683 lbu a3,0(a0)
  754. 1800051a: ca85 beqz a3,1800054a <rlSendString+0x34>
  755. return readl((volatile void *)(uart_base[uart_id] + offset));
  756. 1800051c: 00010797 auipc a5,0x10
  757. 18000520: ae47e783 lwu a5,-1308(a5) # 18010000 <uart_id>
  758. 18000524: 00379713 slli a4,a5,0x3
  759. 18000528: 00002797 auipc a5,0x2
  760. 1800052c: f2078793 addi a5,a5,-224 # 18002448 <uart_base>
  761. 18000530: 97ba add a5,a5,a4
  762. 18000532: 6390 ld a2,0(a5)
  763. 18000534: 01460713 addi a4,a2,20
  764. _putc(*s++);
  765. 18000538: 0505 addi a0,a0,1
  766. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  767. 1800053a: 431c lw a5,0(a4)
  768. {}while((serial_in(REG_LSR) & LSR_THRE) == 0);
  769. 1800053c: 0207f793 andi a5,a5,32
  770. 18000540: dfed beqz a5,1800053a <rlSendString+0x24>
  771. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  772. 18000542: c214 sw a3,0(a2)
  773. while (*s){
  774. 18000544: 00054683 lbu a3,0(a0)
  775. 18000548: fae5 bnez a3,18000538 <rlSendString+0x22>
  776. }
  777. }
  778. 1800054a: 8082 ret
  779. 000000001800054c <CtrlBreak>:
  780. return readl((volatile void *)(uart_base[uart_id] + offset));
  781. 1800054c: 00010797 auipc a5,0x10
  782. 18000550: ab47e783 lwu a5,-1356(a5) # 18010000 <uart_id>
  783. 18000554: 00379713 slli a4,a5,0x3
  784. 18000558: 00002797 auipc a5,0x2
  785. 1800055c: ef078793 addi a5,a5,-272 # 18002448 <uart_base>
  786. 18000560: 97ba add a5,a5,a4
  787. 18000562: 6394 ld a3,0(a5)
  788. {
  789. int retflag;
  790. do{
  791. retflag = serial_getc();
  792. if( retflag == 0x03 ){
  793. 18000564: 460d li a2,3
  794. return readl((volatile void *)(uart_base[uart_id] + offset));
  795. 18000566: 01468713 addi a4,a3,20
  796. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  797. 1800056a: 431c lw a5,0(a4)
  798. return retflag;
  799. }
  800. int serial_getc()
  801. {
  802. /* Wait here until the the FIFO is not full */
  803. while (!(serial_in(REG_LSR) & (1 << 0))){};
  804. 1800056c: 8b85 andi a5,a5,1
  805. 1800056e: dff5 beqz a5,1800056a <CtrlBreak+0x1e>
  806. 18000570: 4288 lw a0,0(a3)
  807. return serial_in(REG_RDR);
  808. 18000572: 2501 sext.w a0,a0
  809. if( retflag == 0x03 ){
  810. 18000574: 00c50363 beq a0,a2,1800057a <CtrlBreak+0x2e>
  811. }while( retflag );
  812. 18000578: f96d bnez a0,1800056a <CtrlBreak+0x1e>
  813. }
  814. 1800057a: 8082 ret
  815. 000000001800057c <serial_getc>:
  816. return readl((volatile void *)(uart_base[uart_id] + offset));
  817. 1800057c: 00010797 auipc a5,0x10
  818. 18000580: a847e783 lwu a5,-1404(a5) # 18010000 <uart_id>
  819. 18000584: 00379713 slli a4,a5,0x3
  820. 18000588: 00002797 auipc a5,0x2
  821. 1800058c: ec078793 addi a5,a5,-320 # 18002448 <uart_base>
  822. 18000590: 97ba add a5,a5,a4
  823. 18000592: 6388 ld a0,0(a5)
  824. 18000594: 01450713 addi a4,a0,20
  825. 18000598: 431c lw a5,0(a4)
  826. while (!(serial_in(REG_LSR) & (1 << 0))){};
  827. 1800059a: 8b85 andi a5,a5,1
  828. 1800059c: dff5 beqz a5,18000598 <serial_getc+0x1c>
  829. 1800059e: 4108 lw a0,0(a0)
  830. }
  831. 180005a0: 2501 sext.w a0,a0
  832. 180005a2: 8082 ret
  833. 00000000180005a4 <serial_gets>:
  834. return readl((volatile void *)(uart_base[uart_id] + offset));
  835. 180005a4: 00010f17 auipc t5,0x10
  836. 180005a8: a5cf0f13 addi t5,t5,-1444 # 18010000 <uart_id>
  837. 180005ac: 000f6783 lwu a5,0(t5)
  838. 180005b0: 00002e97 auipc t4,0x2
  839. 180005b4: e98e8e93 addi t4,t4,-360 # 18002448 <uart_base>
  840. unsigned char c;
  841. unsigned char *pstrorg;
  842. pstrorg = (unsigned char *) pstr;
  843. while ((c = serial_getc()) != '\r')
  844. 180005b8: 88aa mv a7,a0
  845. return readl((volatile void *)(uart_base[uart_id] + offset));
  846. 180005ba: 078e slli a5,a5,0x3
  847. 180005bc: 97f6 add a5,a5,t4
  848. 180005be: 638c ld a1,0(a5)
  849. while ((c = serial_getc()) != '\r')
  850. 180005c0: 4335 li t1,13
  851. {
  852. if (c == '\b'){
  853. 180005c2: 4e21 li t3,8
  854. 180005c4: 01458713 addi a4,a1,20 # ffffffff80000014 <_sp+0xffffffff67fedeb4>
  855. 180005c8: 431c lw a5,0(a4)
  856. while (!(serial_in(REG_LSR) & (1 << 0))){};
  857. 180005ca: 8b85 andi a5,a5,1
  858. 180005cc: dff5 beqz a5,180005c8 <serial_gets+0x24>
  859. 180005ce: 4190 lw a2,0(a1)
  860. while ((c = serial_getc()) != '\r')
  861. 180005d0: 0ff67693 zext.b a3,a2
  862. 180005d4: 0006079b sext.w a5,a2
  863. 180005d8: 06668063 beq a3,t1,18000638 <serial_gets+0x94>
  864. if (c == '\b'){
  865. 180005dc: 03c69a63 bne a3,t3,18000610 <serial_gets+0x6c>
  866. if ((int) *pstrorg < (int) *pstr){
  867. 180005e0: 00054603 lbu a2,0(a0)
  868. 180005e4: 0008c783 lbu a5,0(a7)
  869. 180005e8: fef670e3 bgeu a2,a5,180005c8 <serial_gets+0x24>
  870. 180005ec: 02000813 li a6,32
  871. 180005f0: 00002617 auipc a2,0x2
  872. 180005f4: df060613 addi a2,a2,-528 # 180023e0 <memset+0x15e>
  873. _putc(*s++);
  874. 180005f8: 0605 addi a2,a2,1
  875. 180005fa: 431c lw a5,0(a4)
  876. {}while((serial_in(REG_LSR) & LSR_THRE) == 0);
  877. 180005fc: 0207f793 andi a5,a5,32
  878. 18000600: dfed beqz a5,180005fa <serial_gets+0x56>
  879. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  880. 18000602: c194 sw a3,0(a1)
  881. while (*s){
  882. 18000604: 02080863 beqz a6,18000634 <serial_gets+0x90>
  883. 18000608: 86c2 mv a3,a6
  884. 1800060a: 00164803 lbu a6,1(a2)
  885. 1800060e: b7ed j 180005f8 <serial_gets+0x54>
  886. rlSendString("\b \b");
  887. pstr--;
  888. }
  889. }else{
  890. *pstr++ = c;
  891. 18000610: 00f88023 sb a5,0(a7)
  892. return readl((volatile void *)(uart_base[uart_id] + offset));
  893. 18000614: 000f6783 lwu a5,0(t5)
  894. *pstr++ = c;
  895. 18000618: 0885 addi a7,a7,1
  896. return readl((volatile void *)(uart_base[uart_id] + offset));
  897. 1800061a: 078e slli a5,a5,0x3
  898. 1800061c: 97f6 add a5,a5,t4
  899. 1800061e: 638c ld a1,0(a5)
  900. 18000620: 01458713 addi a4,a1,20
  901. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  902. 18000624: 431c lw a5,0(a4)
  903. {}while((serial_in(REG_LSR) & LSR_THRE) == 0);
  904. 18000626: 0207f793 andi a5,a5,32
  905. 1800062a: dfed beqz a5,18000624 <serial_gets+0x80>
  906. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  907. 1800062c: 0ff67613 zext.b a2,a2
  908. 18000630: c190 sw a2,0(a1)
  909. return 0;
  910. 18000632: bf59 j 180005c8 <serial_gets+0x24>
  911. pstr--;
  912. 18000634: 18fd addi a7,a7,-1
  913. 18000636: bf49 j 180005c8 <serial_gets+0x24>
  914. _putc(c);
  915. }
  916. }
  917. *pstr = '\0';
  918. 18000638: 00088023 sb zero,0(a7)
  919. return readl((volatile void *)(uart_base[uart_id] + offset));
  920. 1800063c: 000f6783 lwu a5,0(t5)
  921. writel(value, (volatile void *)(uart_base[uart_id] + offset));
  922. 18000640: 45a9 li a1,10
  923. 18000642: 00002617 auipc a2,0x2
  924. 18000646: da660613 addi a2,a2,-602 # 180023e8 <memset+0x166>
  925. return readl((volatile void *)(uart_base[uart_id] + offset));
  926. 1800064a: 078e slli a5,a5,0x3
  927. 1800064c: 9ebe add t4,t4,a5
  928. 1800064e: 000eb503 ld a0,0(t4)
  929. 18000652: 01450713 addi a4,a0,20
  930. _putc(*s++);
  931. 18000656: 0605 addi a2,a2,1
  932. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  933. 18000658: 431c lw a5,0(a4)
  934. {}while((serial_in(REG_LSR) & LSR_THRE) == 0);
  935. 1800065a: 0207f793 andi a5,a5,32
  936. 1800065e: dfed beqz a5,18000658 <serial_gets+0xb4>
  937. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  938. 18000660: c114 sw a3,0(a0)
  939. while (*s){
  940. 18000662: c589 beqz a1,1800066c <serial_gets+0xc8>
  941. 18000664: 86ae mv a3,a1
  942. 18000666: 00164583 lbu a1,1(a2)
  943. 1800066a: b7f5 j 18000656 <serial_gets+0xb2>
  944. rlSendString("\r\n");
  945. }
  946. 1800066c: 8082 ret
  947. 000000001800066e <_puts>:
  948. 1800066e: 00054683 lbu a3,0(a0)
  949. 18000672: ca85 beqz a3,180006a2 <_puts+0x34>
  950. 18000674: 00010797 auipc a5,0x10
  951. 18000678: 98c7e783 lwu a5,-1652(a5) # 18010000 <uart_id>
  952. 1800067c: 00379713 slli a4,a5,0x3
  953. 18000680: 00002797 auipc a5,0x2
  954. 18000684: dc878793 addi a5,a5,-568 # 18002448 <uart_base>
  955. 18000688: 97ba add a5,a5,a4
  956. 1800068a: 6390 ld a2,0(a5)
  957. 1800068c: 01460713 addi a4,a2,20
  958. 18000690: 0505 addi a0,a0,1
  959. 18000692: 431c lw a5,0(a4)
  960. 18000694: 0207f793 andi a5,a5,32
  961. 18000698: dfed beqz a5,18000692 <_puts+0x24>
  962. 1800069a: c214 sw a3,0(a2)
  963. 1800069c: 00054683 lbu a3,0(a0)
  964. 180006a0: fae5 bnez a3,18000690 <_puts+0x22>
  965. 180006a2: 8082 ret
  966. 00000000180006a4 <print_ubyte_hex>:
  967. return readl((volatile void *)(uart_base[uart_id] + offset));
  968. 180006a4: 00010717 auipc a4,0x10
  969. 180006a8: 95c76703 lwu a4,-1700(a4) # 18010000 <uart_id>
  970. static const char digits[16] = "0123456789ABCDEF";
  971. char tmp[2];
  972. int dig=0;
  973. dig = ((bval&0xf0)>>4);
  974. tmp[0] = digits[dig];
  975. 180006ac: 00002797 auipc a5,0x2
  976. 180006b0: d9c78793 addi a5,a5,-612 # 18002448 <uart_base>
  977. return readl((volatile void *)(uart_base[uart_id] + offset));
  978. 180006b4: 070e slli a4,a4,0x3
  979. 180006b6: 973e add a4,a4,a5
  980. tmp[0] = digits[dig];
  981. 180006b8: 00455613 srli a2,a0,0x4
  982. dig = (bval&0x0f);
  983. tmp[1] = digits[dig];
  984. 180006bc: 893d andi a0,a0,15
  985. tmp[0] = digits[dig];
  986. 180006be: 963e add a2,a2,a5
  987. return readl((volatile void *)(uart_base[uart_id] + offset));
  988. 180006c0: 6314 ld a3,0(a4)
  989. tmp[1] = digits[dig];
  990. 180006c2: 97aa add a5,a5,a0
  991. tmp[0] = digits[dig];
  992. 180006c4: 02064583 lbu a1,32(a2)
  993. tmp[1] = digits[dig];
  994. 180006c8: 0207c603 lbu a2,32(a5)
  995. return readl((volatile void *)(uart_base[uart_id] + offset));
  996. 180006cc: 01468713 addi a4,a3,20
  997. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  998. 180006d0: 431c lw a5,0(a4)
  999. {}while((serial_in(REG_LSR) & LSR_THRE) == 0);
  1000. 180006d2: 0207f793 andi a5,a5,32
  1001. 180006d6: dfed beqz a5,180006d0 <print_ubyte_hex+0x2c>
  1002. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  1003. 180006d8: c28c sw a1,0(a3)
  1004. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  1005. 180006da: 431c lw a5,0(a4)
  1006. 180006dc: 0207f793 andi a5,a5,32
  1007. 180006e0: dfed beqz a5,180006da <print_ubyte_hex+0x36>
  1008. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  1009. 180006e2: c290 sw a2,0(a3)
  1010. _putc(tmp[0]);
  1011. _putc(tmp[1]);
  1012. }
  1013. 180006e4: 8082 ret
  1014. 00000000180006e6 <serial_nowait_getc>:
  1015. return readl((volatile void *)(uart_base[uart_id] + offset));
  1016. 180006e6: 00010797 auipc a5,0x10
  1017. 180006ea: 91a7e783 lwu a5,-1766(a5) # 18010000 <uart_id>
  1018. 180006ee: 00379713 slli a4,a5,0x3
  1019. 180006f2: 00002797 auipc a5,0x2
  1020. 180006f6: d5678793 addi a5,a5,-682 # 18002448 <uart_base>
  1021. 180006fa: 97ba add a5,a5,a4
  1022. 180006fc: 6398 ld a4,0(a5)
  1023. 180006fe: 01470793 addi a5,a4,20
  1024. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  1025. 18000702: 439c lw a5,0(a5)
  1026. int serial_nowait_getc()
  1027. {
  1028. unsigned int status;
  1029. status = serial_in(REG_LSR);
  1030. if (!(status & (1 << 0))) {
  1031. 18000704: 8b85 andi a5,a5,1
  1032. 18000706: 4501 li a0,0
  1033. 18000708: c781 beqz a5,18000710 <serial_nowait_getc+0x2a>
  1034. 1800070a: 4318 lw a4,0(a4)
  1035. status = 0;//NO_POLL_CHAR;
  1036. goto out;
  1037. }
  1038. status = serial_in(REG_RDR);
  1039. out:
  1040. return status;
  1041. 1800070c: 0007051b sext.w a0,a4
  1042. }
  1043. 18000710: 8082 ret
  1044. 0000000018000712 <vnprintf>:
  1045. int vnprintf(char* out, size_t n, const char* s, va_list vl)
  1046. {
  1047. bool format = false;
  1048. bool longarg = false;
  1049. size_t pos = 0;
  1050. for( ; *s; s++)
  1051. 18000712: 00064783 lbu a5,0(a2)
  1052. {
  1053. 18000716: 832a mv t1,a0
  1054. for( ; *s; s++)
  1055. 18000718: 24078c63 beqz a5,18000970 <vnprintf+0x25e>
  1056. {
  1057. 1800071c: 7179 addi sp,sp,-48
  1058. 1800071e: f422 sd s0,40(sp)
  1059. 18000720: f026 sd s1,32(sp)
  1060. 18000722: ec4a sd s2,24(sp)
  1061. 18000724: e84e sd s3,16(sp)
  1062. 18000726: e452 sd s4,8(sp)
  1063. 18000728: e056 sd s5,0(sp)
  1064. size_t pos = 0;
  1065. 1800072a: 4701 li a4,0
  1066. bool longarg = false;
  1067. 1800072c: 4901 li s2,0
  1068. bool format = false;
  1069. 1800072e: 4801 li a6,0
  1070. }
  1071. default:
  1072. break;
  1073. }
  1074. }
  1075. else if(*s == '%')
  1076. 18000730: 02500293 li t0,37
  1077. 18000734: 4fd5 li t6,21
  1078. 18000736: 00002e97 auipc t4,0x2
  1079. 1800073a: cbae8e93 addi t4,t4,-838 # 180023f0 <memset+0x16e>
  1080. for (long nn = num; nn /= 10; digits++)
  1081. 1800073e: 4529 li a0,10
  1082. if (++pos < n) out[pos-1] = '-';
  1083. 18000740: 02d00493 li s1,45
  1084. if (++pos < n) out[pos-1] = (d < 10 ? '0'+d : 'a'+d-10);
  1085. 18000744: 4f25 li t5,9
  1086. for(int i = 2*(longarg ? sizeof(long) : sizeof(int))-1; i >= 0; i--) {
  1087. 18000746: 5e71 li t3,-4
  1088. if (++pos < n) out[pos-1] = 'x';
  1089. 18000748: 07800413 li s0,120
  1090. if (++pos < n) out[pos-1] = '0';
  1091. 1800074c: 03000393 li t2,48
  1092. if(format)
  1093. 18000750: 18080863 beqz a6,180008e0 <vnprintf+0x1ce>
  1094. switch(*s)
  1095. 18000754: f9d7879b addiw a5,a5,-99
  1096. 18000758: 0ff7f793 zext.b a5,a5
  1097. 1800075c: 00ffe863 bltu t6,a5,1800076c <vnprintf+0x5a>
  1098. 18000760: 078a slli a5,a5,0x2
  1099. 18000762: 97f6 add a5,a5,t4
  1100. 18000764: 439c lw a5,0(a5)
  1101. 18000766: 97f6 add a5,a5,t4
  1102. 18000768: 8782 jr a5
  1103. format = true;
  1104. 1800076a: 4805 li a6,1
  1105. for( ; *s; s++)
  1106. 1800076c: 00164783 lbu a5,1(a2)
  1107. 18000770: 0605 addi a2,a2,1
  1108. 18000772: fff9 bnez a5,18000750 <vnprintf+0x3e>
  1109. }
  1110. if (pos < n)
  1111. out[pos] = 0;
  1112. else if (n)
  1113. out[n-1] = 0;
  1114. return pos;
  1115. 18000774: 0007051b sext.w a0,a4
  1116. if (pos < n)
  1117. 18000778: 18b76b63 bltu a4,a1,1800090e <vnprintf+0x1fc>
  1118. else if (n)
  1119. 1800077c: c589 beqz a1,18000786 <vnprintf+0x74>
  1120. out[n-1] = 0;
  1121. 1800077e: 00b30733 add a4,t1,a1
  1122. 18000782: fe070fa3 sb zero,-1(a4)
  1123. }
  1124. 18000786: 7422 ld s0,40(sp)
  1125. 18000788: 7482 ld s1,32(sp)
  1126. 1800078a: 6962 ld s2,24(sp)
  1127. 1800078c: 69c2 ld s3,16(sp)
  1128. 1800078e: 6a22 ld s4,8(sp)
  1129. 18000790: 6a82 ld s5,0(sp)
  1130. 18000792: 6145 addi sp,sp,48
  1131. 18000794: 8082 ret
  1132. long num = longarg ? va_arg(vl, long) : va_arg(vl, int);
  1133. 18000796: 00868793 addi a5,a3,8
  1134. 1800079a: 1a091d63 bnez s2,18000954 <vnprintf+0x242>
  1135. 1800079e: 0006aa03 lw s4,0(a3)
  1136. for(int i = 2*(longarg ? sizeof(long) : sizeof(int))-1; i >= 0; i--) {
  1137. 180007a2: 4a9d li s5,7
  1138. long num = longarg ? va_arg(vl, long) : va_arg(vl, int);
  1139. 180007a4: 86be mv a3,a5
  1140. for(int i = 2*(longarg ? sizeof(long) : sizeof(int))-1; i >= 0; i--) {
  1141. 180007a6: 002a9813 slli a6,s5,0x2
  1142. 180007aa: 87ba mv a5,a4
  1143. if (++pos < n) out[pos-1] = (d < 10 ? '0'+d : 'a'+d-10);
  1144. 180007ac: 0785 addi a5,a5,1
  1145. 180007ae: 02b7f063 bgeu a5,a1,180007ce <vnprintf+0xbc>
  1146. int d = (num >> (4*i)) & 0xF;
  1147. 180007b2: 410a58b3 sra a7,s4,a6
  1148. if (++pos < n) out[pos-1] = (d < 10 ? '0'+d : 'a'+d-10);
  1149. 180007b6: 00f8f993 andi s3,a7,15
  1150. 180007ba: 05798913 addi s2,s3,87
  1151. 180007be: 013f4463 blt t5,s3,180007c6 <vnprintf+0xb4>
  1152. 180007c2: 03098913 addi s2,s3,48
  1153. 180007c6: 00f308b3 add a7,t1,a5
  1154. 180007ca: ff288fa3 sb s2,-1(a7)
  1155. for(int i = 2*(longarg ? sizeof(long) : sizeof(int))-1; i >= 0; i--) {
  1156. 180007ce: 3871 addiw a6,a6,-4
  1157. 180007d0: fdc81ee3 bne a6,t3,180007ac <vnprintf+0x9a>
  1158. for( ; *s; s++)
  1159. 180007d4: 00164783 lbu a5,1(a2)
  1160. 180007d8: 0705 addi a4,a4,1
  1161. if (++pos < n) out[pos-1] = (d < 10 ? '0'+d : 'a'+d-10);
  1162. 180007da: 9756 add a4,a4,s5
  1163. longarg = false;
  1164. 180007dc: 4901 li s2,0
  1165. format = false;
  1166. 180007de: 4801 li a6,0
  1167. for( ; *s; s++)
  1168. 180007e0: 0605 addi a2,a2,1
  1169. 180007e2: f7bd bnez a5,18000750 <vnprintf+0x3e>
  1170. 180007e4: bf41 j 18000774 <vnprintf+0x62>
  1171. const char* s2 = va_arg(vl, const char*);
  1172. 180007e6: 0006b803 ld a6,0(a3)
  1173. 180007ea: 00868913 addi s2,a3,8
  1174. while (*s2) {
  1175. 180007ee: 00084683 lbu a3,0(a6)
  1176. 180007f2: 18068a63 beqz a3,18000986 <vnprintf+0x274>
  1177. 180007f6: 87ba mv a5,a4
  1178. if (++pos < n)
  1179. 180007f8: 0785 addi a5,a5,1
  1180. 180007fa: 00b7f663 bgeu a5,a1,18000806 <vnprintf+0xf4>
  1181. out[pos-1] = *s2;
  1182. 180007fe: 00f308b3 add a7,t1,a5
  1183. 18000802: fed88fa3 sb a3,-1(a7)
  1184. while (*s2) {
  1185. 18000806: 40e786b3 sub a3,a5,a4
  1186. 1800080a: 96c2 add a3,a3,a6
  1187. 1800080c: 0006c683 lbu a3,0(a3)
  1188. 18000810: f6e5 bnez a3,180007f8 <vnprintf+0xe6>
  1189. if (++pos < n)
  1190. 18000812: 873e mv a4,a5
  1191. for( ; *s; s++)
  1192. 18000814: 00164783 lbu a5,1(a2)
  1193. const char* s2 = va_arg(vl, const char*);
  1194. 18000818: 86ca mv a3,s2
  1195. format = false;
  1196. 1800081a: 4801 li a6,0
  1197. longarg = false;
  1198. 1800081c: 4901 li s2,0
  1199. for( ; *s; s++)
  1200. 1800081e: 0605 addi a2,a2,1
  1201. 18000820: fb85 bnez a5,18000750 <vnprintf+0x3e>
  1202. 18000822: bf89 j 18000774 <vnprintf+0x62>
  1203. if (++pos < n) out[pos-1] = '0';
  1204. 18000824: 00170793 addi a5,a4,1
  1205. 18000828: 00b7f663 bgeu a5,a1,18000834 <vnprintf+0x122>
  1206. 1800082c: 00e30833 add a6,t1,a4
  1207. 18000830: 00780023 sb t2,0(a6)
  1208. if (++pos < n) out[pos-1] = 'x';
  1209. 18000834: 0709 addi a4,a4,2
  1210. long num = longarg ? va_arg(vl, long) : va_arg(vl, int);
  1211. 18000836: 00868813 addi a6,a3,8
  1212. if (++pos < n) out[pos-1] = 'x';
  1213. 1800083a: 00b77563 bgeu a4,a1,18000844 <vnprintf+0x132>
  1214. 1800083e: 979a add a5,a5,t1
  1215. 18000840: 00878023 sb s0,0(a5)
  1216. long num = longarg ? va_arg(vl, long) : va_arg(vl, int);
  1217. 18000844: 0006ba03 ld s4,0(a3)
  1218. for(int i = 2*(longarg ? sizeof(long) : sizeof(int))-1; i >= 0; i--) {
  1219. 18000848: 4abd li s5,15
  1220. long num = longarg ? va_arg(vl, long) : va_arg(vl, int);
  1221. 1800084a: 86c2 mv a3,a6
  1222. 1800084c: bfa9 j 180007a6 <vnprintf+0x94>
  1223. 1800084e: 00868993 addi s3,a3,8
  1224. long num = longarg ? va_arg(vl, long) : va_arg(vl, int);
  1225. 18000852: 0e090263 beqz s2,18000936 <vnprintf+0x224>
  1226. 18000856: 0006b803 ld a6,0(a3)
  1227. if (num < 0) {
  1228. 1800085a: 0e084263 bltz a6,1800093e <vnprintf+0x22c>
  1229. for (long nn = num; nn /= 10; digits++)
  1230. 1800085e: 02a847b3 div a5,a6,a0
  1231. 18000862: 10078f63 beqz a5,18000980 <vnprintf+0x26e>
  1232. long digits = 1;
  1233. 18000866: 4685 li a3,1
  1234. for (long nn = num; nn /= 10; digits++)
  1235. 18000868: 02a7c7b3 div a5,a5,a0
  1236. 1800086c: 0685 addi a3,a3,1
  1237. 1800086e: ffed bnez a5,18000868 <vnprintf+0x156>
  1238. for (int i = digits-1; i >= 0; i--) {
  1239. 18000870: fff6879b addiw a5,a3,-1
  1240. pos += digits;
  1241. 18000874: 88b6 mv a7,a3
  1242. for (int i = digits-1; i >= 0; i--) {
  1243. 18000876: 0207c863 bltz a5,180008a6 <vnprintf+0x194>
  1244. 1800087a: 00170a13 addi s4,a4,1
  1245. if (pos + i + 1 < n) out[pos + i] = '0' + (num % 10);
  1246. 1800087e: 00fa06b3 add a3,s4,a5
  1247. 18000882: 00b6fb63 bgeu a3,a1,18000898 <vnprintf+0x186>
  1248. 18000886: 02a866b3 rem a3,a6,a0
  1249. 1800088a: 00f70933 add s2,a4,a5
  1250. 1800088e: 991a add s2,s2,t1
  1251. 18000890: 0306869b addiw a3,a3,48
  1252. 18000894: 00d90023 sb a3,0(s2)
  1253. for (int i = digits-1; i >= 0; i--) {
  1254. 18000898: 17fd addi a5,a5,-1
  1255. 1800089a: 0007869b sext.w a3,a5
  1256. num /= 10;
  1257. 1800089e: 02a84833 div a6,a6,a0
  1258. for (int i = digits-1; i >= 0; i--) {
  1259. 180008a2: fc06dee3 bgez a3,1800087e <vnprintf+0x16c>
  1260. for( ; *s; s++)
  1261. 180008a6: 00164783 lbu a5,1(a2)
  1262. pos += digits;
  1263. 180008aa: 9746 add a4,a4,a7
  1264. break;
  1265. 180008ac: 86ce mv a3,s3
  1266. longarg = false;
  1267. 180008ae: 4901 li s2,0
  1268. format = false;
  1269. 180008b0: 4801 li a6,0
  1270. for( ; *s; s++)
  1271. 180008b2: 0605 addi a2,a2,1
  1272. 180008b4: e8079ee3 bnez a5,18000750 <vnprintf+0x3e>
  1273. 180008b8: bd75 j 18000774 <vnprintf+0x62>
  1274. if (++pos < n) out[pos-1] = (char)va_arg(vl,int);
  1275. 180008ba: 00170793 addi a5,a4,1
  1276. 180008be: 06b7f363 bgeu a5,a1,18000924 <vnprintf+0x212>
  1277. 180008c2: 0006a803 lw a6,0(a3)
  1278. 180008c6: 971a add a4,a4,t1
  1279. 180008c8: 06a1 addi a3,a3,8
  1280. 180008ca: 01070023 sb a6,0(a4)
  1281. 180008ce: 873e mv a4,a5
  1282. for( ; *s; s++)
  1283. 180008d0: 00164783 lbu a5,1(a2)
  1284. longarg = false;
  1285. 180008d4: 4901 li s2,0
  1286. format = false;
  1287. 180008d6: 4801 li a6,0
  1288. for( ; *s; s++)
  1289. 180008d8: 0605 addi a2,a2,1
  1290. 180008da: e6079be3 bnez a5,18000750 <vnprintf+0x3e>
  1291. 180008de: bd59 j 18000774 <vnprintf+0x62>
  1292. else if(*s == '%')
  1293. 180008e0: e85785e3 beq a5,t0,1800076a <vnprintf+0x58>
  1294. if (++pos < n) out[pos-1] = *s;
  1295. 180008e4: 00170893 addi a7,a4,1
  1296. 180008e8: 00b8fc63 bgeu a7,a1,18000900 <vnprintf+0x1ee>
  1297. 180008ec: 971a add a4,a4,t1
  1298. 180008ee: 00f70023 sb a5,0(a4)
  1299. for( ; *s; s++)
  1300. 180008f2: 00164783 lbu a5,1(a2)
  1301. if (++pos < n) out[pos-1] = *s;
  1302. 180008f6: 8746 mv a4,a7
  1303. for( ; *s; s++)
  1304. 180008f8: 0605 addi a2,a2,1
  1305. 180008fa: e4079be3 bnez a5,18000750 <vnprintf+0x3e>
  1306. 180008fe: bd9d j 18000774 <vnprintf+0x62>
  1307. 18000900: 00164783 lbu a5,1(a2)
  1308. 18000904: 8746 mv a4,a7
  1309. 18000906: 0605 addi a2,a2,1
  1310. 18000908: e40794e3 bnez a5,18000750 <vnprintf+0x3e>
  1311. 1800090c: b5a5 j 18000774 <vnprintf+0x62>
  1312. out[pos] = 0;
  1313. 1800090e: 971a add a4,a4,t1
  1314. 18000910: 00070023 sb zero,0(a4)
  1315. }
  1316. 18000914: 7422 ld s0,40(sp)
  1317. 18000916: 7482 ld s1,32(sp)
  1318. 18000918: 6962 ld s2,24(sp)
  1319. 1800091a: 69c2 ld s3,16(sp)
  1320. 1800091c: 6a22 ld s4,8(sp)
  1321. 1800091e: 6a82 ld s5,0(sp)
  1322. 18000920: 6145 addi sp,sp,48
  1323. 18000922: 8082 ret
  1324. 18000924: 873e mv a4,a5
  1325. for( ; *s; s++)
  1326. 18000926: 00164783 lbu a5,1(a2)
  1327. longarg = false;
  1328. 1800092a: 4901 li s2,0
  1329. format = false;
  1330. 1800092c: 4801 li a6,0
  1331. for( ; *s; s++)
  1332. 1800092e: 0605 addi a2,a2,1
  1333. 18000930: e20790e3 bnez a5,18000750 <vnprintf+0x3e>
  1334. 18000934: b581 j 18000774 <vnprintf+0x62>
  1335. long num = longarg ? va_arg(vl, long) : va_arg(vl, int);
  1336. 18000936: 0006a803 lw a6,0(a3)
  1337. if (num < 0) {
  1338. 1800093a: f20852e3 bgez a6,1800085e <vnprintf+0x14c>
  1339. if (++pos < n) out[pos-1] = '-';
  1340. 1800093e: 00170793 addi a5,a4,1
  1341. num = -num;
  1342. 18000942: 41000833 neg a6,a6
  1343. if (++pos < n) out[pos-1] = '-';
  1344. 18000946: 02b7f363 bgeu a5,a1,1800096c <vnprintf+0x25a>
  1345. 1800094a: 971a add a4,a4,t1
  1346. 1800094c: 00970023 sb s1,0(a4)
  1347. 18000950: 873e mv a4,a5
  1348. 18000952: b731 j 1800085e <vnprintf+0x14c>
  1349. long num = longarg ? va_arg(vl, long) : va_arg(vl, int);
  1350. 18000954: 0006ba03 ld s4,0(a3)
  1351. for(int i = 2*(longarg ? sizeof(long) : sizeof(int))-1; i >= 0; i--) {
  1352. 18000958: 4abd li s5,15
  1353. long num = longarg ? va_arg(vl, long) : va_arg(vl, int);
  1354. 1800095a: 86be mv a3,a5
  1355. 1800095c: b5a9 j 180007a6 <vnprintf+0x94>
  1356. for( ; *s; s++)
  1357. 1800095e: 00164783 lbu a5,1(a2)
  1358. if(format)
  1359. 18000962: 8942 mv s2,a6
  1360. for( ; *s; s++)
  1361. 18000964: 0605 addi a2,a2,1
  1362. 18000966: de0795e3 bnez a5,18000750 <vnprintf+0x3e>
  1363. 1800096a: b529 j 18000774 <vnprintf+0x62>
  1364. 1800096c: 873e mv a4,a5
  1365. 1800096e: bdc5 j 1800085e <vnprintf+0x14c>
  1366. size_t pos = 0;
  1367. 18000970: 4701 li a4,0
  1368. for( ; *s; s++)
  1369. 18000972: 4501 li a0,0
  1370. if (pos < n)
  1371. 18000974: 00b77d63 bgeu a4,a1,1800098e <vnprintf+0x27c>
  1372. out[pos] = 0;
  1373. 18000978: 971a add a4,a4,t1
  1374. 1800097a: 00070023 sb zero,0(a4)
  1375. 1800097e: 8082 ret
  1376. for (long nn = num; nn /= 10; digits++)
  1377. 18000980: 4885 li a7,1
  1378. for (int i = digits-1; i >= 0; i--) {
  1379. 18000982: 4781 li a5,0
  1380. 18000984: bddd j 1800087a <vnprintf+0x168>
  1381. const char* s2 = va_arg(vl, const char*);
  1382. 18000986: 86ca mv a3,s2
  1383. format = false;
  1384. 18000988: 4801 li a6,0
  1385. longarg = false;
  1386. 1800098a: 4901 li s2,0
  1387. 1800098c: b3c5 j 1800076c <vnprintf+0x5a>
  1388. else if (n)
  1389. 1800098e: c591 beqz a1,1800099a <vnprintf+0x288>
  1390. out[n-1] = 0;
  1391. 18000990: 00b30733 add a4,t1,a1
  1392. 18000994: fe070fa3 sb zero,-1(a4)
  1393. 18000998: 8082 ret
  1394. }
  1395. 1800099a: 8082 ret
  1396. 000000001800099c <vprintk>:
  1397. static void vprintk(const char* s, va_list vl)
  1398. {
  1399. 1800099c: 716d addi sp,sp,-272
  1400. 1800099e: 862a mv a2,a0
  1401. 180009a0: 86ae mv a3,a1
  1402. char out[256];
  1403. int res = vnprintf(out, sizeof(out), s, vl);
  1404. 180009a2: 850a mv a0,sp
  1405. 180009a4: 10000593 li a1,256
  1406. {
  1407. 180009a8: e606 sd ra,264(sp)
  1408. int res = vnprintf(out, sizeof(out), s, vl);
  1409. 180009aa: d69ff0ef jal ra,18000712 <vnprintf>
  1410. while (*s){
  1411. 180009ae: 00014603 lbu a2,0(sp)
  1412. 180009b2: ca0d beqz a2,180009e4 <vprintk+0x48>
  1413. return readl((volatile void *)(uart_base[uart_id] + offset));
  1414. 180009b4: 0000f797 auipc a5,0xf
  1415. 180009b8: 64c7e783 lwu a5,1612(a5) # 18010000 <uart_id>
  1416. 180009bc: 00379713 slli a4,a5,0x3
  1417. 180009c0: 00002797 auipc a5,0x2
  1418. 180009c4: a8878793 addi a5,a5,-1400 # 18002448 <uart_base>
  1419. 180009c8: 97ba add a5,a5,a4
  1420. 180009ca: 638c ld a1,0(a5)
  1421. writel(value, (volatile void *)(uart_base[uart_id] + offset));
  1422. 180009cc: 868a mv a3,sp
  1423. return readl((volatile void *)(uart_base[uart_id] + offset));
  1424. 180009ce: 01458713 addi a4,a1,20
  1425. _putc(*s++);
  1426. 180009d2: 0685 addi a3,a3,1
  1427. 180009d4: 431c lw a5,0(a4)
  1428. {}while((serial_in(REG_LSR) & LSR_THRE) == 0);
  1429. 180009d6: 0207f793 andi a5,a5,32
  1430. 180009da: dfed beqz a5,180009d4 <vprintk+0x38>
  1431. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  1432. 180009dc: c190 sw a2,0(a1)
  1433. while (*s){
  1434. 180009de: 0006c603 lbu a2,0(a3)
  1435. 180009e2: fa65 bnez a2,180009d2 <vprintk+0x36>
  1436. _puts(out);
  1437. }
  1438. 180009e4: 60b2 ld ra,264(sp)
  1439. 180009e6: 6151 addi sp,sp,272
  1440. 180009e8: 8082 ret
  1441. 00000000180009ea <printk>:
  1442. void printk(const char* s, ...)
  1443. {
  1444. 180009ea: 711d addi sp,sp,-96
  1445. va_list vl;
  1446. va_start(vl, s);
  1447. 180009ec: 02810313 addi t1,sp,40
  1448. {
  1449. 180009f0: f42e sd a1,40(sp)
  1450. vprintk(s, vl);
  1451. 180009f2: 859a mv a1,t1
  1452. {
  1453. 180009f4: ec06 sd ra,24(sp)
  1454. 180009f6: f832 sd a2,48(sp)
  1455. 180009f8: fc36 sd a3,56(sp)
  1456. 180009fa: e0ba sd a4,64(sp)
  1457. 180009fc: e4be sd a5,72(sp)
  1458. 180009fe: e8c2 sd a6,80(sp)
  1459. 18000a00: ecc6 sd a7,88(sp)
  1460. va_start(vl, s);
  1461. 18000a02: e41a sd t1,8(sp)
  1462. vprintk(s, vl);
  1463. 18000a04: f99ff0ef jal ra,1800099c <vprintk>
  1464. va_end(vl);
  1465. }
  1466. 18000a08: 60e2 ld ra,24(sp)
  1467. 18000a0a: 6125 addi sp,sp,96
  1468. 18000a0c: 8082 ret
  1469. 0000000018000a0e <sys_memcpy>:
  1470. void * sys_memcpy(void *p_des,const void * p_src,unsigned long size)
  1471. {
  1472. char *tmp = p_des;
  1473. const char *s = p_src;
  1474. while (size--)
  1475. 18000a0e: ca19 beqz a2,18000a24 <sys_memcpy+0x16>
  1476. 18000a10: 962a add a2,a2,a0
  1477. char *tmp = p_des;
  1478. 18000a12: 87aa mv a5,a0
  1479. *tmp++ = *s++;
  1480. 18000a14: 0005c703 lbu a4,0(a1)
  1481. 18000a18: 0785 addi a5,a5,1
  1482. 18000a1a: 0585 addi a1,a1,1
  1483. 18000a1c: fee78fa3 sb a4,-1(a5)
  1484. while (size--)
  1485. 18000a20: fec79ae3 bne a5,a2,18000a14 <sys_memcpy+0x6>
  1486. return p_des;
  1487. }
  1488. 18000a24: 8082 ret
  1489. 0000000018000a26 <sys_memcmp>:
  1490. int sys_memcmp(const void * cs,const void * ct,unsigned int count)
  1491. {
  1492. 18000a26: 87aa mv a5,a0
  1493. const unsigned char *su1, *su2;
  1494. int res = 0;
  1495. for( su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--)
  1496. 18000a28: c215 beqz a2,18000a4c <sys_memcmp+0x26>
  1497. 18000a2a: 1602 slli a2,a2,0x20
  1498. 18000a2c: 9201 srli a2,a2,0x20
  1499. 18000a2e: 00c506b3 add a3,a0,a2
  1500. 18000a32: a019 j 18000a38 <sys_memcmp+0x12>
  1501. 18000a34: 00d78b63 beq a5,a3,18000a4a <sys_memcmp+0x24>
  1502. if ((res = *su1 - *su2) != 0)
  1503. 18000a38: 0007c503 lbu a0,0(a5)
  1504. 18000a3c: 0005c703 lbu a4,0(a1)
  1505. for( su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--)
  1506. 18000a40: 0785 addi a5,a5,1
  1507. 18000a42: 0585 addi a1,a1,1
  1508. if ((res = *su1 - *su2) != 0)
  1509. 18000a44: 9d19 subw a0,a0,a4
  1510. 18000a46: d57d beqz a0,18000a34 <sys_memcmp+0xe>
  1511. break;
  1512. return res;
  1513. }
  1514. 18000a48: 8082 ret
  1515. 18000a4a: 8082 ret
  1516. for( su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--)
  1517. 18000a4c: 4501 li a0,0
  1518. }
  1519. 18000a4e: 8082 ret
  1520. 0000000018000a50 <_memcpy>:
  1521. void * _memcpy(void * dest,const void *src,unsigned int count)
  1522. {
  1523. char *tmp = (char *) dest;
  1524. const char *s = (char *) src;
  1525. while (count--)
  1526. 18000a50: ce11 beqz a2,18000a6c <_memcpy+0x1c>
  1527. 18000a52: 1602 slli a2,a2,0x20
  1528. 18000a54: 9201 srli a2,a2,0x20
  1529. 18000a56: 00c506b3 add a3,a0,a2
  1530. char *tmp = (char *) dest;
  1531. 18000a5a: 87aa mv a5,a0
  1532. *tmp++ = *s++;
  1533. 18000a5c: 0005c703 lbu a4,0(a1)
  1534. 18000a60: 0785 addi a5,a5,1
  1535. 18000a62: 0585 addi a1,a1,1
  1536. 18000a64: fee78fa3 sb a4,-1(a5)
  1537. while (count--)
  1538. 18000a68: fef69ae3 bne a3,a5,18000a5c <_memcpy+0xc>
  1539. return dest;
  1540. }
  1541. 18000a6c: 8082 ret
  1542. 0000000018000a6e <sys_memcpy_32>:
  1543. RETURN VALUE:
  1544. ===========================================================================*/
  1545. void sys_memcpy_32(void *p_des,const void * p_src,unsigned long size)
  1546. {
  1547. unsigned long i;
  1548. for (i=0;i<size;i++)
  1549. 18000a6e: ca19 beqz a2,18000a84 <sys_memcpy_32+0x16>
  1550. 18000a70: 060e slli a2,a2,0x3
  1551. 18000a72: 00c58733 add a4,a1,a2
  1552. *((unsigned long*)p_des+i) = *((unsigned long*)p_src+i);
  1553. 18000a76: 619c ld a5,0(a1)
  1554. for (i=0;i<size;i++)
  1555. 18000a78: 05a1 addi a1,a1,8
  1556. 18000a7a: 0521 addi a0,a0,8
  1557. *((unsigned long*)p_des+i) = *((unsigned long*)p_src+i);
  1558. 18000a7c: fef53c23 sd a5,-8(a0)
  1559. for (i=0;i<size;i++)
  1560. 18000a80: fee59be3 bne a1,a4,18000a76 <sys_memcpy_32+0x8>
  1561. }
  1562. 18000a84: 8082 ret
  1563. 0000000018000a86 <sys_memset>:
  1564. RETURN VALUE:
  1565. ===========================================================================*/
  1566. void sys_memset(void *p_des,unsigned char c,unsigned long size)
  1567. {
  1568. unsigned long i;
  1569. for (i=0;i<size;i++)
  1570. 18000a86: c219 beqz a2,18000a8c <sys_memset+0x6>
  1571. *((char*)p_des+i) = c;
  1572. 18000a88: 7fa0106f j 18002282 <memset>
  1573. }
  1574. 18000a8c: 8082 ret
  1575. 0000000018000a8e <sys_memset32>:
  1576. RETURN VALUE:
  1577. ===========================================================================*/
  1578. void sys_memset32(void *p_des,int c,unsigned long size)
  1579. {
  1580. unsigned long i;
  1581. for(i=0; i< size; i++)
  1582. 18000a8e: 00361793 slli a5,a2,0x3
  1583. 18000a92: 97aa add a5,a5,a0
  1584. 18000a94: c609 beqz a2,18000a9e <sys_memset32+0x10>
  1585. ((unsigned long*)p_des)[i] = c;
  1586. 18000a96: e10c sd a1,0(a0)
  1587. for(i=0; i< size; i++)
  1588. 18000a98: 0521 addi a0,a0,8
  1589. 18000a9a: fef51ee3 bne a0,a5,18000a96 <sys_memset32+0x8>
  1590. }
  1591. 18000a9e: 8082 ret
  1592. 0000000018000aa0 <spi_register>:
  1593. #define SPI_CONTROLLER_NUM 1
  1594. struct spi_operation *operations[SPI_CONTROLLER_NUM];
  1595. int spi_register(unsigned int bus, struct spi_operation *operation)
  1596. {
  1597. if(bus> SPI_CONTROLLER_NUM-1)
  1598. 18000aa0: e511 bnez a0,18000aac <spi_register+0xc>
  1599. return -1;
  1600. operations[bus] = operation;
  1601. 18000aa2: 0000f797 auipc a5,0xf
  1602. 18000aa6: 56b7b323 sd a1,1382(a5) # 18010008 <operations>
  1603. return 0;
  1604. 18000aaa: 8082 ret
  1605. return -1;
  1606. 18000aac: 557d li a0,-1
  1607. }
  1608. 18000aae: 8082 ret
  1609. 0000000018000ab0 <spi_unregister>:
  1610. int spi_unregister(unsigned int bus)
  1611. {
  1612. if(bus> SPI_CONTROLLER_NUM-1)
  1613. 18000ab0: e511 bnez a0,18000abc <spi_unregister+0xc>
  1614. return -1;
  1615. operations[bus] = 0;
  1616. 18000ab2: 0000f797 auipc a5,0xf
  1617. 18000ab6: 5407bb23 sd zero,1366(a5) # 18010008 <operations>
  1618. return 0;
  1619. 18000aba: 8082 ret
  1620. return -1;
  1621. 18000abc: 557d li a0,-1
  1622. }
  1623. 18000abe: 8082 ret
  1624. 0000000018000ac0 <spi_setup_slave>:
  1625. struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
  1626. unsigned int max_hz, unsigned int mode, unsigned int bus_width)
  1627. {
  1628. if(bus> SPI_CONTROLLER_NUM-1)
  1629. 18000ac0: e901 bnez a0,18000ad0 <spi_setup_slave+0x10>
  1630. return NULL;
  1631. if(operations[bus]->setup_slave)
  1632. 18000ac2: 0000f797 auipc a5,0xf
  1633. 18000ac6: 5467b783 ld a5,1350(a5) # 18010008 <operations>
  1634. 18000aca: 639c ld a5,0(a5)
  1635. 18000acc: c391 beqz a5,18000ad0 <spi_setup_slave+0x10>
  1636. {
  1637. return operations[bus]->setup_slave(bus,cs,max_hz,mode,bus_width);
  1638. 18000ace: 8782 jr a5
  1639. }
  1640. return NULL;
  1641. }
  1642. 18000ad0: 4501 li a0,0
  1643. 18000ad2: 8082 ret
  1644. 0000000018000ad4 <spi_xfer>:
  1645. void *din, unsigned long flags,int bit_mode)
  1646. {
  1647. unsigned int bus = slave->bus;
  1648. int ret = -1;
  1649. if(bus> SPI_CONTROLLER_NUM-1)
  1650. 18000ad4: 00052803 lw a6,0(a0)
  1651. 18000ad8: 00081b63 bnez a6,18000aee <spi_xfer+0x1a>
  1652. return -1;
  1653. if(operations[bus]->spi_xfer)
  1654. 18000adc: 0000f817 auipc a6,0xf
  1655. 18000ae0: 52c83803 ld a6,1324(a6) # 18010008 <operations>
  1656. 18000ae4: 00883803 ld a6,8(a6)
  1657. 18000ae8: 00080363 beqz a6,18000aee <spi_xfer+0x1a>
  1658. ret = operations[bus]->spi_xfer(slave, bitlen, dout, din, flags, bit_mode);
  1659. 18000aec: 8802 jr a6
  1660. return ret;
  1661. }
  1662. 18000aee: 557d li a0,-1
  1663. 18000af0: 8082 ret
  1664. 0000000018000af2 <spi_flash_probe_nor>:
  1665. struct spi_flash_params *params;
  1666. struct spi_flash *flash;
  1667. u32 id = 0;
  1668. static int i = 0;
  1669. id = ((idcode[2] << 16) | (idcode[1] << 8) | idcode[0]);
  1670. 18000af2: 0025c783 lbu a5,2(a1)
  1671. 18000af6: 0015c703 lbu a4,1(a1)
  1672. 18000afa: 0005c683 lbu a3,0(a1)
  1673. 18000afe: 0107979b slliw a5,a5,0x10
  1674. 18000b02: 0087171b slliw a4,a4,0x8
  1675. 18000b06: 8fd9 or a5,a5,a4
  1676. 18000b08: 8fd5 or a5,a5,a3
  1677. 18000b0a: 0007871b sext.w a4,a5
  1678. 18000b0e: 87ba mv a5,a4
  1679. if(id == 0x0)
  1680. 18000b10: c355 beqz a4,18000bb4 <spi_flash_probe_nor+0xc2>
  1681. {
  1682. return NULL;
  1683. }
  1684. params = spi_flash_table;
  1685. for (i = 0; spi_flash_table[i].name != NULL; i++)
  1686. 18000b12: 0000f717 auipc a4,0xf
  1687. 18000b16: 4e072f23 sw zero,1278(a4) # 18010010 <i.0>
  1688. {
  1689. if ((spi_flash_table[i].id & 0xFFFFFF) == id)
  1690. 18000b1a: 00200737 lui a4,0x200
  1691. 18000b1e: 20170713 addi a4,a4,513 # 200201 <__stack_size+0x1ffa01>
  1692. 18000b22: 08e78b63 beq a5,a4,18000bb8 <spi_flash_probe_nor+0xc6>
  1693. 18000b26: 4785 li a5,1
  1694. 18000b28: 0000f717 auipc a4,0xf
  1695. 18000b2c: 4ef72423 sw a5,1256(a4) # 18010010 <i.0>
  1696. for (i = 0; spi_flash_table[i].name != NULL; i++)
  1697. 18000b30: 00002617 auipc a2,0x2
  1698. 18000b34: 94860613 addi a2,a2,-1720 # 18002478 <digits.0+0x10>
  1699. 18000b38: 4685 li a3,1
  1700. {
  1701. break;
  1702. }
  1703. }
  1704. flash = &g_spi_flash[spi->bus];
  1705. 18000b3a: 00056783 lwu a5,0(a0)
  1706. //uart_printf("SF: Failed to allocate memory\r\n");
  1707. return NULL;
  1708. }
  1709. flash->name = spi_flash_table[i].name;
  1710. if(spi_flash_table[i].flags == NOR)
  1711. 18000b3e: 00169713 slli a4,a3,0x1
  1712. 18000b42: 9736 add a4,a4,a3
  1713. flash = &g_spi_flash[spi->bus];
  1714. 18000b44: 00379513 slli a0,a5,0x3
  1715. 18000b48: 8d1d sub a0,a0,a5
  1716. if(spi_flash_table[i].flags == NOR)
  1717. 18000b4a: 070e slli a4,a4,0x3
  1718. 18000b4c: 00002797 auipc a5,0x2
  1719. 18000b50: 94c78793 addi a5,a5,-1716 # 18002498 <spi_flash_table>
  1720. 18000b54: 973e add a4,a4,a5
  1721. 18000b56: 4b54 lw a3,20(a4)
  1722. flash = &g_spi_flash[spi->bus];
  1723. 18000b58: 00351793 slli a5,a0,0x3
  1724. 18000b5c: 0000f517 auipc a0,0xf
  1725. 18000b60: 4bc50513 addi a0,a0,1212 # 18010018 <g_spi_flash>
  1726. 18000b64: 953e add a0,a0,a5
  1727. flash->name = spi_flash_table[i].name;
  1728. 18000b66: e510 sd a2,8(a0)
  1729. if(spi_flash_table[i].flags == NOR)
  1730. 18000b68: e6b9 bnez a3,18000bb6 <spi_flash_probe_nor+0xc4>
  1731. {
  1732. /* Assuming power-of-two page size initially. */
  1733. flash->write = spi_flash_cmd_write_mode;
  1734. flash->erase = spi_flash_erase_mode;
  1735. flash->read = spi_flash_read_mode;
  1736. flash->page_size = 1 << spi_flash_table[i].l2_page_size;
  1737. 18000b6a: 00c74583 lbu a1,12(a4)
  1738. flash->sector_size = flash->page_size * spi_flash_table[i].pages_per_sector;
  1739. 18000b6e: 00e75683 lhu a3,14(a4)
  1740. flash->block_size = flash->sector_size * spi_flash_table[i].sectors_per_block;
  1741. 18000b72: 01075783 lhu a5,16(a4)
  1742. flash->size = flash->page_size * spi_flash_table[i].pages_per_sector
  1743. * spi_flash_table[i].sectors_per_block
  1744. * spi_flash_table[i].nr_blocks;
  1745. 18000b76: 01275603 lhu a2,18(a4)
  1746. flash->sector_size = flash->page_size * spi_flash_table[i].pages_per_sector;
  1747. 18000b7a: 00b6973b sllw a4,a3,a1
  1748. flash->block_size = flash->sector_size * spi_flash_table[i].sectors_per_block;
  1749. 18000b7e: 02e787bb mulw a5,a5,a4
  1750. flash->page_size = 1 << spi_flash_table[i].l2_page_size;
  1751. 18000b82: 4685 li a3,1
  1752. 18000b84: 00b696bb sllw a3,a3,a1
  1753. 18000b88: c954 sw a3,20(a0)
  1754. flash->write = spi_flash_cmd_write_mode;
  1755. 18000b8a: 00001597 auipc a1,0x1
  1756. 18000b8e: b3258593 addi a1,a1,-1230 # 180016bc <spi_flash_cmd_write_mode>
  1757. 18000b92: f50c sd a1,40(a0)
  1758. flash->erase = spi_flash_erase_mode;
  1759. 18000b94: 00001597 auipc a1,0x1
  1760. 18000b98: afe58593 addi a1,a1,-1282 # 18001692 <spi_flash_erase_mode>
  1761. 18000b9c: f90c sd a1,48(a0)
  1762. flash->read = spi_flash_read_mode;
  1763. 18000b9e: 00001597 auipc a1,0x1
  1764. 18000ba2: e0058593 addi a1,a1,-512 # 1800199e <spi_flash_read_mode>
  1765. 18000ba6: f10c sd a1,32(a0)
  1766. * spi_flash_table[i].nr_blocks;
  1767. 18000ba8: 02f606bb mulw a3,a2,a5
  1768. flash->sector_size = flash->page_size * spi_flash_table[i].pages_per_sector;
  1769. 18000bac: cd18 sw a4,24(a0)
  1770. flash->block_size = flash->sector_size * spi_flash_table[i].sectors_per_block;
  1771. 18000bae: cd5c sw a5,28(a0)
  1772. flash->size = flash->page_size * spi_flash_table[i].pages_per_sector
  1773. 18000bb0: c914 sw a3,16(a0)
  1774. 18000bb2: 8082 ret
  1775. return NULL;
  1776. 18000bb4: 4501 li a0,0
  1777. }
  1778. //uart_printf("spi probe complete\r\n");
  1779. return flash;
  1780. }
  1781. 18000bb6: 8082 ret
  1782. for (i = 0; spi_flash_table[i].name != NULL; i++)
  1783. 18000bb8: 00002617 auipc a2,0x2
  1784. 18000bbc: 8d060613 addi a2,a2,-1840 # 18002488 <digits.0+0x20>
  1785. 18000bc0: 4681 li a3,0
  1786. 18000bc2: bfa5 j 18000b3a <spi_flash_probe_nor+0x48>
  1787. 0000000018000bc4 <spi_flash_probe>:
  1788. static struct spi_flash aic_flash;
  1789. struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
  1790. unsigned int max_hz, unsigned int mode, unsigned int bus_width)
  1791. {
  1792. 18000bc4: 1101 addi sp,sp,-32
  1793. 18000bc6: ec06 sd ra,24(sp)
  1794. 18000bc8: e822 sd s0,16(sp)
  1795. struct spi_slave *spi;
  1796. struct spi_flash *flash = &aic_flash;
  1797. int ret = 0;
  1798. u8 idcode[IDCODE_LEN];
  1799. spi = spi_setup_slave(bus, cs, max_hz, mode, bus_width);
  1800. 18000bca: ef7ff0ef jal ra,18000ac0 <spi_setup_slave>
  1801. if (!spi) {
  1802. 18000bce: c121 beqz a0,18000c0e <spi_flash_probe+0x4a>
  1803. buf[0] = cmd;
  1804. 18000bd0: f9f00813 li a6,-97
  1805. unsigned char buf[4] = {0};// = {(u8)cmd, 0x00, 0x00, 0x00};
  1806. 18000bd4: c402 sw zero,8(sp)
  1807. ret1 = spi_xfer(spi, 1*8, &buf[0], NULL, SPI_XFER_BEGIN, 8);
  1808. 18000bd6: 47a1 li a5,8
  1809. 18000bd8: 4705 li a4,1
  1810. 18000bda: 4681 li a3,0
  1811. 18000bdc: 0030 addi a2,sp,8
  1812. 18000bde: 45a1 li a1,8
  1813. 18000be0: 842a mv s0,a0
  1814. buf[0] = cmd;
  1815. 18000be2: 01010423 sb a6,8(sp)
  1816. ret1 = spi_xfer(spi, 1*8, &buf[0], NULL, SPI_XFER_BEGIN, 8);
  1817. 18000be6: eefff0ef jal ra,18000ad4 <spi_xfer>
  1818. ret2 = spi_xfer(spi, len*8, NULL, response, SPI_XFER_END, 8);
  1819. 18000bea: 45e1 li a1,24
  1820. 18000bec: 47a1 li a5,8
  1821. 18000bee: 4709 li a4,2
  1822. 18000bf0: 868a mv a3,sp
  1823. 18000bf2: 4601 li a2,0
  1824. 18000bf4: 8522 mv a0,s0
  1825. 18000bf6: edfff0ef jal ra,18000ad4 <spi_xfer>
  1826. goto err_read_id;
  1827. }
  1828. //print_id(idcode, sizeof(idcode));
  1829. flash = spi_flash_probe_nor(spi,idcode);
  1830. 18000bfa: 858a mv a1,sp
  1831. 18000bfc: 8522 mv a0,s0
  1832. 18000bfe: ef5ff0ef jal ra,18000af2 <spi_flash_probe_nor>
  1833. if (!flash)
  1834. 18000c02: c111 beqz a0,18000c06 <spi_flash_probe+0x42>
  1835. {
  1836. goto err_manufacturer_probe;
  1837. }
  1838. flash->spi = spi;
  1839. 18000c04: e100 sd s0,0(a0)
  1840. err_manufacturer_probe:
  1841. err_read_id:
  1842. return NULL;
  1843. }
  1844. 18000c06: 60e2 ld ra,24(sp)
  1845. 18000c08: 6442 ld s0,16(sp)
  1846. 18000c0a: 6105 addi sp,sp,32
  1847. 18000c0c: 8082 ret
  1848. 18000c0e: 60e2 ld ra,24(sp)
  1849. 18000c10: 6442 ld s0,16(sp)
  1850. return NULL;
  1851. 18000c12: 4501 li a0,0
  1852. }
  1853. 18000c14: 6105 addi sp,sp,32
  1854. 18000c16: 8082 ret
  1855. 0000000018000c18 <cadence_spi_xfer>:
  1856. }
  1857. static int cadence_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
  1858. const void *dout, void *din, unsigned long flags)
  1859. {
  1860. 18000c18: 715d addi sp,sp,-80
  1861. 18000c1a: e0a2 sd s0,64(sp)
  1862. 18000c1c: fc26 sd s1,56(sp)
  1863. 18000c1e: f84a sd s2,48(sp)
  1864. 18000c20: f44e sd s3,40(sp)
  1865. 18000c22: ec56 sd s5,24(sp)
  1866. 18000c24: e85a sd s6,16(sp)
  1867. 18000c26: e45e sd s7,8(sp)
  1868. 18000c28: e062 sd s8,0(sp)
  1869. struct cadence_spi_platdata *plat = &cadence_plat;
  1870. struct cadence_spi_priv *priv = &spi_priv;
  1871. void * base = priv->regbase;
  1872. 18000c2a: 0000fb17 auipc s6,0xf
  1873. 18000c2e: 426b0b13 addi s6,s6,1062 # 18010050 <spi_priv>
  1874. {
  1875. 18000c32: e486 sd ra,72(sp)
  1876. 18000c34: f052 sd s4,32(sp)
  1877. u8 *cmd_buf = priv->cmd_buf;
  1878. unsigned int data_bytes = 0;
  1879. int err = 0;
  1880. u32 mode = CQSPI_STIG_WRITE;
  1881. if (flags & SPI_XFER_BEGIN) {
  1882. 18000c36: 00177c13 andi s8,a4,1
  1883. void * base = priv->regbase;
  1884. 18000c3a: 000b3b83 ld s7,0(s6)
  1885. {
  1886. 18000c3e: 843a mv s0,a4
  1887. 18000c40: 892a mv s2,a0
  1888. 18000c42: 84ae mv s1,a1
  1889. 18000c44: 89b2 mv s3,a2
  1890. 18000c46: 8ab6 mv s5,a3
  1891. if (flags & SPI_XFER_BEGIN) {
  1892. 18000c48: 0a0c1f63 bnez s8,18000d06 <cadence_spi_xfer+0xee>
  1893. /* copy command to local buffer */
  1894. priv->cmd_len = bitlen / 8;
  1895. sys_memcpy(cmd_buf, dout, priv->cmd_len);
  1896. }
  1897. if (flags == (SPI_XFER_BEGIN | SPI_XFER_END))
  1898. 18000c4c: 478d li a5,3
  1899. data_bytes = bitlen / 8;
  1900. }
  1901. //uart_printf("%s: len=%d [bytes]\n", __func__, data_bytes);
  1902. /* Set Chip select */
  1903. cadence_qspi_apb_chipselect(base, slave->cs,
  1904. 18000c4e: 00c92583 lw a1,12(s2)
  1905. CONFIG_CQSPI_DECODER);
  1906. if ((flags & SPI_XFER_END) || (flags == 0)) {
  1907. 18000c52: 00247a13 andi s4,s0,2
  1908. cadence_qspi_apb_chipselect(base, slave->cs,
  1909. 18000c56: 4601 li a2,0
  1910. 18000c58: 855e mv a0,s7
  1911. if (flags == (SPI_XFER_BEGIN | SPI_XFER_END))
  1912. 18000c5a: 08f40563 beq s0,a5,18000ce4 <cadence_spi_xfer+0xcc>
  1913. data_bytes = bitlen / 8;
  1914. 18000c5e: 0034d49b srliw s1,s1,0x3
  1915. cadence_qspi_apb_chipselect(base, slave->cs,
  1916. 18000c62: 74f000ef jal ra,18001bb0 <cadence_qspi_apb_chipselect>
  1917. if ((flags & SPI_XFER_END) || (flags == 0)) {
  1918. 18000c66: 000a1463 bnez s4,18000c6e <cadence_spi_xfer+0x56>
  1919. int err = 0;
  1920. 18000c6a: 4901 li s2,0
  1921. if ((flags & SPI_XFER_END) || (flags == 0)) {
  1922. 18000c6c: ec39 bnez s0,18000cca <cadence_spi_xfer+0xb2>
  1923. if (priv->cmd_len == 0) {
  1924. 18000c6e: 010b2583 lw a1,16(s6)
  1925. 18000c72: 10058163 beqz a1,18000d74 <cadence_spi_xfer+0x15c>
  1926. //uart_printf("QSPI: Error, command is empty.\n");
  1927. return -1;
  1928. }
  1929. if (din && data_bytes) {
  1930. 18000c76: 0c0a8263 beqz s5,18000d3a <cadence_spi_xfer+0x122>
  1931. 18000c7a: c0e1 beqz s1,18000d3a <cadence_spi_xfer+0x122>
  1932. /* read */
  1933. /* Use STIG if no address. */
  1934. if (!CQSPI_IS_ADDR(priv->cmd_len))
  1935. 18000c7c: 4785 li a5,1
  1936. 18000c7e: 0af58263 beq a1,a5,18000d22 <cadence_spi_xfer+0x10a>
  1937. err = cadence_qspi_apb_command_write(base,
  1938. priv->cmd_len, cmd_buf,
  1939. data_bytes, dout);
  1940. break;
  1941. case CQSPI_INDIRECT_READ:
  1942. err = cadence_qspi_apb_indirect_read_setup(plat,
  1943. 18000c82: 0000f617 auipc a2,0xf
  1944. 18000c86: 3e260613 addi a2,a2,994 # 18010064 <spi_priv+0x14>
  1945. 18000c8a: 0000f517 auipc a0,0xf
  1946. 18000c8e: 40e50513 addi a0,a0,1038 # 18010098 <cadence_plat>
  1947. 18000c92: 1b2010ef jal ra,18001e44 <cadence_qspi_apb_indirect_read_setup>
  1948. 18000c96: 892a mv s2,a0
  1949. priv->cmd_len, cmd_buf);
  1950. if (!err) {
  1951. 18000c98: e911 bnez a0,18000cac <cadence_spi_xfer+0x94>
  1952. err = cadence_qspi_apb_indirect_read_execute
  1953. 18000c9a: 8656 mv a2,s5
  1954. 18000c9c: 85a6 mv a1,s1
  1955. 18000c9e: 0000f517 auipc a0,0xf
  1956. 18000ca2: 3fa50513 addi a0,a0,1018 # 18010098 <cadence_plat>
  1957. 18000ca6: 248010ef jal ra,18001eee <cadence_qspi_apb_indirect_read_execute>
  1958. 18000caa: 892a mv s2,a0
  1959. default:
  1960. err = -1;
  1961. break;
  1962. }
  1963. if (flags & SPI_XFER_END) {
  1964. 18000cac: 000a0f63 beqz s4,18000cca <cadence_spi_xfer+0xb2>
  1965. /* clear command buffer */
  1966. sys_memset(cmd_buf, 0, sizeof(priv->cmd_buf));
  1967. 18000cb0: 02000613 li a2,32
  1968. 18000cb4: 4581 li a1,0
  1969. 18000cb6: 0000f517 auipc a0,0xf
  1970. 18000cba: 3ae50513 addi a0,a0,942 # 18010064 <spi_priv+0x14>
  1971. 18000cbe: dc9ff0ef jal ra,18000a86 <sys_memset>
  1972. priv->cmd_len = 0;
  1973. 18000cc2: 0000f797 auipc a5,0xf
  1974. 18000cc6: 3807af23 sw zero,926(a5) # 18010060 <spi_priv+0x10>
  1975. }
  1976. }
  1977. return err;
  1978. }
  1979. 18000cca: 60a6 ld ra,72(sp)
  1980. 18000ccc: 6406 ld s0,64(sp)
  1981. 18000cce: 74e2 ld s1,56(sp)
  1982. 18000cd0: 79a2 ld s3,40(sp)
  1983. 18000cd2: 7a02 ld s4,32(sp)
  1984. 18000cd4: 6ae2 ld s5,24(sp)
  1985. 18000cd6: 6b42 ld s6,16(sp)
  1986. 18000cd8: 6ba2 ld s7,8(sp)
  1987. 18000cda: 6c02 ld s8,0(sp)
  1988. 18000cdc: 854a mv a0,s2
  1989. 18000cde: 7942 ld s2,48(sp)
  1990. 18000ce0: 6161 addi sp,sp,80
  1991. 18000ce2: 8082 ret
  1992. cadence_qspi_apb_chipselect(base, slave->cs,
  1993. 18000ce4: 6cd000ef jal ra,18001bb0 <cadence_qspi_apb_chipselect>
  1994. if (priv->cmd_len == 0) {
  1995. 18000ce8: 010b2583 lw a1,16(s6)
  1996. 18000cec: c5c1 beqz a1,18000d74 <cadence_spi_xfer+0x15c>
  1997. data_bytes = 0;
  1998. 18000cee: 4481 li s1,0
  1999. err = cadence_qspi_apb_command_write(base,
  2000. 18000cf0: 874e mv a4,s3
  2001. 18000cf2: 86a6 mv a3,s1
  2002. 18000cf4: 0000f617 auipc a2,0xf
  2003. 18000cf8: 37060613 addi a2,a2,880 # 18010064 <spi_priv+0x14>
  2004. 18000cfc: 855e mv a0,s7
  2005. 18000cfe: 03a010ef jal ra,18001d38 <cadence_qspi_apb_command_write>
  2006. 18000d02: 892a mv s2,a0
  2007. break;
  2008. 18000d04: b765 j 18000cac <cadence_spi_xfer+0x94>
  2009. priv->cmd_len = bitlen / 8;
  2010. 18000d06: 0035d79b srliw a5,a1,0x3
  2011. sys_memcpy(cmd_buf, dout, priv->cmd_len);
  2012. 18000d0a: 0035d61b srliw a2,a1,0x3
  2013. 18000d0e: 0000f517 auipc a0,0xf
  2014. 18000d12: 35650513 addi a0,a0,854 # 18010064 <spi_priv+0x14>
  2015. 18000d16: 85ce mv a1,s3
  2016. priv->cmd_len = bitlen / 8;
  2017. 18000d18: 00fb2823 sw a5,16(s6)
  2018. sys_memcpy(cmd_buf, dout, priv->cmd_len);
  2019. 18000d1c: cf3ff0ef jal ra,18000a0e <sys_memcpy>
  2020. 18000d20: b735 j 18000c4c <cadence_spi_xfer+0x34>
  2021. err = cadence_qspi_apb_command_read(
  2022. 18000d22: 8756 mv a4,s5
  2023. 18000d24: 86a6 mv a3,s1
  2024. 18000d26: 0000f617 auipc a2,0xf
  2025. 18000d2a: 33e60613 addi a2,a2,830 # 18010064 <spi_priv+0x14>
  2026. 18000d2e: 4585 li a1,1
  2027. 18000d30: 855e mv a0,s7
  2028. 18000d32: 75d000ef jal ra,18001c8e <cadence_qspi_apb_command_read>
  2029. 18000d36: 892a mv s2,a0
  2030. break;
  2031. 18000d38: bf95 j 18000cac <cadence_spi_xfer+0x94>
  2032. } else if (dout && !(flags & SPI_XFER_BEGIN)) {
  2033. 18000d3a: fa098be3 beqz s3,18000cf0 <cadence_spi_xfer+0xd8>
  2034. 18000d3e: fa0c19e3 bnez s8,18000cf0 <cadence_spi_xfer+0xd8>
  2035. if (!CQSPI_IS_ADDR(priv->cmd_len))
  2036. 18000d42: 4785 li a5,1
  2037. 18000d44: faf586e3 beq a1,a5,18000cf0 <cadence_spi_xfer+0xd8>
  2038. err = cadence_qspi_apb_indirect_write_setup
  2039. 18000d48: 0000f617 auipc a2,0xf
  2040. 18000d4c: 31c60613 addi a2,a2,796 # 18010064 <spi_priv+0x14>
  2041. 18000d50: 0000f517 auipc a0,0xf
  2042. 18000d54: 34850513 addi a0,a0,840 # 18010098 <cadence_plat>
  2043. 18000d58: 2f4010ef jal ra,1800204c <cadence_qspi_apb_indirect_write_setup>
  2044. 18000d5c: 892a mv s2,a0
  2045. if (!err) {
  2046. 18000d5e: f539 bnez a0,18000cac <cadence_spi_xfer+0x94>
  2047. err = cadence_qspi_apb_indirect_write_execute
  2048. 18000d60: 864e mv a2,s3
  2049. 18000d62: 85a6 mv a1,s1
  2050. 18000d64: 0000f517 auipc a0,0xf
  2051. 18000d68: 33450513 addi a0,a0,820 # 18010098 <cadence_plat>
  2052. 18000d6c: 376010ef jal ra,180020e2 <cadence_qspi_apb_indirect_write_execute>
  2053. 18000d70: 892a mv s2,a0
  2054. 18000d72: bf2d j 18000cac <cadence_spi_xfer+0x94>
  2055. return -1;
  2056. 18000d74: 597d li s2,-1
  2057. 18000d76: bf91 j 18000cca <cadence_spi_xfer+0xb2>
  2058. 0000000018000d78 <cadence_spi_write_speed.isra.0>:
  2059. static int cadence_spi_write_speed(unsigned int hz)
  2060. 18000d78: 1101 addi sp,sp,-32
  2061. 18000d7a: e822 sd s0,16(sp)
  2062. cadence_qspi_apb_config_baudrate_div(priv->regbase,
  2063. 18000d7c: 0000f417 auipc s0,0xf
  2064. 18000d80: 2d440413 addi s0,s0,724 # 18010050 <spi_priv>
  2065. static int cadence_spi_write_speed(unsigned int hz)
  2066. 18000d84: e426 sd s1,8(sp)
  2067. 18000d86: 84aa mv s1,a0
  2068. cadence_qspi_apb_config_baudrate_div(priv->regbase,
  2069. 18000d88: 6008 ld a0,0(s0)
  2070. static int cadence_spi_write_speed(unsigned int hz)
  2071. 18000d8a: e04a sd s2,0(sp)
  2072. cadence_qspi_apb_config_baudrate_div(priv->regbase,
  2073. 18000d8c: 0ee6b937 lui s2,0xee6b
  2074. 18000d90: 8626 mv a2,s1
  2075. 18000d92: 28090593 addi a1,s2,640 # ee6b280 <__stack_size+0xee6aa80>
  2076. static int cadence_spi_write_speed(unsigned int hz)
  2077. 18000d96: ec06 sd ra,24(sp)
  2078. cadence_qspi_apb_config_baudrate_div(priv->regbase,
  2079. 18000d98: 5a9000ef jal ra,18001b40 <cadence_qspi_apb_config_baudrate_div>
  2080. cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz,
  2081. 18000d9c: 07842803 lw a6,120(s0)
  2082. 18000da0: 587c lw a5,116(s0)
  2083. 18000da2: 5838 lw a4,112(s0)
  2084. 18000da4: 5474 lw a3,108(s0)
  2085. 18000da6: 6008 ld a0,0(s0)
  2086. }
  2087. 18000da8: 6442 ld s0,16(sp)
  2088. 18000daa: 60e2 ld ra,24(sp)
  2089. cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz,
  2090. 18000dac: 8626 mv a2,s1
  2091. 18000dae: 28090593 addi a1,s2,640
  2092. }
  2093. 18000db2: 64a2 ld s1,8(sp)
  2094. 18000db4: 6902 ld s2,0(sp)
  2095. 18000db6: 6105 addi sp,sp,32
  2096. cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz,
  2097. 18000db8: 6430006f j 18001bfa <cadence_qspi_apb_delay>
  2098. 0000000018000dbc <cadence_spi4x_setup_slave>:
  2099. {
  2100. 18000dbc: 7159 addi sp,sp,-112
  2101. 18000dbe: f062 sd s8,32(sp)
  2102. plat->tsd2d_ns = 255;
  2103. 18000dc0: 4785 li a5,1
  2104. plat->block_size = 16;
  2105. 18000dc2: 4865 li a6,25
  2106. {
  2107. 18000dc4: 8c3a mv s8,a4
  2108. plat->max_hz = CADENCE_QSPI_MAX_HZ;
  2109. 18000dc6: 05f5e737 lui a4,0x5f5e
  2110. {
  2111. 18000dca: eca6 sd s1,88(sp)
  2112. plat->tsd2d_ns = 255;
  2113. 18000dcc: 02179313 slli t1,a5,0x21
  2114. spi4slave->base = (void *)QSPI_BASE_ADDR;
  2115. 18000dd0: 0000f497 auipc s1,0xf
  2116. 18000dd4: 28048493 addi s1,s1,640 # 18010050 <spi_priv>
  2117. plat->max_hz = CADENCE_QSPI_MAX_HZ;
  2118. 18000dd8: 10070713 addi a4,a4,256 # 5f5e100 <__stack_size+0x5f5d900>
  2119. plat->tslch_ns = 20;
  2120. 18000ddc: 17a2 slli a5,a5,0x28
  2121. plat->block_size = 16;
  2122. 18000dde: 180e slli a6,a6,0x23
  2123. spi4slave->base = (void *)QSPI_BASE_ADDR;
  2124. 18000de0: 118608b7 lui a7,0x11860
  2125. plat->ahbbase = (void *)QSPI_BASE_AHB_ADDR;
  2126. 18000de4: 20000e37 lui t3,0x20000
  2127. plat->tsd2d_ns = 255;
  2128. 18000de8: 0ff30313 addi t1,t1,255
  2129. plat->tslch_ns = 20;
  2130. 18000dec: 07d1 addi a5,a5,20
  2131. plat->block_size = 16;
  2132. 18000dee: 0841 addi a6,a6,16
  2133. {
  2134. 18000df0: ec66 sd s9,24(sp)
  2135. plat->max_hz = CADENCE_QSPI_MAX_HZ;
  2136. 18000df2: c4b8 sw a4,72(s1)
  2137. {
  2138. 18000df4: 8caa mv s9,a0
  2139. plat->page_size = 256;
  2140. 18000df6: 10000713 li a4,256
  2141. cadence_qspi_apb_controller_disable(priv->regbase);
  2142. 18000dfa: 11860537 lui a0,0x11860
  2143. {
  2144. 18000dfe: f486 sd ra,104(sp)
  2145. spi4slave->base = (void *)QSPI_BASE_ADDR;
  2146. 18000e00: 0914ac23 sw a7,152(s1)
  2147. plat->regbase = (void *)QSPI_BASE_ADDR;
  2148. 18000e04: 0514b823 sd a7,80(s1)
  2149. plat->ahbbase = (void *)QSPI_BASE_AHB_ADDR;
  2150. 18000e08: 05c4bc23 sd t3,88(s1)
  2151. plat->page_size = 256;
  2152. 18000e0c: d0f8 sw a4,100(s1)
  2153. plat->block_size = 16;
  2154. 18000e0e: 0704b423 sd a6,104(s1)
  2155. plat->tsd2d_ns = 255;
  2156. 18000e12: 0664b823 sd t1,112(s1)
  2157. plat->tslch_ns = 20;
  2158. 18000e16: fcbc sd a5,120(s1)
  2159. priv->regbase = plat->regbase;
  2160. 18000e18: 0114b023 sd a7,0(s1)
  2161. priv->ahbbase = plat->ahbbase;
  2162. 18000e1c: 01c4b423 sd t3,8(s1)
  2163. {
  2164. 18000e20: f0a2 sd s0,96(sp)
  2165. 18000e22: e8ca sd s2,80(sp)
  2166. 18000e24: 8436 mv s0,a3
  2167. 18000e26: e4ce sd s3,72(sp)
  2168. 18000e28: f85a sd s6,48(sp)
  2169. 18000e2a: 8932 mv s2,a2
  2170. 18000e2c: 8b2e mv s6,a1
  2171. 18000e2e: e0d2 sd s4,64(sp)
  2172. 18000e30: fc56 sd s5,56(sp)
  2173. 18000e32: f45e sd s7,40(sp)
  2174. 18000e34: e86a sd s10,16(sp)
  2175. cadence_qspi_apb_controller_disable(priv->regbase);
  2176. 18000e36: 4c7000ef jal ra,18001afc <cadence_qspi_apb_controller_disable>
  2177. cadence_qspi_apb_set_clk_mode(priv->regbase, clk_pol, clk_pha);
  2178. 18000e3a: 6088 ld a0,0(s1)
  2179. clk_pol = (mode & SPI_CPOL) ? 1 : 0;
  2180. 18000e3c: 0014559b srliw a1,s0,0x1
  2181. cadence_qspi_apb_set_clk_mode(priv->regbase, clk_pol, clk_pha);
  2182. 18000e40: 00147613 andi a2,s0,1
  2183. 18000e44: 8985 andi a1,a1,1
  2184. 18000e46: 53f000ef jal ra,18001b84 <cadence_qspi_apb_set_clk_mode>
  2185. cadence_qspi_apb_controller_init(plat);
  2186. 18000e4a: 0000f517 auipc a0,0xf
  2187. 18000e4e: 24e50513 addi a0,a0,590 # 18010098 <cadence_plat>
  2188. 18000e52: 5cf000ef jal ra,18001c20 <cadence_qspi_apb_controller_init>
  2189. if (max_hz > plat->max_hz)
  2190. 18000e56: 0484a983 lw s3,72(s1)
  2191. 18000e5a: 01397363 bgeu s2,s3,18000e60 <cadence_spi4x_setup_slave+0xa4>
  2192. 18000e5e: 89ca mv s3,s2
  2193. if (priv->previous_hz != max_hz ||
  2194. 18000e60: 40fc lw a5,68(s1)
  2195. 18000e62: 01379563 bne a5,s3,18000e6c <cadence_spi4x_setup_slave+0xb0>
  2196. 18000e66: 5cdc lw a5,60(s1)
  2197. 18000e68: 11378663 beq a5,s3,18000f74 <cadence_spi4x_setup_slave+0x1b8>
  2198. void * base = priv->regbase;
  2199. 18000e6c: 0004b903 ld s2,0(s1)
  2200. cadence_spi_write_speed(500000);
  2201. 18000e70: 0007a537 lui a0,0x7a
  2202. u8 opcode_rdid = 0x9F;
  2203. 18000e74: f9f00793 li a5,-97
  2204. cadence_spi_write_speed(500000);
  2205. 18000e78: 12050513 addi a0,a0,288 # 7a120 <__stack_size+0x79920>
  2206. u8 opcode_rdid = 0x9F;
  2207. 18000e7c: 00f103a3 sb a5,7(sp)
  2208. unsigned int idcode = 0, temp = 0;
  2209. 18000e80: c402 sw zero,8(sp)
  2210. 18000e82: c602 sw zero,12(sp)
  2211. cadence_spi_write_speed(500000);
  2212. 18000e84: ef5ff0ef jal ra,18000d78 <cadence_spi_write_speed.isra.0>
  2213. cadence_qspi_apb_readdata_capture(base, 1, 0);
  2214. 18000e88: 4601 li a2,0
  2215. 18000e8a: 4585 li a1,1
  2216. 18000e8c: 854a mv a0,s2
  2217. 18000e8e: 47b000ef jal ra,18001b08 <cadence_qspi_apb_readdata_capture>
  2218. cadence_qspi_apb_controller_enable(base);
  2219. 18000e92: 854a mv a0,s2
  2220. 18000e94: 45b000ef jal ra,18001aee <cadence_qspi_apb_controller_enable>
  2221. err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
  2222. 18000e98: 0038 addi a4,sp,8
  2223. 18000e9a: 468d li a3,3
  2224. 18000e9c: 00710613 addi a2,sp,7
  2225. 18000ea0: 4585 li a1,1
  2226. 18000ea2: 854a mv a0,s2
  2227. 18000ea4: 5eb000ef jal ra,18001c8e <cadence_qspi_apb_command_read>
  2228. 18000ea8: 842a mv s0,a0
  2229. if (err) {
  2230. 18000eaa: c105 beqz a0,18000eca <cadence_spi4x_setup_slave+0x10e>
  2231. return NULL;
  2232. 18000eac: 4501 li a0,0
  2233. }
  2234. 18000eae: 70a6 ld ra,104(sp)
  2235. 18000eb0: 7406 ld s0,96(sp)
  2236. 18000eb2: 64e6 ld s1,88(sp)
  2237. 18000eb4: 6946 ld s2,80(sp)
  2238. 18000eb6: 69a6 ld s3,72(sp)
  2239. 18000eb8: 6a06 ld s4,64(sp)
  2240. 18000eba: 7ae2 ld s5,56(sp)
  2241. 18000ebc: 7b42 ld s6,48(sp)
  2242. 18000ebe: 7ba2 ld s7,40(sp)
  2243. 18000ec0: 7c02 ld s8,32(sp)
  2244. 18000ec2: 6ce2 ld s9,24(sp)
  2245. 18000ec4: 6d42 ld s10,16(sp)
  2246. 18000ec6: 6165 addi sp,sp,112
  2247. 18000ec8: 8082 ret
  2248. cadence_spi_write_speed(hz);
  2249. 18000eca: 854e mv a0,s3
  2250. 18000ecc: eadff0ef jal ra,18000d78 <cadence_spi_write_speed.isra.0>
  2251. int err = 0, i, range_lo = -1, range_hi = -1;
  2252. 18000ed0: 5afd li s5,-1
  2253. 18000ed2: 5a7d li s4,-1
  2254. if (range_lo == -1 && temp == idcode) {
  2255. 18000ed4: 5bfd li s7,-1
  2256. for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
  2257. 18000ed6: 4d41 li s10,16
  2258. 18000ed8: a039 j 18000ee6 <cadence_spi4x_setup_slave+0x12a>
  2259. 18000eda: 8aa2 mv s5,s0
  2260. if (range_lo != -1 && temp != idcode) {
  2261. 18000edc: 0af71063 bne a4,a5,18000f7c <cadence_spi4x_setup_slave+0x1c0>
  2262. for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
  2263. 18000ee0: 2405 addiw s0,s0,1
  2264. 18000ee2: 05a40163 beq s0,s10,18000f24 <cadence_spi4x_setup_slave+0x168>
  2265. cadence_qspi_apb_controller_disable(base);
  2266. 18000ee6: 854a mv a0,s2
  2267. 18000ee8: 415000ef jal ra,18001afc <cadence_qspi_apb_controller_disable>
  2268. cadence_qspi_apb_readdata_capture(base, 1, i);
  2269. 18000eec: 0004061b sext.w a2,s0
  2270. 18000ef0: 4585 li a1,1
  2271. 18000ef2: 854a mv a0,s2
  2272. 18000ef4: 415000ef jal ra,18001b08 <cadence_qspi_apb_readdata_capture>
  2273. cadence_qspi_apb_controller_enable(base);
  2274. 18000ef8: 854a mv a0,s2
  2275. 18000efa: 3f5000ef jal ra,18001aee <cadence_qspi_apb_controller_enable>
  2276. err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
  2277. 18000efe: 0078 addi a4,sp,12
  2278. 18000f00: 468d li a3,3
  2279. 18000f02: 00710613 addi a2,sp,7
  2280. 18000f06: 4585 li a1,1
  2281. 18000f08: 854a mv a0,s2
  2282. 18000f0a: 585000ef jal ra,18001c8e <cadence_qspi_apb_command_read>
  2283. if (err) {
  2284. 18000f0e: fd59 bnez a0,18000eac <cadence_spi4x_setup_slave+0xf0>
  2285. if (range_lo == -1 && temp == idcode) {
  2286. 18000f10: 47b2 lw a5,12(sp)
  2287. 18000f12: 4722 lw a4,8(sp)
  2288. 18000f14: fd7a13e3 bne s4,s7,18000eda <cadence_spi4x_setup_slave+0x11e>
  2289. 18000f18: 04f70c63 beq a4,a5,18000f70 <cadence_spi4x_setup_slave+0x1b4>
  2290. 18000f1c: 8aa2 mv s5,s0
  2291. for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
  2292. 18000f1e: 2405 addiw s0,s0,1
  2293. 18000f20: fda413e3 bne s0,s10,18000ee6 <cadence_spi4x_setup_slave+0x12a>
  2294. if (range_lo == -1) {
  2295. 18000f24: 57fd li a5,-1
  2296. 18000f26: 02fa0563 beq s4,a5,18000f50 <cadence_spi4x_setup_slave+0x194>
  2297. cadence_qspi_apb_controller_disable(base);
  2298. 18000f2a: 854a mv a0,s2
  2299. 18000f2c: 3d1000ef jal ra,18001afc <cadence_qspi_apb_controller_disable>
  2300. cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
  2301. 18000f30: 014a8a3b addw s4,s5,s4
  2302. 18000f34: 01fa561b srliw a2,s4,0x1f
  2303. 18000f38: 0146063b addw a2,a2,s4
  2304. 18000f3c: 4016561b sraiw a2,a2,0x1
  2305. 18000f40: 4585 li a1,1
  2306. 18000f42: 854a mv a0,s2
  2307. 18000f44: 3c5000ef jal ra,18001b08 <cadence_qspi_apb_readdata_capture>
  2308. priv->qspi_calibrated_hz = hz;
  2309. 18000f48: 0334ae23 sw s3,60(s1)
  2310. priv->qspi_calibrated_cs = cs;
  2311. 18000f4c: 0564a023 sw s6,64(s1)
  2312. priv->previous_hz = max_hz;
  2313. 18000f50: 0534a223 sw s3,68(s1)
  2314. cadence_qspi_apb_controller_enable(priv->regbase);
  2315. 18000f54: 6088 ld a0,0(s1)
  2316. 18000f56: 399000ef jal ra,18001aee <cadence_qspi_apb_controller_enable>
  2317. return &spi4slave->slave;
  2318. 18000f5a: 0000f517 auipc a0,0xf
  2319. 18000f5e: 17e50513 addi a0,a0,382 # 180100d8 <vic_spi_slave>
  2320. spi4slave->slave.bus = bus;
  2321. 18000f62: 0994a423 sw s9,136(s1)
  2322. spi4slave->slave.cs = cs;
  2323. 18000f66: 0964aa23 sw s6,148(s1)
  2324. spi4slave->slave.bus_width= fifo_width;
  2325. 18000f6a: 0984a623 sw s8,140(s1)
  2326. return &spi4slave->slave;
  2327. 18000f6e: b781 j 18000eae <cadence_spi4x_setup_slave+0xf2>
  2328. 18000f70: 8a22 mv s4,s0
  2329. 18000f72: b7bd j 18000ee0 <cadence_spi4x_setup_slave+0x124>
  2330. priv->qspi_calibrated_hz != max_hz ||
  2331. 18000f74: 40bc lw a5,64(s1)
  2332. 18000f76: ef679be3 bne a5,s6,18000e6c <cadence_spi4x_setup_slave+0xb0>
  2333. 18000f7a: bfe9 j 18000f54 <cadence_spi4x_setup_slave+0x198>
  2334. range_hi = i - 1;
  2335. 18000f7c: fff40a9b addiw s5,s0,-1
  2336. if (range_lo == -1) {
  2337. 18000f80: b76d j 18000f2a <cadence_spi4x_setup_slave+0x16e>
  2338. 0000000018000f82 <cadence_qspi_init>:
  2339. _ASSERT_RESET_rstgen_rstn_qspi_apb_;
  2340. _CLEAR_RESET_rstgen_rstn_qspi_ahb_;
  2341. _CLEAR_RESET_rstgen_rstn_qspi_core_;
  2342. _CLEAR_RESET_rstgen_rstn_qspi_apb_;
  2343. #endif
  2344. plat->bit_mode = mode;
  2345. 18000f82: 0000f797 auipc a5,0xf
  2346. 18000f86: 0ce78793 addi a5,a5,206 # 18010050 <spi_priv>
  2347. {
  2348. 18000f8a: 872e mv a4,a1
  2349. plat->bit_mode = mode;
  2350. 18000f8c: 08e7a023 sw a4,128(a5)
  2351. func = &cadence_spi4x_func;
  2352. func->setup_slave = cadence_spi4x_setup_slave;
  2353. 18000f90: 00000717 auipc a4,0x0
  2354. 18000f94: e2c70713 addi a4,a4,-468 # 18000dbc <cadence_spi4x_setup_slave>
  2355. 18000f98: f3d8 sd a4,160(a5)
  2356. func->spi_xfer = cadence_spi_xfer;
  2357. spi_register(bus, func);
  2358. 18000f9a: 0000f597 auipc a1,0xf
  2359. 18000f9e: 15658593 addi a1,a1,342 # 180100f0 <cadence_spi4x_func>
  2360. func->spi_xfer = cadence_spi_xfer;
  2361. 18000fa2: 00000717 auipc a4,0x0
  2362. 18000fa6: c7670713 addi a4,a4,-906 # 18000c18 <cadence_spi_xfer>
  2363. 18000faa: f7d8 sd a4,168(a5)
  2364. spi_register(bus, func);
  2365. 18000fac: bcd5 j 18000aa0 <spi_register>
  2366. 0000000018000fae <spi_flash_read_write>:
  2367. int ret;
  2368. if (data_len == 0)
  2369. flags |= SPI_XFER_END;
  2370. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  2371. 18000fae: 0036181b slliw a6,a2,0x3
  2372. {
  2373. 18000fb2: 862e mv a2,a1
  2374. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  2375. 18000fb4: 0008059b sext.w a1,a6
  2376. if (data_len == 0)
  2377. 18000fb8: e789 bnez a5,18000fc2 <spi_flash_read_write+0x14>
  2378. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  2379. 18000fba: 47a1 li a5,8
  2380. 18000fbc: 470d li a4,3
  2381. 18000fbe: 4681 li a3,0
  2382. 18000fc0: be11 j 18000ad4 <spi_xfer>
  2383. {
  2384. 18000fc2: 7179 addi sp,sp,-48
  2385. 18000fc4: f022 sd s0,32(sp)
  2386. 18000fc6: e84a sd s2,16(sp)
  2387. 18000fc8: e44e sd s3,8(sp)
  2388. 18000fca: 843e mv s0,a5
  2389. 18000fcc: 8936 mv s2,a3
  2390. 18000fce: 89ba mv s3,a4
  2391. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  2392. 18000fd0: 47a1 li a5,8
  2393. 18000fd2: 4705 li a4,1
  2394. 18000fd4: 4681 li a3,0
  2395. {
  2396. 18000fd6: ec26 sd s1,24(sp)
  2397. 18000fd8: f406 sd ra,40(sp)
  2398. 18000fda: 84aa mv s1,a0
  2399. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  2400. 18000fdc: af9ff0ef jal ra,18000ad4 <spi_xfer>
  2401. if (ret)
  2402. 18000fe0: c901 beqz a0,18000ff0 <spi_flash_read_write+0x42>
  2403. {
  2404. ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END, SPI_DATAMODE_8);
  2405. }
  2406. return ret;
  2407. }
  2408. 18000fe2: 70a2 ld ra,40(sp)
  2409. 18000fe4: 7402 ld s0,32(sp)
  2410. 18000fe6: 64e2 ld s1,24(sp)
  2411. 18000fe8: 6942 ld s2,16(sp)
  2412. 18000fea: 69a2 ld s3,8(sp)
  2413. 18000fec: 6145 addi sp,sp,48
  2414. 18000fee: 8082 ret
  2415. ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END, SPI_DATAMODE_8);
  2416. 18000ff0: 0034159b slliw a1,s0,0x3
  2417. }
  2418. 18000ff4: 7402 ld s0,32(sp)
  2419. 18000ff6: 70a2 ld ra,40(sp)
  2420. ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END, SPI_DATAMODE_8);
  2421. 18000ff8: 86ce mv a3,s3
  2422. 18000ffa: 864a mv a2,s2
  2423. }
  2424. 18000ffc: 69a2 ld s3,8(sp)
  2425. 18000ffe: 6942 ld s2,16(sp)
  2426. ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END, SPI_DATAMODE_8);
  2427. 18001000: 8526 mv a0,s1
  2428. }
  2429. 18001002: 64e2 ld s1,24(sp)
  2430. ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END, SPI_DATAMODE_8);
  2431. 18001004: 47a1 li a5,8
  2432. 18001006: 4709 li a4,2
  2433. }
  2434. 18001008: 6145 addi sp,sp,48
  2435. ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END, SPI_DATAMODE_8);
  2436. 1800100a: b4e9 j 18000ad4 <spi_xfer>
  2437. 000000001800100c <spi_flash_cmd>:
  2438. int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, u32 len)
  2439. {
  2440. 1800100c: 7179 addi sp,sp,-48
  2441. 1800100e: f406 sd ra,40(sp)
  2442. 18001010: f022 sd s0,32(sp)
  2443. 18001012: ec26 sd s1,24(sp)
  2444. 18001014: e84a sd s2,16(sp)
  2445. 18001016: 00b107a3 sb a1,15(sp)
  2446. if (data_len == 0)
  2447. 1800101a: ee91 bnez a3,18001036 <spi_flash_cmd+0x2a>
  2448. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  2449. 1800101c: 47a1 li a5,8
  2450. 1800101e: 470d li a4,3
  2451. 18001020: 00f10613 addi a2,sp,15
  2452. 18001024: 45a1 li a1,8
  2453. 18001026: aafff0ef jal ra,18000ad4 <spi_xfer>
  2454. return spi_flash_cmd_read(spi, &cmd, 1, response, len);
  2455. }
  2456. 1800102a: 70a2 ld ra,40(sp)
  2457. 1800102c: 7402 ld s0,32(sp)
  2458. 1800102e: 64e2 ld s1,24(sp)
  2459. 18001030: 6942 ld s2,16(sp)
  2460. 18001032: 6145 addi sp,sp,48
  2461. 18001034: 8082 ret
  2462. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  2463. 18001036: 8436 mv s0,a3
  2464. 18001038: 8932 mv s2,a2
  2465. 1800103a: 47a1 li a5,8
  2466. 1800103c: 4705 li a4,1
  2467. 1800103e: 4681 li a3,0
  2468. 18001040: 00f10613 addi a2,sp,15
  2469. 18001044: 45a1 li a1,8
  2470. 18001046: 84aa mv s1,a0
  2471. 18001048: a8dff0ef jal ra,18000ad4 <spi_xfer>
  2472. if (ret)
  2473. 1800104c: fd79 bnez a0,1800102a <spi_flash_cmd+0x1e>
  2474. ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END, SPI_DATAMODE_8);
  2475. 1800104e: 0034159b slliw a1,s0,0x3
  2476. 18001052: 86ca mv a3,s2
  2477. 18001054: 8526 mv a0,s1
  2478. 18001056: 47a1 li a5,8
  2479. 18001058: 4709 li a4,2
  2480. 1800105a: 4601 li a2,0
  2481. 1800105c: a79ff0ef jal ra,18000ad4 <spi_xfer>
  2482. }
  2483. 18001060: 70a2 ld ra,40(sp)
  2484. 18001062: 7402 ld s0,32(sp)
  2485. 18001064: 64e2 ld s1,24(sp)
  2486. 18001066: 6942 ld s2,16(sp)
  2487. 18001068: 6145 addi sp,sp,48
  2488. 1800106a: 8082 ret
  2489. 000000001800106c <spi_flash_cmd_read>:
  2490. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  2491. 1800106c: 0036179b slliw a5,a2,0x3
  2492. int spi_flash_cmd_read(struct spi_slave *spi, u8 *cmd,
  2493. u32 cmd_len, void *data, u32 data_len)
  2494. {
  2495. 18001070: 862e mv a2,a1
  2496. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  2497. 18001072: 0007859b sext.w a1,a5
  2498. if (data_len == 0)
  2499. 18001076: e709 bnez a4,18001080 <spi_flash_cmd_read+0x14>
  2500. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  2501. 18001078: 47a1 li a5,8
  2502. 1800107a: 470d li a4,3
  2503. 1800107c: 4681 li a3,0
  2504. 1800107e: bc99 j 18000ad4 <spi_xfer>
  2505. {
  2506. 18001080: 1101 addi sp,sp,-32
  2507. 18001082: e822 sd s0,16(sp)
  2508. 18001084: e04a sd s2,0(sp)
  2509. 18001086: 843a mv s0,a4
  2510. 18001088: 8936 mv s2,a3
  2511. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  2512. 1800108a: 47a1 li a5,8
  2513. 1800108c: 4705 li a4,1
  2514. 1800108e: 4681 li a3,0
  2515. {
  2516. 18001090: e426 sd s1,8(sp)
  2517. 18001092: ec06 sd ra,24(sp)
  2518. 18001094: 84aa mv s1,a0
  2519. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  2520. 18001096: a3fff0ef jal ra,18000ad4 <spi_xfer>
  2521. if (ret)
  2522. 1800109a: c519 beqz a0,180010a8 <spi_flash_cmd_read+0x3c>
  2523. return spi_flash_read_write(spi, cmd, cmd_len, NULL, data, data_len);
  2524. }
  2525. 1800109c: 60e2 ld ra,24(sp)
  2526. 1800109e: 6442 ld s0,16(sp)
  2527. 180010a0: 64a2 ld s1,8(sp)
  2528. 180010a2: 6902 ld s2,0(sp)
  2529. 180010a4: 6105 addi sp,sp,32
  2530. 180010a6: 8082 ret
  2531. ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END, SPI_DATAMODE_8);
  2532. 180010a8: 0034159b slliw a1,s0,0x3
  2533. }
  2534. 180010ac: 6442 ld s0,16(sp)
  2535. 180010ae: 60e2 ld ra,24(sp)
  2536. ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END, SPI_DATAMODE_8);
  2537. 180010b0: 86ca mv a3,s2
  2538. 180010b2: 8526 mv a0,s1
  2539. }
  2540. 180010b4: 6902 ld s2,0(sp)
  2541. 180010b6: 64a2 ld s1,8(sp)
  2542. ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END, SPI_DATAMODE_8);
  2543. 180010b8: 47a1 li a5,8
  2544. 180010ba: 4709 li a4,2
  2545. 180010bc: 4601 li a2,0
  2546. }
  2547. 180010be: 6105 addi sp,sp,32
  2548. ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END, SPI_DATAMODE_8);
  2549. 180010c0: bc11 j 18000ad4 <spi_xfer>
  2550. 00000000180010c2 <spi_flash_cmd_write>:
  2551. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  2552. 180010c2: 0036179b slliw a5,a2,0x3
  2553. int spi_flash_cmd_write(struct spi_slave *spi, u8 *cmd, u32 cmd_len,
  2554. void *data, u32 data_len)
  2555. {
  2556. 180010c6: 862e mv a2,a1
  2557. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  2558. 180010c8: 0007859b sext.w a1,a5
  2559. if (data_len == 0)
  2560. 180010cc: e709 bnez a4,180010d6 <spi_flash_cmd_write+0x14>
  2561. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  2562. 180010ce: 47a1 li a5,8
  2563. 180010d0: 470d li a4,3
  2564. 180010d2: 4681 li a3,0
  2565. 180010d4: b401 j 18000ad4 <spi_xfer>
  2566. {
  2567. 180010d6: 1101 addi sp,sp,-32
  2568. 180010d8: e822 sd s0,16(sp)
  2569. 180010da: e04a sd s2,0(sp)
  2570. 180010dc: 843a mv s0,a4
  2571. 180010de: 8936 mv s2,a3
  2572. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  2573. 180010e0: 47a1 li a5,8
  2574. 180010e2: 4705 li a4,1
  2575. 180010e4: 4681 li a3,0
  2576. {
  2577. 180010e6: e426 sd s1,8(sp)
  2578. 180010e8: ec06 sd ra,24(sp)
  2579. 180010ea: 84aa mv s1,a0
  2580. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  2581. 180010ec: 9e9ff0ef jal ra,18000ad4 <spi_xfer>
  2582. if (ret)
  2583. 180010f0: c519 beqz a0,180010fe <spi_flash_cmd_write+0x3c>
  2584. return spi_flash_read_write(spi, cmd, cmd_len, data, NULL, data_len);
  2585. }
  2586. 180010f2: 60e2 ld ra,24(sp)
  2587. 180010f4: 6442 ld s0,16(sp)
  2588. 180010f6: 64a2 ld s1,8(sp)
  2589. 180010f8: 6902 ld s2,0(sp)
  2590. 180010fa: 6105 addi sp,sp,32
  2591. 180010fc: 8082 ret
  2592. ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END, SPI_DATAMODE_8);
  2593. 180010fe: 0034159b slliw a1,s0,0x3
  2594. }
  2595. 18001102: 6442 ld s0,16(sp)
  2596. 18001104: 60e2 ld ra,24(sp)
  2597. ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END, SPI_DATAMODE_8);
  2598. 18001106: 864a mv a2,s2
  2599. 18001108: 8526 mv a0,s1
  2600. }
  2601. 1800110a: 6902 ld s2,0(sp)
  2602. 1800110c: 64a2 ld s1,8(sp)
  2603. ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END, SPI_DATAMODE_8);
  2604. 1800110e: 47a1 li a5,8
  2605. 18001110: 4709 li a4,2
  2606. 18001112: 4681 li a3,0
  2607. }
  2608. 18001114: 6105 addi sp,sp,32
  2609. ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END, SPI_DATAMODE_8);
  2610. 18001116: ba7d j 18000ad4 <spi_xfer>
  2611. 0000000018001118 <spi_flash_cmd_write_enable>:
  2612. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  2613. 18001118: 6108 ld a0,0(a0)
  2614. int spi_flash_cmd_write_enable(struct spi_flash *flash)
  2615. {
  2616. 1800111a: 1101 addi sp,sp,-32
  2617. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  2618. 1800111c: 00f10613 addi a2,sp,15
  2619. 18001120: 4819 li a6,6
  2620. 18001122: 47a1 li a5,8
  2621. 18001124: 470d li a4,3
  2622. 18001126: 4681 li a3,0
  2623. 18001128: 45a1 li a1,8
  2624. {
  2625. 1800112a: ec06 sd ra,24(sp)
  2626. 1800112c: 010107a3 sb a6,15(sp)
  2627. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  2628. 18001130: 9a5ff0ef jal ra,18000ad4 <spi_xfer>
  2629. return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, (void*)NULL, 0);
  2630. }
  2631. 18001134: 60e2 ld ra,24(sp)
  2632. 18001136: 6105 addi sp,sp,32
  2633. 18001138: 8082 ret
  2634. 000000001800113a <spi_flash_cmd_write_status_enable>:
  2635. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  2636. 1800113a: 6108 ld a0,0(a0)
  2637. int spi_flash_cmd_write_status_enable(struct spi_flash *flash)
  2638. {
  2639. 1800113c: 1101 addi sp,sp,-32
  2640. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  2641. 1800113e: 00f10613 addi a2,sp,15
  2642. 18001142: 05000813 li a6,80
  2643. 18001146: 47a1 li a5,8
  2644. 18001148: 470d li a4,3
  2645. 1800114a: 4681 li a3,0
  2646. 1800114c: 45a1 li a1,8
  2647. {
  2648. 1800114e: ec06 sd ra,24(sp)
  2649. 18001150: 010107a3 sb a6,15(sp)
  2650. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  2651. 18001154: 981ff0ef jal ra,18000ad4 <spi_xfer>
  2652. return spi_flash_cmd(flash->spi, CMD_STATUS_ENABLE, (void*)NULL, 0);
  2653. }
  2654. 18001158: 60e2 ld ra,24(sp)
  2655. 1800115a: 6105 addi sp,sp,32
  2656. 1800115c: 8082 ret
  2657. 000000001800115e <spi_flash_cmd_write_disable>:
  2658. int spi_flash_cmd_write_disable(struct spi_slave *spi)
  2659. {
  2660. 1800115e: 1101 addi sp,sp,-32
  2661. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  2662. 18001160: 00f10613 addi a2,sp,15
  2663. 18001164: 4811 li a6,4
  2664. 18001166: 47a1 li a5,8
  2665. 18001168: 470d li a4,3
  2666. 1800116a: 4681 li a3,0
  2667. 1800116c: 45a1 li a1,8
  2668. {
  2669. 1800116e: ec06 sd ra,24(sp)
  2670. 18001170: 010107a3 sb a6,15(sp)
  2671. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  2672. 18001174: 961ff0ef jal ra,18000ad4 <spi_xfer>
  2673. return spi_flash_cmd(spi, CMD_WRITE_DISABLE, (void*)NULL, 0);
  2674. }
  2675. 18001178: 60e2 ld ra,24(sp)
  2676. 1800117a: 6105 addi sp,sp,32
  2677. 1800117c: 8082 ret
  2678. 000000001800117e <spi_flash_cmd_read_status>:
  2679. int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *cmd, u32 cmd_len, u8 *status)
  2680. {
  2681. 1800117e: 1101 addi sp,sp,-32
  2682. 18001180: e426 sd s1,8(sp)
  2683. struct spi_slave *spi = flash->spi;
  2684. 18001182: 6104 ld s1,0(a0)
  2685. {
  2686. 18001184: 8532 mv a0,a2
  2687. 18001186: e822 sd s0,16(sp)
  2688. 18001188: 862e mv a2,a1
  2689. 1800118a: 8436 mv s0,a3
  2690. int ret;
  2691. ret = spi_xfer(spi, 8*cmd_len, cmd, NULL, SPI_XFER_BEGIN, SPI_DATAMODE_8);
  2692. 1800118c: 0035159b slliw a1,a0,0x3
  2693. 18001190: 47a1 li a5,8
  2694. 18001192: 4705 li a4,1
  2695. 18001194: 4681 li a3,0
  2696. 18001196: 8526 mv a0,s1
  2697. {
  2698. 18001198: ec06 sd ra,24(sp)
  2699. ret = spi_xfer(spi, 8*cmd_len, cmd, NULL, SPI_XFER_BEGIN, SPI_DATAMODE_8);
  2700. 1800119a: 93bff0ef jal ra,18000ad4 <spi_xfer>
  2701. if (ret) {
  2702. 1800119e: c511 beqz a0,180011aa <spi_flash_cmd_read_status+0x2c>
  2703. //uart_printf("status = 0x%x\r\n", status[0]);
  2704. if (ret)
  2705. return ret;
  2706. return 0;
  2707. }
  2708. 180011a0: 60e2 ld ra,24(sp)
  2709. 180011a2: 6442 ld s0,16(sp)
  2710. 180011a4: 64a2 ld s1,8(sp)
  2711. 180011a6: 6105 addi sp,sp,32
  2712. 180011a8: 8082 ret
  2713. ret = spi_xfer(spi, 8*1, NULL, status, SPI_XFER_END, SPI_DATAMODE_8);
  2714. 180011aa: 86a2 mv a3,s0
  2715. }
  2716. 180011ac: 6442 ld s0,16(sp)
  2717. 180011ae: 60e2 ld ra,24(sp)
  2718. ret = spi_xfer(spi, 8*1, NULL, status, SPI_XFER_END, SPI_DATAMODE_8);
  2719. 180011b0: 8526 mv a0,s1
  2720. }
  2721. 180011b2: 64a2 ld s1,8(sp)
  2722. ret = spi_xfer(spi, 8*1, NULL, status, SPI_XFER_END, SPI_DATAMODE_8);
  2723. 180011b4: 47a1 li a5,8
  2724. 180011b6: 4709 li a4,2
  2725. 180011b8: 4601 li a2,0
  2726. 180011ba: 45a1 li a1,8
  2727. }
  2728. 180011bc: 6105 addi sp,sp,32
  2729. ret = spi_xfer(spi, 8*1, NULL, status, SPI_XFER_END, SPI_DATAMODE_8);
  2730. 180011be: ba19 j 18000ad4 <spi_xfer>
  2731. 00000000180011c0 <spi_flash_cmd_poll_bit>:
  2732. int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout,
  2733. u8 cmd, u8 poll_bit)
  2734. {
  2735. 180011c0: 715d addi sp,sp,-80
  2736. 180011c2: e0a2 sd s0,64(sp)
  2737. 180011c4: f84a sd s2,48(sp)
  2738. 180011c6: f44e sd s3,40(sp)
  2739. 180011c8: f052 sd s4,32(sp)
  2740. 180011ca: e486 sd ra,72(sp)
  2741. 180011cc: fc26 sd s1,56(sp)
  2742. 180011ce: 892a mv s2,a0
  2743. 180011d0: 8a2e mv s4,a1
  2744. 180011d2: 89b6 mv s3,a3
  2745. 180011d4: 00c107a3 sb a2,15(sp)
  2746. int ret;
  2747. u8 status;
  2748. u32 status_tmp = 0;
  2749. u32 timebase_1 = 0;
  2750. 180011d8: 4401 li s0,0
  2751. struct spi_slave *spi = flash->spi;
  2752. 180011da: 00093483 ld s1,0(s2)
  2753. ret = spi_xfer(spi, 8*cmd_len, cmd, NULL, SPI_XFER_BEGIN, SPI_DATAMODE_8);
  2754. 180011de: 47a1 li a5,8
  2755. 180011e0: 4705 li a4,1
  2756. 180011e2: 4681 li a3,0
  2757. 180011e4: 00f10613 addi a2,sp,15
  2758. 180011e8: 45a1 li a1,8
  2759. 180011ea: 8526 mv a0,s1
  2760. 180011ec: 8e9ff0ef jal ra,18000ad4 <spi_xfer>
  2761. 180011f0: 882a mv a6,a0
  2762. ret = spi_xfer(spi, 8*1, NULL, status, SPI_XFER_END, SPI_DATAMODE_8);
  2763. 180011f2: 47a1 li a5,8
  2764. 180011f4: 4709 li a4,2
  2765. 180011f6: 01f10693 addi a3,sp,31
  2766. 180011fa: 4601 li a2,0
  2767. 180011fc: 45a1 li a1,8
  2768. 180011fe: 8526 mv a0,s1
  2769. if (ret) {
  2770. 18001200: 00080b63 beqz a6,18001216 <spi_flash_cmd_poll_bit+0x56>
  2771. return 0;
  2772. /* Timed out */
  2773. //uart_printf("SF: time out!\r\n");
  2774. return -1;
  2775. }
  2776. 18001204: 60a6 ld ra,72(sp)
  2777. 18001206: 6406 ld s0,64(sp)
  2778. 18001208: 74e2 ld s1,56(sp)
  2779. 1800120a: 7942 ld s2,48(sp)
  2780. 1800120c: 79a2 ld s3,40(sp)
  2781. 1800120e: 7a02 ld s4,32(sp)
  2782. 18001210: 8542 mv a0,a6
  2783. 18001212: 6161 addi sp,sp,80
  2784. 18001214: 8082 ret
  2785. ret = spi_xfer(spi, 8*1, NULL, status, SPI_XFER_END, SPI_DATAMODE_8);
  2786. 18001216: 8bfff0ef jal ra,18000ad4 <spi_xfer>
  2787. timebase_1++;//libo
  2788. 1800121a: 0014071b addiw a4,s0,1
  2789. } while (timebase_1 < timeout);
  2790. 1800121e: 02071613 slli a2,a4,0x20
  2791. ret = spi_xfer(spi, 8*1, NULL, status, SPI_XFER_END, SPI_DATAMODE_8);
  2792. 18001222: 882a mv a6,a0
  2793. } while (timebase_1 < timeout);
  2794. 18001224: 9201 srli a2,a2,0x20
  2795. if (ret)
  2796. 18001226: fd79 bnez a0,18001204 <spi_flash_cmd_poll_bit+0x44>
  2797. if ((status & poll_bit) == 0)
  2798. 18001228: 01f14783 lbu a5,31(sp)
  2799. timebase_1++;//libo
  2800. 1800122c: 0007041b sext.w s0,a4
  2801. if ((status & poll_bit) == 0)
  2802. 18001230: 00f9f7b3 and a5,s3,a5
  2803. 18001234: dbe1 beqz a5,18001204 <spi_flash_cmd_poll_bit+0x44>
  2804. } while (timebase_1 < timeout);
  2805. 18001236: fb4662e3 bltu a2,s4,180011da <spi_flash_cmd_poll_bit+0x1a>
  2806. return -1;
  2807. 1800123a: 587d li a6,-1
  2808. 1800123c: b7e1 j 18001204 <spi_flash_cmd_poll_bit+0x44>
  2809. 000000001800123e <spi_flash_cmd_wait_ready>:
  2810. int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
  2811. {
  2812. return spi_flash_cmd_poll_bit(flash, timeout,
  2813. 1800123e: 4685 li a3,1
  2814. 18001240: 4615 li a2,5
  2815. 18001242: bfbd j 180011c0 <spi_flash_cmd_poll_bit>
  2816. 0000000018001244 <spi_flash_cmd_poll_enable>:
  2817. CMD_READ_STATUS, STATUS_WIP);
  2818. }
  2819. int spi_flash_cmd_poll_enable(struct spi_flash *flash, unsigned long timeout,
  2820. u8 cmd, u32 poll_bit)
  2821. {
  2822. 18001244: 715d addi sp,sp,-80
  2823. 18001246: e0a2 sd s0,64(sp)
  2824. 18001248: f84a sd s2,48(sp)
  2825. 1800124a: f44e sd s3,40(sp)
  2826. 1800124c: f052 sd s4,32(sp)
  2827. 1800124e: e486 sd ra,72(sp)
  2828. 18001250: fc26 sd s1,56(sp)
  2829. 18001252: 892a mv s2,a0
  2830. 18001254: 8a2e mv s4,a1
  2831. 18001256: 89b6 mv s3,a3
  2832. 18001258: 00c107a3 sb a2,15(sp)
  2833. int ret;
  2834. u8 status;
  2835. u32 status_tmp = 0;
  2836. u32 timebase_1 = 0;
  2837. 1800125c: 4401 li s0,0
  2838. struct spi_slave *spi = flash->spi;
  2839. 1800125e: 00093483 ld s1,0(s2)
  2840. ret = spi_xfer(spi, 8*cmd_len, cmd, NULL, SPI_XFER_BEGIN, SPI_DATAMODE_8);
  2841. 18001262: 47a1 li a5,8
  2842. 18001264: 4705 li a4,1
  2843. 18001266: 4681 li a3,0
  2844. 18001268: 00f10613 addi a2,sp,15
  2845. 1800126c: 45a1 li a1,8
  2846. 1800126e: 8526 mv a0,s1
  2847. 18001270: 865ff0ef jal ra,18000ad4 <spi_xfer>
  2848. 18001274: 882a mv a6,a0
  2849. ret = spi_xfer(spi, 8*1, NULL, status, SPI_XFER_END, SPI_DATAMODE_8);
  2850. 18001276: 47a1 li a5,8
  2851. 18001278: 4709 li a4,2
  2852. 1800127a: 01f10693 addi a3,sp,31
  2853. 1800127e: 4601 li a2,0
  2854. 18001280: 45a1 li a1,8
  2855. 18001282: 8526 mv a0,s1
  2856. if (ret) {
  2857. 18001284: 00080b63 beqz a6,1800129a <spi_flash_cmd_poll_enable+0x56>
  2858. } while (timebase_1 < timeout);
  2859. /* Timed out */
  2860. //uart_printf("SF: time out!\r\n");
  2861. return 0;
  2862. }
  2863. 18001288: 60a6 ld ra,72(sp)
  2864. 1800128a: 6406 ld s0,64(sp)
  2865. 1800128c: 74e2 ld s1,56(sp)
  2866. 1800128e: 7942 ld s2,48(sp)
  2867. 18001290: 79a2 ld s3,40(sp)
  2868. 18001292: 7a02 ld s4,32(sp)
  2869. 18001294: 8542 mv a0,a6
  2870. 18001296: 6161 addi sp,sp,80
  2871. 18001298: 8082 ret
  2872. ret = spi_xfer(spi, 8*1, NULL, status, SPI_XFER_END, SPI_DATAMODE_8);
  2873. 1800129a: 83bff0ef jal ra,18000ad4 <spi_xfer>
  2874. timebase_1++;
  2875. 1800129e: 0014071b addiw a4,s0,1
  2876. } while (timebase_1 < timeout);
  2877. 180012a2: 02071693 slli a3,a4,0x20
  2878. ret = spi_xfer(spi, 8*1, NULL, status, SPI_XFER_END, SPI_DATAMODE_8);
  2879. 180012a6: 882a mv a6,a0
  2880. if ((status & poll_bit) == 1)
  2881. 180012a8: 4605 li a2,1
  2882. } while (timebase_1 < timeout);
  2883. 180012aa: 9281 srli a3,a3,0x20
  2884. if (ret)
  2885. 180012ac: fd71 bnez a0,18001288 <spi_flash_cmd_poll_enable+0x44>
  2886. if ((status & poll_bit) == 1)
  2887. 180012ae: 01f14783 lbu a5,31(sp)
  2888. timebase_1++;
  2889. 180012b2: 0007041b sext.w s0,a4
  2890. if ((status & poll_bit) == 1)
  2891. 180012b6: 00f9f7b3 and a5,s3,a5
  2892. 180012ba: fcc787e3 beq a5,a2,18001288 <spi_flash_cmd_poll_enable+0x44>
  2893. } while (timebase_1 < timeout);
  2894. 180012be: fb46e0e3 bltu a3,s4,1800125e <spi_flash_cmd_poll_enable+0x1a>
  2895. 180012c2: b7d9 j 18001288 <spi_flash_cmd_poll_enable+0x44>
  2896. 00000000180012c4 <spi_flash_cmd_status_poll_enable>:
  2897. int spi_flash_cmd_status_poll_enable(struct spi_flash *flash, unsigned long timeout,
  2898. u8 cmd, u32 poll_bit)
  2899. {
  2900. 180012c4: 715d addi sp,sp,-80
  2901. 180012c6: e0a2 sd s0,64(sp)
  2902. 180012c8: f84a sd s2,48(sp)
  2903. 180012ca: f44e sd s3,40(sp)
  2904. 180012cc: f052 sd s4,32(sp)
  2905. 180012ce: e486 sd ra,72(sp)
  2906. 180012d0: fc26 sd s1,56(sp)
  2907. 180012d2: 892a mv s2,a0
  2908. 180012d4: 8a2e mv s4,a1
  2909. 180012d6: 89b6 mv s3,a3
  2910. 180012d8: 00c107a3 sb a2,15(sp)
  2911. int ret;
  2912. u8 status;
  2913. u32 status_tmp = 0;
  2914. u32 timebase_1 = 0;
  2915. 180012dc: 4401 li s0,0
  2916. struct spi_slave *spi = flash->spi;
  2917. 180012de: 00093483 ld s1,0(s2)
  2918. ret = spi_xfer(spi, 8*cmd_len, cmd, NULL, SPI_XFER_BEGIN, SPI_DATAMODE_8);
  2919. 180012e2: 47a1 li a5,8
  2920. 180012e4: 4705 li a4,1
  2921. 180012e6: 4681 li a3,0
  2922. 180012e8: 00f10613 addi a2,sp,15
  2923. 180012ec: 45a1 li a1,8
  2924. 180012ee: 8526 mv a0,s1
  2925. 180012f0: fe4ff0ef jal ra,18000ad4 <spi_xfer>
  2926. 180012f4: 882a mv a6,a0
  2927. ret = spi_xfer(spi, 8*1, NULL, status, SPI_XFER_END, SPI_DATAMODE_8);
  2928. 180012f6: 47a1 li a5,8
  2929. 180012f8: 4709 li a4,2
  2930. 180012fa: 01f10693 addi a3,sp,31
  2931. 180012fe: 4601 li a2,0
  2932. 18001300: 45a1 li a1,8
  2933. 18001302: 8526 mv a0,s1
  2934. if (ret) {
  2935. 18001304: 00080b63 beqz a6,1800131a <spi_flash_cmd_status_poll_enable+0x56>
  2936. } while (timebase_1 < timeout);
  2937. /* Timed out */
  2938. //uart_printf("SF: time out!\r\n");
  2939. return 0;
  2940. }
  2941. 18001308: 60a6 ld ra,72(sp)
  2942. 1800130a: 6406 ld s0,64(sp)
  2943. 1800130c: 74e2 ld s1,56(sp)
  2944. 1800130e: 7942 ld s2,48(sp)
  2945. 18001310: 79a2 ld s3,40(sp)
  2946. 18001312: 7a02 ld s4,32(sp)
  2947. 18001314: 8542 mv a0,a6
  2948. 18001316: 6161 addi sp,sp,80
  2949. 18001318: 8082 ret
  2950. ret = spi_xfer(spi, 8*1, NULL, status, SPI_XFER_END, SPI_DATAMODE_8);
  2951. 1800131a: fbaff0ef jal ra,18000ad4 <spi_xfer>
  2952. timebase_1++;
  2953. 1800131e: 0014071b addiw a4,s0,1
  2954. } while (timebase_1 < timeout);
  2955. 18001322: 02071693 slli a3,a4,0x20
  2956. ret = spi_xfer(spi, 8*1, NULL, status, SPI_XFER_END, SPI_DATAMODE_8);
  2957. 18001326: 882a mv a6,a0
  2958. if ((status & poll_bit) == 0x2)
  2959. 18001328: 4609 li a2,2
  2960. } while (timebase_1 < timeout);
  2961. 1800132a: 9281 srli a3,a3,0x20
  2962. if (ret)
  2963. 1800132c: fd71 bnez a0,18001308 <spi_flash_cmd_status_poll_enable+0x44>
  2964. if ((status & poll_bit) == 0x2)
  2965. 1800132e: 01f14783 lbu a5,31(sp)
  2966. timebase_1++;
  2967. 18001332: 0007041b sext.w s0,a4
  2968. if ((status & poll_bit) == 0x2)
  2969. 18001336: 00f9f7b3 and a5,s3,a5
  2970. 1800133a: fcc787e3 beq a5,a2,18001308 <spi_flash_cmd_status_poll_enable+0x44>
  2971. } while (timebase_1 < timeout);
  2972. 1800133e: fb46e0e3 bltu a3,s4,180012de <spi_flash_cmd_status_poll_enable+0x1a>
  2973. 18001342: b7d9 j 18001308 <spi_flash_cmd_status_poll_enable+0x44>
  2974. 0000000018001344 <spi_flash_cmd_wait_enable>:
  2975. int spi_flash_cmd_wait_enable(struct spi_flash *flash, unsigned long timeout)
  2976. {
  2977. 18001344: 7139 addi sp,sp,-64
  2978. 18001346: 4795 li a5,5
  2979. 18001348: f822 sd s0,48(sp)
  2980. 1800134a: f04a sd s2,32(sp)
  2981. 1800134c: ec4e sd s3,24(sp)
  2982. 1800134e: fc06 sd ra,56(sp)
  2983. 18001350: f426 sd s1,40(sp)
  2984. 18001352: 892a mv s2,a0
  2985. 18001354: 89ae mv s3,a1
  2986. 18001356: 00f10723 sb a5,14(sp)
  2987. u32 timebase_1 = 0;
  2988. 1800135a: 4401 li s0,0
  2989. struct spi_slave *spi = flash->spi;
  2990. 1800135c: 00093483 ld s1,0(s2)
  2991. ret = spi_xfer(spi, 8*cmd_len, cmd, NULL, SPI_XFER_BEGIN, SPI_DATAMODE_8);
  2992. 18001360: 47a1 li a5,8
  2993. 18001362: 4705 li a4,1
  2994. 18001364: 4681 li a3,0
  2995. 18001366: 00e10613 addi a2,sp,14
  2996. 1800136a: 45a1 li a1,8
  2997. 1800136c: 8526 mv a0,s1
  2998. 1800136e: f66ff0ef jal ra,18000ad4 <spi_xfer>
  2999. 18001372: 882a mv a6,a0
  3000. ret = spi_xfer(spi, 8*1, NULL, status, SPI_XFER_END, SPI_DATAMODE_8);
  3001. 18001374: 47a1 li a5,8
  3002. 18001376: 4709 li a4,2
  3003. 18001378: 00f10693 addi a3,sp,15
  3004. 1800137c: 4601 li a2,0
  3005. 1800137e: 45a1 li a1,8
  3006. 18001380: 8526 mv a0,s1
  3007. if (ret) {
  3008. 18001382: 00080a63 beqz a6,18001396 <spi_flash_cmd_wait_enable+0x52>
  3009. return spi_flash_cmd_status_poll_enable(flash, timeout,
  3010. CMD_READ_STATUS, FLASH_ENABLE);
  3011. }
  3012. 18001386: 70e2 ld ra,56(sp)
  3013. 18001388: 7442 ld s0,48(sp)
  3014. 1800138a: 74a2 ld s1,40(sp)
  3015. 1800138c: 7902 ld s2,32(sp)
  3016. 1800138e: 69e2 ld s3,24(sp)
  3017. 18001390: 8542 mv a0,a6
  3018. 18001392: 6121 addi sp,sp,64
  3019. 18001394: 8082 ret
  3020. ret = spi_xfer(spi, 8*1, NULL, status, SPI_XFER_END, SPI_DATAMODE_8);
  3021. 18001396: f3eff0ef jal ra,18000ad4 <spi_xfer>
  3022. timebase_1++;
  3023. 1800139a: 0014071b addiw a4,s0,1
  3024. } while (timebase_1 < timeout);
  3025. 1800139e: 02071693 slli a3,a4,0x20
  3026. ret = spi_xfer(spi, 8*1, NULL, status, SPI_XFER_END, SPI_DATAMODE_8);
  3027. 180013a2: 882a mv a6,a0
  3028. } while (timebase_1 < timeout);
  3029. 180013a4: 9281 srli a3,a3,0x20
  3030. if (ret)
  3031. 180013a6: f165 bnez a0,18001386 <spi_flash_cmd_wait_enable+0x42>
  3032. if ((status & poll_bit) == 0x2)
  3033. 180013a8: 00f14783 lbu a5,15(sp)
  3034. timebase_1++;
  3035. 180013ac: 0007041b sext.w s0,a4
  3036. if ((status & poll_bit) == 0x2)
  3037. 180013b0: 8b89 andi a5,a5,2
  3038. 180013b2: fbf1 bnez a5,18001386 <spi_flash_cmd_wait_enable+0x42>
  3039. } while (timebase_1 < timeout);
  3040. 180013b4: fb36e4e3 bltu a3,s3,1800135c <spi_flash_cmd_wait_enable+0x18>
  3041. }
  3042. 180013b8: 70e2 ld ra,56(sp)
  3043. 180013ba: 7442 ld s0,48(sp)
  3044. 180013bc: 74a2 ld s1,40(sp)
  3045. 180013be: 7902 ld s2,32(sp)
  3046. 180013c0: 69e2 ld s3,24(sp)
  3047. 180013c2: 8542 mv a0,a6
  3048. 180013c4: 6121 addi sp,sp,64
  3049. 180013c6: 8082 ret
  3050. 00000000180013c8 <spi_flash_write_status>:
  3051. int spi_flash_write_status(struct spi_flash *flash, u8 *cmd, unsigned int cmd_len,void *data, unsigned int data_len)
  3052. {
  3053. 180013c8: 7139 addi sp,sp,-64
  3054. 180013ca: f822 sd s0,48(sp)
  3055. 180013cc: 842a mv s0,a0
  3056. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3057. 180013ce: 6108 ld a0,0(a0)
  3058. {
  3059. 180013d0: f426 sd s1,40(sp)
  3060. 180013d2: f04a sd s2,32(sp)
  3061. 180013d4: ec4e sd s3,24(sp)
  3062. 180013d6: e852 sd s4,16(sp)
  3063. 180013d8: 84ae mv s1,a1
  3064. 180013da: 8932 mv s2,a2
  3065. 180013dc: 89b6 mv s3,a3
  3066. 180013de: 8a3a mv s4,a4
  3067. 180013e0: 4819 li a6,6
  3068. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3069. 180013e2: 47a1 li a5,8
  3070. 180013e4: 470d li a4,3
  3071. 180013e6: 4681 li a3,0
  3072. 180013e8: 00f10613 addi a2,sp,15
  3073. 180013ec: 45a1 li a1,8
  3074. {
  3075. 180013ee: fc06 sd ra,56(sp)
  3076. 180013f0: 010107a3 sb a6,15(sp)
  3077. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3078. 180013f4: ee0ff0ef jal ra,18000ad4 <spi_xfer>
  3079. if (ret)
  3080. 180013f8: e921 bnez a0,18001448 <spi_flash_write_status+0x80>
  3081. return spi_flash_read_write(spi, cmd, cmd_len, data, NULL, data_len);
  3082. 180013fa: 6008 ld a0,0(s0)
  3083. 180013fc: 87d2 mv a5,s4
  3084. 180013fe: 4701 li a4,0
  3085. 18001400: 86ce mv a3,s3
  3086. 18001402: 864a mv a2,s2
  3087. 18001404: 85a6 mv a1,s1
  3088. 18001406: ba9ff0ef jal ra,18000fae <spi_flash_read_write>
  3089. // uart_printf("SF: Unable to claim SPI bus\n");
  3090. return ret;
  3091. }
  3092. ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, data, data_len);
  3093. if (ret < 0) {
  3094. 1800140a: 02054f63 bltz a0,18001448 <spi_flash_write_status+0x80>
  3095. return spi_flash_cmd_poll_bit(flash, timeout,
  3096. 1800140e: 039385b7 lui a1,0x3938
  3097. 18001412: 4685 li a3,1
  3098. 18001414: 4615 li a2,5
  3099. 18001416: 70058593 addi a1,a1,1792 # 3938700 <__stack_size+0x3937f00>
  3100. 1800141a: 8522 mv a0,s0
  3101. 1800141c: da5ff0ef jal ra,180011c0 <spi_flash_cmd_poll_bit>
  3102. //uart_printf("SF: write failed\n");
  3103. return ret;
  3104. }
  3105. ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
  3106. if (ret < 0) {
  3107. 18001420: 02054463 bltz a0,18001448 <spi_flash_write_status+0x80>
  3108. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3109. 18001424: 6008 ld a0,0(s0)
  3110. 18001426: 47a1 li a5,8
  3111. 18001428: 4811 li a6,4
  3112. 1800142a: 470d li a4,3
  3113. 1800142c: 4681 li a3,0
  3114. 1800142e: 00f10613 addi a2,sp,15
  3115. 18001432: 45a1 li a1,8
  3116. 18001434: 010107a3 sb a6,15(sp)
  3117. 18001438: e9cff0ef jal ra,18000ad4 <spi_xfer>
  3118. //uart_printf("SF: wait ready failed\n");
  3119. return ret;
  3120. }
  3121. ret = spi_flash_cmd_write_disable(flash->spi);
  3122. if (ret < 0) {
  3123. 1800143c: 00152793 slti a5,a0,1
  3124. 18001440: 40f007bb negw a5,a5
  3125. 18001444: 8d7d and a0,a0,a5
  3126. 18001446: 2501 sext.w a0,a0
  3127. //uart_printf("SF: disable write failed\n");
  3128. return ret;
  3129. }
  3130. return 0;
  3131. }
  3132. 18001448: 70e2 ld ra,56(sp)
  3133. 1800144a: 7442 ld s0,48(sp)
  3134. 1800144c: 74a2 ld s1,40(sp)
  3135. 1800144e: 7902 ld s2,32(sp)
  3136. 18001450: 69e2 ld s3,24(sp)
  3137. 18001452: 6a42 ld s4,16(sp)
  3138. 18001454: 6121 addi sp,sp,64
  3139. 18001456: 8082 ret
  3140. 0000000018001458 <spi_flash_write_status_bit>:
  3141. /* set PB=0 all can write */
  3142. return spi_flash_write_status_bit(flash, 0x00, 0);
  3143. }
  3144. #else
  3145. int spi_flash_write_status_bit(struct spi_flash *flash, u8 status1, u8 status2, u8 bit1, u8 bit2)
  3146. {
  3147. 18001458: 7179 addi sp,sp,-48
  3148. u8 status[3];
  3149. int ret = 0;
  3150. status[0] = CMD_WRITE_STATUS;
  3151. status[1] = status1|bit1;
  3152. 1800145a: 00d5e833 or a6,a1,a3
  3153. status[2] = status2|bit2;
  3154. 1800145e: 00e667b3 or a5,a2,a4
  3155. {
  3156. 18001462: f022 sd s0,32(sp)
  3157. 18001464: ec26 sd s1,24(sp)
  3158. 18001466: 843a mv s0,a4
  3159. 18001468: 84b6 mv s1,a3
  3160. status[0] = CMD_WRITE_STATUS;
  3161. 1800146a: 4885 li a7,1
  3162. spi_flash_write_status(flash, &status[0], 1, &status[1], 2);
  3163. 1800146c: 4709 li a4,2
  3164. 1800146e: 00910693 addi a3,sp,9
  3165. 18001472: 4605 li a2,1
  3166. 18001474: 002c addi a1,sp,8
  3167. {
  3168. 18001476: e84a sd s2,16(sp)
  3169. 18001478: f406 sd ra,40(sp)
  3170. 1800147a: 892a mv s2,a0
  3171. status[0] = CMD_WRITE_STATUS;
  3172. 1800147c: 01110423 sb a7,8(sp)
  3173. status[1] = status1|bit1;
  3174. 18001480: 010104a3 sb a6,9(sp)
  3175. status[2] = status2|bit2;
  3176. 18001484: 00f10523 sb a5,10(sp)
  3177. spi_flash_write_status(flash, &status[0], 1, &status[1], 2);
  3178. 18001488: f41ff0ef jal ra,180013c8 <spi_flash_write_status>
  3179. if (bit1)
  3180. 1800148c: e889 bnez s1,1800149e <spi_flash_write_status_bit+0x46>
  3181. {
  3182. ret &= spi_flash_cmd_poll_bit(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT, CMD_READ_STATUS, ~bit1);
  3183. }
  3184. if (bit2)
  3185. 1800148e: e40d bnez s0,180014b8 <spi_flash_write_status_bit+0x60>
  3186. return ret;
  3187. delay(1000);
  3188. return ret;
  3189. }
  3190. 18001490: 70a2 ld ra,40(sp)
  3191. 18001492: 7402 ld s0,32(sp)
  3192. 18001494: 64e2 ld s1,24(sp)
  3193. 18001496: 6942 ld s2,16(sp)
  3194. 18001498: 4501 li a0,0
  3195. 1800149a: 6145 addi sp,sp,48
  3196. 1800149c: 8082 ret
  3197. ret &= spi_flash_cmd_poll_bit(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT, CMD_READ_STATUS, ~bit1);
  3198. 1800149e: fff4c693 not a3,s1
  3199. 180014a2: 039385b7 lui a1,0x3938
  3200. 180014a6: 0ff6f693 zext.b a3,a3
  3201. 180014aa: 4615 li a2,5
  3202. 180014ac: 70058593 addi a1,a1,1792 # 3938700 <__stack_size+0x3937f00>
  3203. 180014b0: 854a mv a0,s2
  3204. 180014b2: d0fff0ef jal ra,180011c0 <spi_flash_cmd_poll_bit>
  3205. if (bit2)
  3206. 180014b6: dc69 beqz s0,18001490 <spi_flash_write_status_bit+0x38>
  3207. ret &= spi_flash_cmd_poll_bit(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT, CMD_READ_STATUS1, ~bit2);
  3208. 180014b8: fff44693 not a3,s0
  3209. 180014bc: 039385b7 lui a1,0x3938
  3210. 180014c0: 854a mv a0,s2
  3211. 180014c2: 0ff6f693 zext.b a3,a3
  3212. 180014c6: 03500613 li a2,53
  3213. 180014ca: 70058593 addi a1,a1,1792 # 3938700 <__stack_size+0x3937f00>
  3214. 180014ce: cf3ff0ef jal ra,180011c0 <spi_flash_cmd_poll_bit>
  3215. }
  3216. 180014d2: 70a2 ld ra,40(sp)
  3217. 180014d4: 7402 ld s0,32(sp)
  3218. 180014d6: 64e2 ld s1,24(sp)
  3219. 180014d8: 6942 ld s2,16(sp)
  3220. 180014da: 4501 li a0,0
  3221. 180014dc: 6145 addi sp,sp,48
  3222. 180014de: 8082 ret
  3223. 00000000180014e0 <spi_flash_protect>:
  3224. int spi_flash_protect(struct spi_flash *flash)
  3225. {
  3226. 180014e0: 7179 addi sp,sp,-48
  3227. 180014e2: f022 sd s0,32(sp)
  3228. 180014e4: 842a mv s0,a0
  3229. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3230. 180014e6: 6108 ld a0,0(a0)
  3231. status[0] = CMD_WRITE_STATUS;
  3232. 180014e8: 4805 li a6,1
  3233. 180014ea: 01011423 sh a6,8(sp)
  3234. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3235. 180014ee: 47a1 li a5,8
  3236. 180014f0: 4819 li a6,6
  3237. 180014f2: 470d li a4,3
  3238. 180014f4: 4681 li a3,0
  3239. 180014f6: 00710613 addi a2,sp,7
  3240. 180014fa: 45a1 li a1,8
  3241. {
  3242. 180014fc: f406 sd ra,40(sp)
  3243. 180014fe: ec26 sd s1,24(sp)
  3244. status[2] = status2|bit2;
  3245. 18001500: 00010523 sb zero,10(sp)
  3246. return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, (void*)NULL, 0);
  3247. 18001504: 010103a3 sb a6,7(sp)
  3248. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3249. 18001508: dccff0ef jal ra,18000ad4 <spi_xfer>
  3250. if (ret)
  3251. 1800150c: e521 bnez a0,18001554 <spi_flash_protect+0x74>
  3252. ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, data, data_len);
  3253. 1800150e: 6004 ld s1,0(s0)
  3254. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3255. 18001510: 47a1 li a5,8
  3256. 18001512: 4705 li a4,1
  3257. 18001514: 4681 li a3,0
  3258. 18001516: 0030 addi a2,sp,8
  3259. 18001518: 45a1 li a1,8
  3260. 1800151a: 8526 mv a0,s1
  3261. 1800151c: db8ff0ef jal ra,18000ad4 <spi_xfer>
  3262. if (ret)
  3263. 18001520: c121 beqz a0,18001560 <spi_flash_protect+0x80>
  3264. if (ret < 0) {
  3265. 18001522: 02054963 bltz a0,18001554 <spi_flash_protect+0x74>
  3266. return spi_flash_cmd_poll_bit(flash, timeout,
  3267. 18001526: 039385b7 lui a1,0x3938
  3268. 1800152a: 4685 li a3,1
  3269. 1800152c: 4615 li a2,5
  3270. 1800152e: 70058593 addi a1,a1,1792 # 3938700 <__stack_size+0x3937f00>
  3271. 18001532: 8522 mv a0,s0
  3272. 18001534: c8dff0ef jal ra,180011c0 <spi_flash_cmd_poll_bit>
  3273. if (ret < 0) {
  3274. 18001538: 00054e63 bltz a0,18001554 <spi_flash_protect+0x74>
  3275. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3276. 1800153c: 6008 ld a0,0(s0)
  3277. 1800153e: 4811 li a6,4
  3278. 18001540: 47a1 li a5,8
  3279. 18001542: 470d li a4,3
  3280. 18001544: 4681 li a3,0
  3281. 18001546: 00710613 addi a2,sp,7
  3282. 1800154a: 45a1 li a1,8
  3283. 1800154c: 010103a3 sb a6,7(sp)
  3284. 18001550: d84ff0ef jal ra,18000ad4 <spi_xfer>
  3285. /* set PB=0 all can write */
  3286. return spi_flash_write_status_bit(flash, 0x00, 0x00, 0, 0);
  3287. }
  3288. 18001554: 70a2 ld ra,40(sp)
  3289. 18001556: 7402 ld s0,32(sp)
  3290. 18001558: 64e2 ld s1,24(sp)
  3291. 1800155a: 4501 li a0,0
  3292. 1800155c: 6145 addi sp,sp,48
  3293. 1800155e: 8082 ret
  3294. ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END, SPI_DATAMODE_8);
  3295. 18001560: 47a1 li a5,8
  3296. 18001562: 4709 li a4,2
  3297. 18001564: 4681 li a3,0
  3298. 18001566: 00910613 addi a2,sp,9
  3299. 1800156a: 45c1 li a1,16
  3300. 1800156c: 8526 mv a0,s1
  3301. 1800156e: d66ff0ef jal ra,18000ad4 <spi_xfer>
  3302. return ret;
  3303. 18001572: bf45 j 18001522 <spi_flash_protect+0x42>
  3304. 0000000018001574 <spi_flash_cmd_erase>:
  3305. #endif
  3306. int spi_flash_cmd_erase(struct spi_flash *flash, u8 erase_cmd,
  3307. u32 offset, u32 len)
  3308. {
  3309. 18001574: 715d addi sp,sp,-80
  3310. 18001576: e0a2 sd s0,64(sp)
  3311. 18001578: fc26 sd s1,56(sp)
  3312. 1800157a: f84a sd s2,48(sp)
  3313. 1800157c: f052 sd s4,32(sp)
  3314. 1800157e: e486 sd ra,72(sp)
  3315. 18001580: f44e sd s3,40(sp)
  3316. 18001582: ec56 sd s5,24(sp)
  3317. 18001584: e85a sd s6,16(sp)
  3318. int ret;
  3319. u8 cmd[4];
  3320. //uart_printf("spi_flash_cmd_erase \r\n");
  3321. switch(erase_cmd){
  3322. 18001586: 05200793 li a5,82
  3323. {
  3324. 1800158a: 8a2e mv s4,a1
  3325. 1800158c: 84aa mv s1,a0
  3326. 1800158e: 8432 mv s0,a2
  3327. 18001590: 8936 mv s2,a3
  3328. switch(erase_cmd){
  3329. 18001592: 0ef58963 beq a1,a5,18001684 <spi_flash_cmd_erase+0x110>
  3330. 18001596: 0d800793 li a5,216
  3331. 1800159a: 0ef58263 beq a1,a5,1800167e <spi_flash_cmd_erase+0x10a>
  3332. case CMD_W25_SE:
  3333. erase_size = flash->sector_size;
  3334. 1800159e: 01852983 lw s3,24(a0)
  3335. default:
  3336. erase_size = flash->sector_size;
  3337. break;
  3338. }
  3339. if (offset % erase_size || len % erase_size) {
  3340. 180015a2: 033477bb remuw a5,s0,s3
  3341. 180015a6: e7e5 bnez a5,1800168e <spi_flash_cmd_erase+0x11a>
  3342. 180015a8: 033977bb remuw a5,s2,s3
  3343. 180015ac: e3ed bnez a5,1800168e <spi_flash_cmd_erase+0x11a>
  3344. status[0] = CMD_WRITE_STATUS;
  3345. 180015ae: 4785 li a5,1
  3346. spi_flash_write_status(flash, &status[0], 1, &status[1], 2);
  3347. 180015b0: 4709 li a4,2
  3348. 180015b2: 00910693 addi a3,sp,9
  3349. 180015b6: 4605 li a2,1
  3350. 180015b8: 002c addi a1,sp,8
  3351. 180015ba: 8526 mv a0,s1
  3352. status[0] = CMD_WRITE_STATUS;
  3353. 180015bc: 00f11423 sh a5,8(sp)
  3354. status[2] = status2|bit2;
  3355. 180015c0: 00010523 sb zero,10(sp)
  3356. // spi_flash_cmd_write_status_enable(flash);
  3357. spi_flash_protect(flash);
  3358. cmd[0] = erase_cmd;
  3359. start = offset;
  3360. end = start + len;
  3361. 180015c4: 0124093b addw s2,s0,s2
  3362. spi_flash_write_status(flash, &status[0], 1, &status[1], 2);
  3363. 180015c8: e01ff0ef jal ra,180013c8 <spi_flash_write_status>
  3364. cmd[0] = erase_cmd;
  3365. 180015cc: 01410423 sb s4,8(sp)
  3366. while (offset < end)
  3367. 180015d0: 0b247563 bgeu s0,s2,1800167a <spi_flash_cmd_erase+0x106>
  3368. return spi_flash_cmd_poll_bit(flash, timeout,
  3369. 180015d4: 03938a37 lui s4,0x3938
  3370. 180015d8: 4a99 li s5,6
  3371. 180015da: 700a0a13 addi s4,s4,1792 # 3938700 <__stack_size+0x3937f00>
  3372. 180015de: 4b11 li s6,4
  3373. cmd[2] = (addr & 0x0000FF00) >> 8;
  3374. 180015e0: 0104179b slliw a5,s0,0x10
  3375. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3376. 180015e4: 6088 ld a0,0(s1)
  3377. cmd[2] = (addr & 0x0000FF00) >> 8;
  3378. 180015e6: 0107d79b srliw a5,a5,0x10
  3379. 180015ea: 0084181b slliw a6,s0,0x8
  3380. 180015ee: 0087d79b srliw a5,a5,0x8
  3381. 180015f2: 00f86833 or a6,a6,a5
  3382. cmd[1] = (addr & 0x00FF0000) >> 16;
  3383. 180015f6: 0104589b srliw a7,s0,0x10
  3384. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3385. 180015fa: 47a1 li a5,8
  3386. 180015fc: 470d li a4,3
  3387. 180015fe: 4681 li a3,0
  3388. 18001600: 00710613 addi a2,sp,7
  3389. 18001604: 45a1 li a1,8
  3390. cmd[2] = (addr & 0x0000FF00) >> 8;
  3391. 18001606: 01011523 sh a6,10(sp)
  3392. cmd[1] = (addr & 0x00FF0000) >> 16;
  3393. 1800160a: 011104a3 sb a7,9(sp)
  3394. {
  3395. spi_flash_addr(offset, cmd);
  3396. offset += erase_size;
  3397. 1800160e: 015103a3 sb s5,7(sp)
  3398. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3399. 18001612: cc2ff0ef jal ra,18000ad4 <spi_xfer>
  3400. 18001616: 47a1 li a5,8
  3401. 18001618: 470d li a4,3
  3402. 1800161a: 4681 li a3,0
  3403. 1800161c: 0030 addi a2,sp,8
  3404. 1800161e: 02000593 li a1,32
  3405. 18001622: 882a mv a6,a0
  3406. offset += erase_size;
  3407. 18001624: 0089843b addw s0,s3,s0
  3408. if (ret)
  3409. 18001628: cd01 beqz a0,18001640 <spi_flash_cmd_erase+0xcc>
  3410. //uart_printf("SF: Successfully erased %d bytes @ %x\n", len , start);
  3411. out:
  3412. return ret;
  3413. }
  3414. 1800162a: 60a6 ld ra,72(sp)
  3415. 1800162c: 6406 ld s0,64(sp)
  3416. 1800162e: 74e2 ld s1,56(sp)
  3417. 18001630: 7942 ld s2,48(sp)
  3418. 18001632: 79a2 ld s3,40(sp)
  3419. 18001634: 7a02 ld s4,32(sp)
  3420. 18001636: 6ae2 ld s5,24(sp)
  3421. 18001638: 6b42 ld s6,16(sp)
  3422. 1800163a: 8542 mv a0,a6
  3423. 1800163c: 6161 addi sp,sp,80
  3424. 1800163e: 8082 ret
  3425. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3426. 18001640: 6088 ld a0,0(s1)
  3427. 18001642: c92ff0ef jal ra,18000ad4 <spi_xfer>
  3428. 18001646: 882a mv a6,a0
  3429. return spi_flash_cmd_poll_bit(flash, timeout,
  3430. 18001648: 4685 li a3,1
  3431. 1800164a: 4615 li a2,5
  3432. 1800164c: 85d2 mv a1,s4
  3433. 1800164e: 8526 mv a0,s1
  3434. if (ret)
  3435. 18001650: fc081de3 bnez a6,1800162a <spi_flash_cmd_erase+0xb6>
  3436. return spi_flash_cmd_poll_bit(flash, timeout,
  3437. 18001654: b6dff0ef jal ra,180011c0 <spi_flash_cmd_poll_bit>
  3438. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3439. 18001658: 47a1 li a5,8
  3440. 1800165a: 470d li a4,3
  3441. 1800165c: 4681 li a3,0
  3442. 1800165e: 00710613 addi a2,sp,7
  3443. 18001662: 45a1 li a1,8
  3444. return spi_flash_cmd_poll_bit(flash, timeout,
  3445. 18001664: 882a mv a6,a0
  3446. if (ret)
  3447. 18001666: f171 bnez a0,1800162a <spi_flash_cmd_erase+0xb6>
  3448. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3449. 18001668: 6088 ld a0,0(s1)
  3450. 1800166a: 016103a3 sb s6,7(sp)
  3451. 1800166e: c66ff0ef jal ra,18000ad4 <spi_xfer>
  3452. 18001672: 882a mv a6,a0
  3453. if (ret)
  3454. 18001674: f95d bnez a0,1800162a <spi_flash_cmd_erase+0xb6>
  3455. while (offset < end)
  3456. 18001676: f72465e3 bltu s0,s2,180015e0 <spi_flash_cmd_erase+0x6c>
  3457. return -1;
  3458. 1800167a: 4801 li a6,0
  3459. 1800167c: b77d j 1800162a <spi_flash_cmd_erase+0xb6>
  3460. erase_size = flash->block_size;
  3461. 1800167e: 01c52983 lw s3,28(a0)
  3462. break;
  3463. 18001682: b705 j 180015a2 <spi_flash_cmd_erase+0x2e>
  3464. erase_size = flash->sector_size * 8;
  3465. 18001684: 01852983 lw s3,24(a0)
  3466. 18001688: 0039999b slliw s3,s3,0x3
  3467. break;
  3468. 1800168c: bf19 j 180015a2 <spi_flash_cmd_erase+0x2e>
  3469. return -1;
  3470. 1800168e: 587d li a6,-1
  3471. 18001690: bf69 j 1800162a <spi_flash_cmd_erase+0xb6>
  3472. 0000000018001692 <spi_flash_erase_mode>:
  3473. /* mode is 4, 32, 64*/
  3474. int spi_flash_erase_mode(struct spi_flash *flash, u32 offset, u32 len, u32 mode)
  3475. {
  3476. 18001692: 87b6 mv a5,a3
  3477. int ret = 0;
  3478. switch (mode)
  3479. 18001694: 4711 li a4,4
  3480. {
  3481. 18001696: 86b2 mv a3,a2
  3482. switch (mode)
  3483. 18001698: 00e78a63 beq a5,a4,180016ac <spi_flash_erase_mode+0x1a>
  3484. 1800169c: 02000713 li a4,32
  3485. 180016a0: 00e78a63 beq a5,a4,180016b4 <spi_flash_erase_mode+0x22>
  3486. break;
  3487. case 32:
  3488. ret = spi_flash_cmd_erase(flash, CMD_W25_BE_32, offset, len);
  3489. break;
  3490. case 64:
  3491. ret = spi_flash_cmd_erase(flash, CMD_W25_BE, offset, len);
  3492. 180016a4: 862e mv a2,a1
  3493. 180016a6: 0d800593 li a1,216
  3494. 180016aa: b5e9 j 18001574 <spi_flash_cmd_erase>
  3495. ret = spi_flash_cmd_erase(flash, CMD_W25_SE, offset, len);
  3496. 180016ac: 862e mv a2,a1
  3497. 180016ae: 02000593 li a1,32
  3498. 180016b2: b5c9 j 18001574 <spi_flash_cmd_erase>
  3499. ret = spi_flash_cmd_erase(flash, CMD_W25_BE_32, offset, len);
  3500. 180016b4: 862e mv a2,a1
  3501. 180016b6: 05200593 li a1,82
  3502. 180016ba: bd6d j 18001574 <spi_flash_cmd_erase>
  3503. 00000000180016bc <spi_flash_cmd_write_mode>:
  3504. }
  3505. return ret;
  3506. }
  3507. int spi_flash_cmd_write_mode(struct spi_flash *flash, u32 offset,u32 len, void *buf, u32 mode)
  3508. {
  3509. 180016bc: 7135 addi sp,sp,-160
  3510. 180016be: e922 sd s0,144(sp)
  3511. 180016c0: e14a sd s2,128(sp)
  3512. 180016c2: f4d6 sd s5,104(sp)
  3513. 180016c4: f0da sd s6,96(sp)
  3514. 180016c6: ecde sd s7,88(sp)
  3515. 180016c8: fc6e sd s11,56(sp)
  3516. 180016ca: 8b3a mv s6,a4
  3517. 180016cc: ed06 sd ra,152(sp)
  3518. 180016ce: e526 sd s1,136(sp)
  3519. 180016d0: fcce sd s3,120(sp)
  3520. 180016d2: f8d2 sd s4,112(sp)
  3521. 180016d4: e8e2 sd s8,80(sp)
  3522. 180016d6: e4e6 sd s9,72(sp)
  3523. 180016d8: e0ea sd s10,64(sp)
  3524. int write_data = 1;
  3525. unsigned long flags = SPI_XFER_BEGIN;
  3526. page_size = flash->page_size;
  3527. switch (mode){
  3528. 180016da: 4711 li a4,4
  3529. {
  3530. 180016dc: e436 sd a3,8(sp)
  3531. struct spi_slave *spi = flash->spi;
  3532. 180016de: 00053d83 ld s11,0(a0)
  3533. page_size = flash->page_size;
  3534. 180016e2: 01456b83 lwu s7,20(a0)
  3535. {
  3536. 180016e6: 842a mv s0,a0
  3537. 180016e8: 892e mv s2,a1
  3538. 180016ea: 8ab2 mv s5,a2
  3539. switch (mode){
  3540. 180016ec: 16eb0f63 beq s6,a4,1800186a <spi_flash_cmd_write_mode+0x1ae>
  3541. case 1:
  3542. cmd[0] = CMD_PAGE_PROGRAM;
  3543. 180016f0: 4709 li a4,2
  3544. 180016f2: 02e10423 sb a4,40(sp)
  3545. cmd[0] = CMD_PAGE_PROGRAM;
  3546. break;
  3547. }
  3548. for (actual = 0; actual < len; actual += chunk_len)
  3549. 180016f6: 100a8063 beqz s5,180017f6 <spi_flash_cmd_write_mode+0x13a>
  3550. 180016fa: 039387b7 lui a5,0x3938
  3551. 180016fe: 70078793 addi a5,a5,1792 # 3938700 <__stack_size+0x3937f00>
  3552. return spi_flash_cmd_poll_bit(flash, timeout,
  3553. 18001702: 016e3c37 lui s8,0x16e3
  3554. for (actual = 0; actual < len; actual += chunk_len)
  3555. 18001706: 4981 li s3,0
  3556. 18001708: 4c99 li s9,6
  3557. 1800170a: e03e sd a5,0(sp)
  3558. return spi_flash_cmd_poll_bit(flash, timeout,
  3559. 1800170c: 600c0c13 addi s8,s8,1536 # 16e3600 <__stack_size+0x16e2e00>
  3560. {
  3561. write_addr = offset;
  3562. byte_addr = offset % page_size;
  3563. 18001710: 02091493 slli s1,s2,0x20
  3564. 18001714: 9081 srli s1,s1,0x20
  3565. 18001716: 0374f4b3 remu s1,s1,s7
  3566. chunk_len = min(len - actual, page_size - byte_addr);
  3567. 1800171a: 413a87bb subw a5,s5,s3
  3568. 1800171e: 1782 slli a5,a5,0x20
  3569. 18001720: 9381 srli a5,a5,0x20
  3570. 18001722: 409b84b3 sub s1,s7,s1
  3571. 18001726: 0097f363 bgeu a5,s1,1800172c <spi_flash_cmd_write_mode+0x70>
  3572. 1800172a: 84be mv s1,a5
  3573. cmd[2] = (addr & 0x0000FF00) >> 8;
  3574. 1800172c: 0109181b slliw a6,s2,0x10
  3575. 18001730: 0108581b srliw a6,a6,0x10
  3576. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3577. 18001734: 6008 ld a0,0(s0)
  3578. cmd[2] = (addr & 0x0000FF00) >> 8;
  3579. 18001736: 0088579b srliw a5,a6,0x8
  3580. 1800173a: 0089181b slliw a6,s2,0x8
  3581. 1800173e: 00f86833 or a6,a6,a5
  3582. cmd[1] = (addr & 0x00FF0000) >> 16;
  3583. 18001742: 0109589b srliw a7,s2,0x10
  3584. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3585. 18001746: 47a1 li a5,8
  3586. 18001748: 470d li a4,3
  3587. 1800174a: 4681 li a3,0
  3588. 1800174c: 1010 addi a2,sp,32
  3589. 1800174e: 45a1 li a1,8
  3590. cmd[1] = (addr & 0x00FF0000) >> 16;
  3591. 18001750: 031104a3 sb a7,41(sp)
  3592. cmd[2] = (addr & 0x0000FF00) >> 8;
  3593. 18001754: 03011523 sh a6,42(sp)
  3594. 18001758: 03910023 sb s9,32(sp)
  3595. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3596. 1800175c: b78ff0ef jal ra,18000ad4 <spi_xfer>
  3597. 18001760: 87aa mv a5,a0
  3598. chunk_len = min(len - actual, page_size - byte_addr);
  3599. 18001762: 00048a1b sext.w s4,s1
  3600. if (ret)
  3601. 18001766: c119 beqz a0,1800176c <spi_flash_cmd_write_mode+0xb0>
  3602. spi_flash_addr(write_addr, cmd);
  3603. ret = spi_flash_cmd_write_enable(flash);
  3604. if (ret < 0) {
  3605. 18001768: 08054763 bltz a0,180017f6 <spi_flash_cmd_write_mode+0x13a>
  3606. return spi_flash_cmd_status_poll_enable(flash, timeout,
  3607. 1800176c: 4795 li a5,5
  3608. for (actual = 0; actual < len; actual += chunk_len)
  3609. 1800176e: 6d02 ld s10,0(sp)
  3610. 18001770: 00f10fa3 sb a5,31(sp)
  3611. 18001774: a039 j 18001782 <spi_flash_cmd_write_mode+0xc6>
  3612. if ((status & poll_bit) == 0x2)
  3613. 18001776: 02014783 lbu a5,32(sp)
  3614. 1800177a: 8b89 andi a5,a5,2
  3615. 1800177c: ef81 bnez a5,18001794 <spi_flash_cmd_write_mode+0xd8>
  3616. } while (timebase_1 < timeout);
  3617. 1800177e: 000d0b63 beqz s10,18001794 <spi_flash_cmd_write_mode+0xd8>
  3618. ret = spi_flash_cmd_read_status(flash, &cmd, 1, &status);
  3619. 18001782: 1014 addi a3,sp,32
  3620. 18001784: 4605 li a2,1
  3621. 18001786: 01f10593 addi a1,sp,31
  3622. 1800178a: 8522 mv a0,s0
  3623. 1800178c: 9f3ff0ef jal ra,1800117e <spi_flash_cmd_read_status>
  3624. } while (timebase_1 < timeout);
  3625. 18001790: 3d7d addiw s10,s10,-1
  3626. if (ret)
  3627. 18001792: d175 beqz a0,18001776 <spi_flash_cmd_write_mode+0xba>
  3628. //uart_printf("SF: enabling write failed\n");
  3629. break;
  3630. }
  3631. spi_flash_cmd_wait_enable(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
  3632. #if 1
  3633. if (mode == 1)
  3634. 18001794: 4785 li a5,1
  3635. 18001796: 0afb0a63 beq s6,a5,1800184a <spi_flash_cmd_write_mode+0x18e>
  3636. break;
  3637. }
  3638. }
  3639. #endif
  3640. if (mode == 4)
  3641. 1800179a: 4791 li a5,4
  3642. 1800179c: 00fb1f63 bne s6,a5,180017ba <spi_flash_cmd_write_mode+0xfe>
  3643. {
  3644. flags = SPI_XFER_BEGIN;
  3645. if (chunk_len == 0)
  3646. 180017a0: e8bd bnez s1,18001816 <spi_flash_cmd_write_mode+0x15a>
  3647. flags |= SPI_XFER_END;
  3648. ret = spi_xfer(spi, 4 * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3649. 180017a2: 47a1 li a5,8
  3650. 180017a4: 470d li a4,3
  3651. 180017a6: 4681 li a3,0
  3652. 180017a8: 1030 addi a2,sp,40
  3653. 180017aa: 02000593 li a1,32
  3654. 180017ae: 856e mv a0,s11
  3655. 180017b0: b24ff0ef jal ra,18000ad4 <spi_xfer>
  3656. 180017b4: 87aa mv a5,a0
  3657. if (ret < 0)
  3658. 180017b6: 04054063 bltz a0,180017f6 <spi_flash_cmd_write_mode+0x13a>
  3659. return spi_flash_cmd_poll_bit(flash, timeout,
  3660. 180017ba: 4685 li a3,1
  3661. 180017bc: 4615 li a2,5
  3662. 180017be: 85e2 mv a1,s8
  3663. 180017c0: 8522 mv a0,s0
  3664. 180017c2: 9ffff0ef jal ra,180011c0 <spi_flash_cmd_poll_bit>
  3665. 180017c6: 87aa mv a5,a0
  3666. }
  3667. }
  3668. //qspi_mode_ctl(SPI4_DATEMODE_0);
  3669. ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
  3670. if (ret < 0)
  3671. 180017c8: 02054763 bltz a0,180017f6 <spi_flash_cmd_write_mode+0x13a>
  3672. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3673. 180017cc: 6008 ld a0,0(s0)
  3674. 180017ce: 47a1 li a5,8
  3675. 180017d0: 4811 li a6,4
  3676. 180017d2: 470d li a4,3
  3677. 180017d4: 4681 li a3,0
  3678. 180017d6: 1010 addi a2,sp,32
  3679. 180017d8: 45a1 li a1,8
  3680. 180017da: 03010023 sb a6,32(sp)
  3681. 180017de: af6ff0ef jal ra,18000ad4 <spi_xfer>
  3682. 180017e2: 87aa mv a5,a0
  3683. if (ret)
  3684. 180017e4: c119 beqz a0,180017ea <spi_flash_cmd_write_mode+0x12e>
  3685. {
  3686. //uart_printf("SF: spi_flash_cmd_wait_ready failed\n");
  3687. break;
  3688. }
  3689. ret = spi_flash_cmd_write_disable(flash->spi);
  3690. if (ret < 0)
  3691. 180017e6: 00054863 bltz a0,180017f6 <spi_flash_cmd_write_mode+0x13a>
  3692. for (actual = 0; actual < len; actual += chunk_len)
  3693. 180017ea: 013a09bb addw s3,s4,s3
  3694. {
  3695. //uart_printf("SF: disable write failed\n");
  3696. break;
  3697. }
  3698. offset += chunk_len;
  3699. 180017ee: 012a093b addw s2,s4,s2
  3700. for (actual = 0; actual < len; actual += chunk_len)
  3701. 180017f2: f159efe3 bltu s3,s5,18001710 <spi_flash_cmd_write_mode+0x54>
  3702. //uart_printf("SF: program %s %d bytes @ %d\n", ret ? "failure" : "success", len, offset);
  3703. }
  3704. return ret;
  3705. }
  3706. 180017f6: 60ea ld ra,152(sp)
  3707. 180017f8: 644a ld s0,144(sp)
  3708. 180017fa: 64aa ld s1,136(sp)
  3709. 180017fc: 690a ld s2,128(sp)
  3710. 180017fe: 79e6 ld s3,120(sp)
  3711. 18001800: 7a46 ld s4,112(sp)
  3712. 18001802: 7aa6 ld s5,104(sp)
  3713. 18001804: 7b06 ld s6,96(sp)
  3714. 18001806: 6be6 ld s7,88(sp)
  3715. 18001808: 6c46 ld s8,80(sp)
  3716. 1800180a: 6ca6 ld s9,72(sp)
  3717. 1800180c: 6d06 ld s10,64(sp)
  3718. 1800180e: 7de2 ld s11,56(sp)
  3719. 18001810: 853e mv a0,a5
  3720. 18001812: 610d addi sp,sp,160
  3721. 18001814: 8082 ret
  3722. ret = spi_xfer(spi, 4 * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3723. 18001816: 47a1 li a5,8
  3724. 18001818: 4705 li a4,1
  3725. 1800181a: 4681 li a3,0
  3726. 1800181c: 1030 addi a2,sp,40
  3727. 1800181e: 02000593 li a1,32
  3728. 18001822: 856e mv a0,s11
  3729. 18001824: ab0ff0ef jal ra,18000ad4 <spi_xfer>
  3730. 18001828: 87aa mv a5,a0
  3731. if (ret < 0)
  3732. 1800182a: fc0546e3 bltz a0,180017f6 <spi_flash_cmd_write_mode+0x13a>
  3733. ret = spi_xfer(spi, chunk_len * 8, (unsigned char*)buf + actual, NULL, SPI_XFER_END, SPI_DATAMODE_8);
  3734. 1800182e: 6522 ld a0,8(sp)
  3735. 18001830: 02099613 slli a2,s3,0x20
  3736. 18001834: 9201 srli a2,a2,0x20
  3737. 18001836: 962a add a2,a2,a0
  3738. 18001838: 003a159b slliw a1,s4,0x3
  3739. 1800183c: 47a1 li a5,8
  3740. 1800183e: 4709 li a4,2
  3741. 18001840: 4681 li a3,0
  3742. 18001842: 856e mv a0,s11
  3743. 18001844: a90ff0ef jal ra,18000ad4 <spi_xfer>
  3744. 18001848: bf8d j 180017ba <spi_flash_cmd_write_mode+0xfe>
  3745. return spi_flash_read_write(spi, cmd, cmd_len, data, NULL, data_len);
  3746. 1800184a: 6622 ld a2,8(sp)
  3747. 1800184c: 6008 ld a0,0(s0)
  3748. ret = spi_flash_cmd_write(flash->spi, cmd, 4,
  3749. 1800184e: 02099693 slli a3,s3,0x20
  3750. 18001852: 9281 srli a3,a3,0x20
  3751. return spi_flash_read_write(spi, cmd, cmd_len, data, NULL, data_len);
  3752. 18001854: 87d2 mv a5,s4
  3753. 18001856: 96b2 add a3,a3,a2
  3754. 18001858: 4701 li a4,0
  3755. 1800185a: 4611 li a2,4
  3756. 1800185c: 102c addi a1,sp,40
  3757. 1800185e: f50ff0ef jal ra,18000fae <spi_flash_read_write>
  3758. 18001862: 87aa mv a5,a0
  3759. if (ret < 0) {
  3760. 18001864: f4055be3 bgez a0,180017ba <spi_flash_cmd_write_mode+0xfe>
  3761. 18001868: b779 j 180017f6 <spi_flash_cmd_write_mode+0x13a>
  3762. cmd[0] = CMD_PAGE_PROGRAM_QUAD;
  3763. 1800186a: 03200813 li a6,50
  3764. 1800186e: 03010423 sb a6,40(sp)
  3765. status[0] = CMD_WRITE_STATUS;
  3766. 18001872: 4805 li a6,1
  3767. spi_flash_write_status(flash, &status[0], 1, &status[1], 2);
  3768. 18001874: 02110693 addi a3,sp,33
  3769. 18001878: 4605 li a2,1
  3770. 1800187a: 100c addi a1,sp,32
  3771. 1800187c: 4709 li a4,2
  3772. status[0] = CMD_WRITE_STATUS;
  3773. 1800187e: 03011023 sh a6,32(sp)
  3774. status[2] = status2|bit2;
  3775. 18001882: 4809 li a6,2
  3776. 18001884: e03e sd a5,0(sp)
  3777. 18001886: 03010123 sb a6,34(sp)
  3778. spi_flash_write_status(flash, &status[0], 1, &status[1], 2);
  3779. 1800188a: b3fff0ef jal ra,180013c8 <spi_flash_write_status>
  3780. ret &= spi_flash_cmd_poll_bit(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT, CMD_READ_STATUS1, ~bit2);
  3781. 1800188e: 039385b7 lui a1,0x3938
  3782. 18001892: 0fd00693 li a3,253
  3783. 18001896: 03500613 li a2,53
  3784. 1800189a: 70058593 addi a1,a1,1792 # 3938700 <__stack_size+0x3937f00>
  3785. 1800189e: 8522 mv a0,s0
  3786. 180018a0: 921ff0ef jal ra,180011c0 <spi_flash_cmd_poll_bit>
  3787. 180018a4: 6782 ld a5,0(sp)
  3788. return ret;
  3789. 180018a6: bd81 j 180016f6 <spi_flash_cmd_write_mode+0x3a>
  3790. 00000000180018a8 <spi_flash_read_common>:
  3791. int spi_flash_read_common(struct spi_flash *flash, u8 *cmd,
  3792. u32 cmd_len, void *data, u32 data_len)
  3793. {
  3794. 180018a8: 1101 addi sp,sp,-32
  3795. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3796. 180018aa: 0036179b slliw a5,a2,0x3
  3797. {
  3798. 180018ae: e04a sd s2,0(sp)
  3799. 180018b0: ec06 sd ra,24(sp)
  3800. 180018b2: e822 sd s0,16(sp)
  3801. 180018b4: e426 sd s1,8(sp)
  3802. 180018b6: 862e mv a2,a1
  3803. struct spi_slave *spi = flash->spi;
  3804. 180018b8: 00053903 ld s2,0(a0)
  3805. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3806. 180018bc: 0007859b sext.w a1,a5
  3807. if (data_len == 0)
  3808. 180018c0: ef01 bnez a4,180018d8 <spi_flash_read_common+0x30>
  3809. int ret;
  3810. ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
  3811. return ret;
  3812. }
  3813. 180018c2: 6442 ld s0,16(sp)
  3814. 180018c4: 60e2 ld ra,24(sp)
  3815. 180018c6: 64a2 ld s1,8(sp)
  3816. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3817. 180018c8: 854a mv a0,s2
  3818. }
  3819. 180018ca: 6902 ld s2,0(sp)
  3820. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3821. 180018cc: 47a1 li a5,8
  3822. 180018ce: 470d li a4,3
  3823. 180018d0: 4681 li a3,0
  3824. }
  3825. 180018d2: 6105 addi sp,sp,32
  3826. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3827. 180018d4: a00ff06f j 18000ad4 <spi_xfer>
  3828. 180018d8: 843a mv s0,a4
  3829. 180018da: 84b6 mv s1,a3
  3830. 180018dc: 47a1 li a5,8
  3831. 180018de: 4705 li a4,1
  3832. 180018e0: 4681 li a3,0
  3833. 180018e2: 854a mv a0,s2
  3834. 180018e4: 9f0ff0ef jal ra,18000ad4 <spi_xfer>
  3835. if (ret)
  3836. 180018e8: c519 beqz a0,180018f6 <spi_flash_read_common+0x4e>
  3837. }
  3838. 180018ea: 60e2 ld ra,24(sp)
  3839. 180018ec: 6442 ld s0,16(sp)
  3840. 180018ee: 64a2 ld s1,8(sp)
  3841. 180018f0: 6902 ld s2,0(sp)
  3842. 180018f2: 6105 addi sp,sp,32
  3843. 180018f4: 8082 ret
  3844. ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END, SPI_DATAMODE_8);
  3845. 180018f6: 0034159b slliw a1,s0,0x3
  3846. }
  3847. 180018fa: 6442 ld s0,16(sp)
  3848. 180018fc: 60e2 ld ra,24(sp)
  3849. ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END, SPI_DATAMODE_8);
  3850. 180018fe: 86a6 mv a3,s1
  3851. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3852. 18001900: 854a mv a0,s2
  3853. }
  3854. 18001902: 64a2 ld s1,8(sp)
  3855. 18001904: 6902 ld s2,0(sp)
  3856. ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END, SPI_DATAMODE_8);
  3857. 18001906: 47a1 li a5,8
  3858. 18001908: 4709 li a4,2
  3859. 1800190a: 4601 li a2,0
  3860. }
  3861. 1800190c: 6105 addi sp,sp,32
  3862. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3863. 1800190e: 9c6ff06f j 18000ad4 <spi_xfer>
  3864. 0000000018001912 <spi_flash_cmd_read_fast>:
  3865. cmd[2] = (addr & 0x0000FF00) >> 8;
  3866. 18001912: 0105971b slliw a4,a1,0x10
  3867. 18001916: 0107571b srliw a4,a4,0x10
  3868. 1800191a: 0085979b slliw a5,a1,0x8
  3869. 1800191e: 0087571b srliw a4,a4,0x8
  3870. int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
  3871. u32 len, void *data, u32 mode)
  3872. {
  3873. 18001922: 7179 addi sp,sp,-48
  3874. cmd[2] = (addr & 0x0000FF00) >> 8;
  3875. 18001924: 8fd9 or a5,a5,a4
  3876. cmd[1] = (addr & 0x00FF0000) >> 16;
  3877. 18001926: 0105d59b srliw a1,a1,0x10
  3878. u8 cmd[5];
  3879. cmd[0] = CMD_READ_ARRAY_FAST;
  3880. 1800192a: 472d li a4,11
  3881. {
  3882. 1800192c: e84a sd s2,16(sp)
  3883. 1800192e: f406 sd ra,40(sp)
  3884. 18001930: f022 sd s0,32(sp)
  3885. 18001932: ec26 sd s1,24(sp)
  3886. cmd[0] = CMD_READ_ARRAY_FAST;
  3887. 18001934: 00e10423 sb a4,8(sp)
  3888. cmd[1] = (addr & 0x00FF0000) >> 16;
  3889. 18001938: 00b104a3 sb a1,9(sp)
  3890. cmd[2] = (addr & 0x0000FF00) >> 8;
  3891. 1800193c: 00f11523 sh a5,10(sp)
  3892. spi_flash_addr(offset, cmd);
  3893. cmd[4] = 0x00;
  3894. 18001940: 00010623 sb zero,12(sp)
  3895. struct spi_slave *spi = flash->spi;
  3896. 18001944: 00053903 ld s2,0(a0)
  3897. if (data_len == 0)
  3898. 18001948: e205 bnez a2,18001968 <spi_flash_cmd_read_fast+0x56>
  3899. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3900. 1800194a: 47a1 li a5,8
  3901. 1800194c: 470d li a4,3
  3902. 1800194e: 4681 li a3,0
  3903. 18001950: 0030 addi a2,sp,8
  3904. 18001952: 02800593 li a1,40
  3905. 18001956: 854a mv a0,s2
  3906. 18001958: 97cff0ef jal ra,18000ad4 <spi_xfer>
  3907. return spi_flash_read_common(flash, cmd, sizeof(cmd), data, len);
  3908. }
  3909. 1800195c: 70a2 ld ra,40(sp)
  3910. 1800195e: 7402 ld s0,32(sp)
  3911. 18001960: 64e2 ld s1,24(sp)
  3912. 18001962: 6942 ld s2,16(sp)
  3913. 18001964: 6145 addi sp,sp,48
  3914. 18001966: 8082 ret
  3915. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags, SPI_DATAMODE_8);
  3916. 18001968: 8432 mv s0,a2
  3917. 1800196a: 84b6 mv s1,a3
  3918. 1800196c: 47a1 li a5,8
  3919. 1800196e: 4705 li a4,1
  3920. 18001970: 4681 li a3,0
  3921. 18001972: 0030 addi a2,sp,8
  3922. 18001974: 02800593 li a1,40
  3923. 18001978: 854a mv a0,s2
  3924. 1800197a: 95aff0ef jal ra,18000ad4 <spi_xfer>
  3925. if (ret)
  3926. 1800197e: fd79 bnez a0,1800195c <spi_flash_cmd_read_fast+0x4a>
  3927. ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END, SPI_DATAMODE_8);
  3928. 18001980: 0034159b slliw a1,s0,0x3
  3929. 18001984: 86a6 mv a3,s1
  3930. 18001986: 854a mv a0,s2
  3931. 18001988: 47a1 li a5,8
  3932. 1800198a: 4709 li a4,2
  3933. 1800198c: 4601 li a2,0
  3934. 1800198e: 946ff0ef jal ra,18000ad4 <spi_xfer>
  3935. }
  3936. 18001992: 70a2 ld ra,40(sp)
  3937. 18001994: 7402 ld s0,32(sp)
  3938. 18001996: 64e2 ld s1,24(sp)
  3939. 18001998: 6942 ld s2,16(sp)
  3940. 1800199a: 6145 addi sp,sp,48
  3941. 1800199c: 8082 ret
  3942. 000000001800199e <spi_flash_read_mode>:
  3943. int spi_flash_read_mode(struct spi_flash *flash, u32 offset,
  3944. u32 len, void *data, u32 mode)
  3945. {
  3946. 1800199e: 7139 addi sp,sp,-64
  3947. 180019a0: f822 sd s0,48(sp)
  3948. 180019a2: f426 sd s1,40(sp)
  3949. 180019a4: ec4e sd s3,24(sp)
  3950. 180019a6: e852 sd s4,16(sp)
  3951. 180019a8: fc06 sd ra,56(sp)
  3952. 180019aa: f04a sd s2,32(sp)
  3953. int ret;
  3954. int write_data = 0;
  3955. u8 status[2] = {2};
  3956. int i = 0;
  3957. switch (mode)
  3958. 180019ac: 4789 li a5,2
  3959. struct spi_slave *spi = flash->spi;
  3960. 180019ae: 00053a03 ld s4,0(a0)
  3961. {
  3962. 180019b2: 842e mv s0,a1
  3963. 180019b4: 84b2 mv s1,a2
  3964. 180019b6: 89b6 mv s3,a3
  3965. switch (mode)
  3966. 180019b8: 06f70c63 beq a4,a5,18001a30 <spi_flash_read_mode+0x92>
  3967. 180019bc: 4691 li a3,4
  3968. 180019be: 06d70e63 beq a4,a3,18001a3a <spi_flash_read_mode+0x9c>
  3969. {
  3970. case 1:
  3971. cmd[0] = CMD_READ_ARRAY_FAST;
  3972. 180019c2: 47ad li a5,11
  3973. 180019c4: 00f10423 sb a5,8(sp)
  3974. cmd[2] = (addr & 0x0000FF00) >> 8;
  3975. 180019c8: 0104181b slliw a6,s0,0x10
  3976. 180019cc: 0108581b srliw a6,a6,0x10
  3977. 180019d0: 0088579b srliw a5,a6,0x8
  3978. 180019d4: 0084181b slliw a6,s0,0x8
  3979. 180019d8: 00f86833 or a6,a6,a5
  3980. cmd[1] = (addr & 0x00FF0000) >> 16;
  3981. 180019dc: 0104541b srliw s0,s0,0x10
  3982. spi_flash_addr(offset, cmd);
  3983. cmd[4] = 0x00;
  3984. ret = spi_xfer(spi, 5*8, cmd, NULL, SPI_XFER_BEGIN, SPI_DATAMODE_8);
  3985. 180019e0: 47a1 li a5,8
  3986. 180019e2: 4705 li a4,1
  3987. 180019e4: 4681 li a3,0
  3988. 180019e6: 0030 addi a2,sp,8
  3989. 180019e8: 02800593 li a1,40
  3990. 180019ec: 8552 mv a0,s4
  3991. cmd[1] = (addr & 0x00FF0000) >> 16;
  3992. 180019ee: 008104a3 sb s0,9(sp)
  3993. cmd[2] = (addr & 0x0000FF00) >> 8;
  3994. 180019f2: 01011523 sh a6,10(sp)
  3995. cmd[4] = 0x00;
  3996. 180019f6: 00010623 sb zero,12(sp)
  3997. ret = spi_xfer(spi, 5*8, cmd, NULL, SPI_XFER_BEGIN, SPI_DATAMODE_8);
  3998. 180019fa: 8daff0ef jal ra,18000ad4 <spi_xfer>
  3999. if (ret < 0)
  4000. 180019fe: 02054163 bltz a0,18001a20 <spi_flash_read_mode+0x82>
  4001. {
  4002. //uart_printf("xfer failed\n");
  4003. return ret;
  4004. }
  4005. ret = spi_xfer(spi, len*8, NULL, data, SPI_XFER_END, SPI_DATAMODE_8);
  4006. 18001a02: 47a1 li a5,8
  4007. 18001a04: 0034959b slliw a1,s1,0x3
  4008. 18001a08: 4709 li a4,2
  4009. 18001a0a: 86ce mv a3,s3
  4010. 18001a0c: 4601 li a2,0
  4011. 18001a0e: 8552 mv a0,s4
  4012. 18001a10: 8c4ff0ef jal ra,18000ad4 <spi_xfer>
  4013. if (ret < 0)
  4014. 18001a14: 00152793 slti a5,a0,1
  4015. 18001a18: 40f007bb negw a5,a5
  4016. 18001a1c: 8d7d and a0,a0,a5
  4017. 18001a1e: 2501 sext.w a0,a0
  4018. //uart_printf("xfer failed\n");
  4019. return ret;
  4020. }
  4021. return 0;
  4022. }
  4023. 18001a20: 70e2 ld ra,56(sp)
  4024. 18001a22: 7442 ld s0,48(sp)
  4025. 18001a24: 74a2 ld s1,40(sp)
  4026. 18001a26: 7902 ld s2,32(sp)
  4027. 18001a28: 69e2 ld s3,24(sp)
  4028. 18001a2a: 6a42 ld s4,16(sp)
  4029. 18001a2c: 6121 addi sp,sp,64
  4030. 18001a2e: 8082 ret
  4031. cmd[0] = CMD_READ_ARRAY_DUAL;
  4032. 18001a30: 03b00793 li a5,59
  4033. 18001a34: 00f10423 sb a5,8(sp)
  4034. break;
  4035. 18001a38: bf41 j 180019c8 <spi_flash_read_mode+0x2a>
  4036. cmd[0] = CMD_READ_ARRAY_QUAD;
  4037. 18001a3a: 06b00813 li a6,107
  4038. spi_flash_write_status(flash, &status[0], 1, &status[1], 2);
  4039. 18001a3e: 00110693 addi a3,sp,1
  4040. 18001a42: 858a mv a1,sp
  4041. cmd[0] = CMD_READ_ARRAY_QUAD;
  4042. 18001a44: 01010423 sb a6,8(sp)
  4043. spi_flash_write_status(flash, &status[0], 1, &status[1], 2);
  4044. 18001a48: 4605 li a2,1
  4045. status[0] = CMD_WRITE_STATUS;
  4046. 18001a4a: 4805 li a6,1
  4047. spi_flash_write_status(flash, &status[0], 1, &status[1], 2);
  4048. 18001a4c: 4709 li a4,2
  4049. 18001a4e: 892a mv s2,a0
  4050. status[0] = CMD_WRITE_STATUS;
  4051. 18001a50: 01011023 sh a6,0(sp)
  4052. status[2] = status2|bit2;
  4053. 18001a54: 00f10123 sb a5,2(sp)
  4054. spi_flash_write_status(flash, &status[0], 1, &status[1], 2);
  4055. 18001a58: 971ff0ef jal ra,180013c8 <spi_flash_write_status>
  4056. ret &= spi_flash_cmd_poll_bit(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT, CMD_READ_STATUS1, ~bit2);
  4057. 18001a5c: 039385b7 lui a1,0x3938
  4058. 18001a60: 0fd00693 li a3,253
  4059. 18001a64: 03500613 li a2,53
  4060. 18001a68: 70058593 addi a1,a1,1792 # 3938700 <__stack_size+0x3937f00>
  4061. 18001a6c: 854a mv a0,s2
  4062. 18001a6e: f52ff0ef jal ra,180011c0 <spi_flash_cmd_poll_bit>
  4063. return ret;
  4064. 18001a72: bf99 j 180019c8 <spi_flash_read_mode+0x2a>
  4065. 0000000018001a74 <cadence_qspi_apb_exec_flash_cmd>:
  4066. return;
  4067. }
  4068. static int cadence_qspi_apb_exec_flash_cmd(u32 reg_base,
  4069. unsigned int reg)
  4070. {
  4071. 18001a74: 7179 addi sp,sp,-48
  4072. 18001a76: ec26 sd s1,24(sp)
  4073. unsigned int retry = CQSPI_REG_RETRY;
  4074. /* Write the CMDCTRL without start execution. */
  4075. writel(reg, (u32)reg_base + CQSPI_REG_CMDCTRL);
  4076. 18001a78: 0905049b addiw s1,a0,144
  4077. 18001a7c: 1482 slli s1,s1,0x20
  4078. {
  4079. 18001a7e: e84a sd s2,16(sp)
  4080. 18001a80: f406 sd ra,40(sp)
  4081. 18001a82: f022 sd s0,32(sp)
  4082. 18001a84: e44e sd s3,8(sp)
  4083. 18001a86: 892a mv s2,a0
  4084. writel(reg, (u32)reg_base + CQSPI_REG_CMDCTRL);
  4085. 18001a88: 9081 srli s1,s1,0x20
  4086. 18001a8a: c08c sw a1,0(s1)
  4087. /* Start execute */
  4088. reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
  4089. 18001a8c: 0015e593 ori a1,a1,1
  4090. 18001a90: c08c sw a1,0(s1)
  4091. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  4092. 18001a92: 409c lw a5,0(s1)
  4093. writel(reg, (u32)reg_base + CQSPI_REG_CMDCTRL);
  4094. while (retry--) {
  4095. reg = readl((u32)reg_base + CQSPI_REG_CMDCTRL);
  4096. if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS_MASK) == 0)
  4097. 18001a94: 8b89 andi a5,a5,2
  4098. 18001a96: c78d beqz a5,18001ac0 <cadence_qspi_apb_exec_flash_cmd+0x4c>
  4099. break;
  4100. delay(1000);
  4101. 18001a98: 3e800513 li a0,1000
  4102. while (retry--) {
  4103. 18001a9c: 6409 lui s0,0x2
  4104. delay(1000);
  4105. 18001a9e: 7c2000ef jal ra,18002260 <udelay>
  4106. while (retry--) {
  4107. 18001aa2: 70e40413 addi s0,s0,1806 # 270e <__stack_size+0x1f0e>
  4108. 18001aa6: 59fd li s3,-1
  4109. 18001aa8: a031 j 18001ab4 <cadence_qspi_apb_exec_flash_cmd+0x40>
  4110. 18001aaa: 347d addiw s0,s0,-1
  4111. delay(1000);
  4112. 18001aac: 7b4000ef jal ra,18002260 <udelay>
  4113. while (retry--) {
  4114. 18001ab0: 01340863 beq s0,s3,18001ac0 <cadence_qspi_apb_exec_flash_cmd+0x4c>
  4115. 18001ab4: 409c lw a5,0(s1)
  4116. if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS_MASK) == 0)
  4117. 18001ab6: 8b89 andi a5,a5,2
  4118. delay(1000);
  4119. 18001ab8: 3e800513 li a0,1000
  4120. if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS_MASK) == 0)
  4121. 18001abc: f7fd bnez a5,18001aaa <cadence_qspi_apb_exec_flash_cmd+0x36>
  4122. }
  4123. if (!retry) {
  4124. 18001abe: c415 beqz s0,18001aea <cadence_qspi_apb_exec_flash_cmd+0x76>
  4125. //uart_printf("QSPI: flash command execution timeout\n");
  4126. return -1;
  4127. }
  4128. /* Polling QSPI idle status. */
  4129. if (!cadence_qspi_wait_idle(reg_base))
  4130. 18001ac0: 02091693 slli a3,s2,0x20
  4131. 18001ac4: 6709 lui a4,0x2
  4132. 18001ac6: 9281 srli a3,a3,0x20
  4133. 18001ac8: 71070713 addi a4,a4,1808 # 2710 <__stack_size+0x1f10>
  4134. 18001acc: a011 j 18001ad0 <cadence_qspi_apb_exec_flash_cmd+0x5c>
  4135. if (count >= CQSPI_REG_RETRY)
  4136. 18001ace: c711 beqz a4,18001ada <cadence_qspi_apb_exec_flash_cmd+0x66>
  4137. 18001ad0: 429c lw a5,0(a3)
  4138. if (CQSPI_REG_IS_IDLE((u32)reg_base))
  4139. 18001ad2: 2781 sext.w a5,a5
  4140. if (count >= CQSPI_REG_RETRY)
  4141. 18001ad4: 377d addiw a4,a4,-1
  4142. if (CQSPI_REG_IS_IDLE((u32)reg_base))
  4143. 18001ad6: fe07dce3 bgez a5,18001ace <cadence_qspi_apb_exec_flash_cmd+0x5a>
  4144. return -1;
  4145. return 0;
  4146. 18001ada: 4501 li a0,0
  4147. }
  4148. 18001adc: 70a2 ld ra,40(sp)
  4149. 18001ade: 7402 ld s0,32(sp)
  4150. 18001ae0: 64e2 ld s1,24(sp)
  4151. 18001ae2: 6942 ld s2,16(sp)
  4152. 18001ae4: 69a2 ld s3,8(sp)
  4153. 18001ae6: 6145 addi sp,sp,48
  4154. 18001ae8: 8082 ret
  4155. return -1;
  4156. 18001aea: 557d li a0,-1
  4157. 18001aec: bfc5 j 18001adc <cadence_qspi_apb_exec_flash_cmd+0x68>
  4158. 0000000018001aee <cadence_qspi_apb_controller_enable>:
  4159. reg = readl((u32)reg_base + CQSPI_REG_CONFIG);
  4160. 18001aee: 1502 slli a0,a0,0x20
  4161. 18001af0: 9101 srli a0,a0,0x20
  4162. 18001af2: 411c lw a5,0(a0)
  4163. reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
  4164. 18001af4: 0017e793 ori a5,a5,1
  4165. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  4166. 18001af8: c11c sw a5,0(a0)
  4167. }
  4168. 18001afa: 8082 ret
  4169. 0000000018001afc <cadence_qspi_apb_controller_disable>:
  4170. reg = readl((u32)reg_base + CQSPI_REG_CONFIG);
  4171. 18001afc: 1502 slli a0,a0,0x20
  4172. 18001afe: 9101 srli a0,a0,0x20
  4173. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  4174. 18001b00: 411c lw a5,0(a0)
  4175. reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
  4176. 18001b02: 9bf9 andi a5,a5,-2
  4177. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  4178. 18001b04: c11c sw a5,0(a0)
  4179. }
  4180. 18001b06: 8082 ret
  4181. 0000000018001b08 <cadence_qspi_apb_readdata_capture>:
  4182. reg = readl((u32)reg_base + CQSPI_REG_CONFIG);
  4183. 18001b08: 02051713 slli a4,a0,0x20
  4184. 18001b0c: 9301 srli a4,a4,0x20
  4185. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  4186. 18001b0e: 431c lw a5,0(a4)
  4187. reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
  4188. 18001b10: 9bf9 andi a5,a5,-2
  4189. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  4190. 18001b12: c31c sw a5,0(a4)
  4191. reg = readl((u32)reg_base + CQSPI_READLCAPTURE);
  4192. 18001b14: 2541 addiw a0,a0,16
  4193. 18001b16: 1502 slli a0,a0,0x20
  4194. 18001b18: 9101 srli a0,a0,0x20
  4195. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  4196. 18001b1a: 411c lw a5,0(a0)
  4197. if (bypass)
  4198. 18001b1c: cd99 beqz a1,18001b3a <cadence_qspi_apb_readdata_capture+0x32>
  4199. reg |= (1 << CQSPI_READLCAPTURE_BYPASS_LSB);
  4200. 18001b1e: 0017e793 ori a5,a5,1
  4201. 18001b22: 2781 sext.w a5,a5
  4202. << CQSPI_READLCAPTURE_DELAY_LSB);
  4203. 18001b24: 0016161b slliw a2,a2,0x1
  4204. reg &= ~(CQSPI_READLCAPTURE_DELAY_MASK
  4205. 18001b28: 9b85 andi a5,a5,-31
  4206. << CQSPI_READLCAPTURE_DELAY_LSB);
  4207. 18001b2a: 8a79 andi a2,a2,30
  4208. reg |= ((delay & CQSPI_READLCAPTURE_DELAY_MASK)
  4209. 18001b2c: 8e5d or a2,a2,a5
  4210. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  4211. 18001b2e: c110 sw a2,0(a0)
  4212. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  4213. 18001b30: 431c lw a5,0(a4)
  4214. reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
  4215. 18001b32: 0017e793 ori a5,a5,1
  4216. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  4217. 18001b36: c31c sw a5,0(a4)
  4218. }
  4219. 18001b38: 8082 ret
  4220. reg &= ~(1 << CQSPI_READLCAPTURE_BYPASS_LSB);
  4221. 18001b3a: 9bf9 andi a5,a5,-2
  4222. 18001b3c: 2781 sext.w a5,a5
  4223. 18001b3e: b7dd j 18001b24 <cadence_qspi_apb_readdata_capture+0x1c>
  4224. 0000000018001b40 <cadence_qspi_apb_config_baudrate_div>:
  4225. reg = readl((u32)reg_base + CQSPI_REG_CONFIG);
  4226. 18001b40: 1502 slli a0,a0,0x20
  4227. 18001b42: 9101 srli a0,a0,0x20
  4228. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  4229. 18001b44: 411c lw a5,0(a0)
  4230. reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
  4231. 18001b46: 9bf9 andi a5,a5,-2
  4232. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  4233. 18001b48: c11c sw a5,0(a0)
  4234. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  4235. 18001b4a: 4114 lw a3,0(a0)
  4236. div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1;
  4237. 18001b4c: 0016161b slliw a2,a2,0x1
  4238. 18001b50: 35fd addiw a1,a1,-1
  4239. 18001b52: 00c587bb addw a5,a1,a2
  4240. 18001b56: 02c7d7bb divuw a5,a5,a2
  4241. reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
  4242. 18001b5a: ff880737 lui a4,0xff880
  4243. 18001b5e: 177d addi a4,a4,-1
  4244. 18001b60: 8f75 and a4,a4,a3
  4245. div = (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
  4246. 18001b62: 46bd li a3,15
  4247. reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
  4248. 18001b64: 2701 sext.w a4,a4
  4249. div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1;
  4250. 18001b66: fff7861b addiw a2,a5,-1
  4251. 18001b6a: 87b2 mv a5,a2
  4252. div = (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
  4253. 18001b6c: 00c6f363 bgeu a3,a2,18001b72 <cadence_qspi_apb_config_baudrate_div+0x32>
  4254. 18001b70: 47bd li a5,15
  4255. 18001b72: 0137979b slliw a5,a5,0x13
  4256. reg |= div;
  4257. 18001b76: 8fd9 or a5,a5,a4
  4258. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  4259. 18001b78: c11c sw a5,0(a0)
  4260. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  4261. 18001b7a: 411c lw a5,0(a0)
  4262. reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
  4263. 18001b7c: 0017e793 ori a5,a5,1
  4264. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  4265. 18001b80: c11c sw a5,0(a0)
  4266. }
  4267. 18001b82: 8082 ret
  4268. 0000000018001b84 <cadence_qspi_apb_set_clk_mode>:
  4269. reg = readl((u32)reg_base + CQSPI_REG_CONFIG);
  4270. 18001b84: 1502 slli a0,a0,0x20
  4271. 18001b86: 9101 srli a0,a0,0x20
  4272. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  4273. 18001b88: 411c lw a5,0(a0)
  4274. reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
  4275. 18001b8a: 9bf9 andi a5,a5,-2
  4276. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  4277. 18001b8c: c11c sw a5,0(a0)
  4278. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  4279. 18001b8e: 411c lw a5,0(a0)
  4280. reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB);
  4281. 18001b90: 0015959b slliw a1,a1,0x1
  4282. reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB);
  4283. 18001b94: 0026161b slliw a2,a2,0x2
  4284. 18001b98: 8a11 andi a2,a2,4
  4285. reg &= ~(1 <<
  4286. 18001b9a: 9bdd andi a5,a5,-9
  4287. reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB);
  4288. 18001b9c: 8989 andi a1,a1,2
  4289. reg &= ~(1 <<
  4290. 18001b9e: 2781 sext.w a5,a5
  4291. reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB);
  4292. 18001ba0: 8dd1 or a1,a1,a2
  4293. 18001ba2: 8ddd or a1,a1,a5
  4294. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  4295. 18001ba4: c10c sw a1,0(a0)
  4296. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  4297. 18001ba6: 411c lw a5,0(a0)
  4298. reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
  4299. 18001ba8: 0017e793 ori a5,a5,1
  4300. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  4301. 18001bac: c11c sw a5,0(a0)
  4302. }
  4303. 18001bae: 8082 ret
  4304. 0000000018001bb0 <cadence_qspi_apb_chipselect>:
  4305. reg = readl((u32)reg_base + CQSPI_REG_CONFIG);
  4306. 18001bb0: 1502 slli a0,a0,0x20
  4307. 18001bb2: 9101 srli a0,a0,0x20
  4308. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  4309. 18001bb4: 411c lw a5,0(a0)
  4310. reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
  4311. 18001bb6: 9bf9 andi a5,a5,-2
  4312. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  4313. 18001bb8: c11c sw a5,0(a0)
  4314. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  4315. 18001bba: 411c lw a5,0(a0)
  4316. if (decoder_enable) {
  4317. 18001bbc: c60d beqz a2,18001be6 <cadence_qspi_apb_chipselect+0x36>
  4318. reg |= CQSPI_REG_CONFIG_DECODE_MASK;
  4319. 18001bbe: 2007e793 ori a5,a5,512
  4320. 18001bc2: 2781 sext.w a5,a5
  4321. reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
  4322. 18001bc4: 7771 lui a4,0xffffc
  4323. 18001bc6: 3ff70713 addi a4,a4,1023 # ffffffffffffc3ff <_sp+0xffffffffe7fea29f>
  4324. 18001bca: 8ff9 and a5,a5,a4
  4325. << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
  4326. 18001bcc: 6711 lui a4,0x4
  4327. 18001bce: c0070713 addi a4,a4,-1024 # 3c00 <__stack_size+0x3400>
  4328. 18001bd2: 00a5959b slliw a1,a1,0xa
  4329. 18001bd6: 8df9 and a1,a1,a4
  4330. reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
  4331. 18001bd8: 8ddd or a1,a1,a5
  4332. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  4333. 18001bda: c10c sw a1,0(a0)
  4334. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  4335. 18001bdc: 411c lw a5,0(a0)
  4336. reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
  4337. 18001bde: 0017e793 ori a5,a5,1
  4338. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  4339. 18001be2: c11c sw a5,0(a0)
  4340. }
  4341. 18001be4: 8082 ret
  4342. chip_select = 0xF & ~(1 << chip_select);
  4343. 18001be6: 4705 li a4,1
  4344. 18001be8: 00b715bb sllw a1,a4,a1
  4345. reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
  4346. 18001bec: dff7f793 andi a5,a5,-513
  4347. chip_select = 0xF & ~(1 << chip_select);
  4348. 18001bf0: fff5c593 not a1,a1
  4349. reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
  4350. 18001bf4: 2781 sext.w a5,a5
  4351. chip_select = 0xF & ~(1 << chip_select);
  4352. 18001bf6: 89bd andi a1,a1,15
  4353. 18001bf8: b7f1 j 18001bc4 <cadence_qspi_apb_chipselect+0x14>
  4354. 0000000018001bfa <cadence_qspi_apb_delay>:
  4355. reg = readl((u32)reg_base + CQSPI_REG_CONFIG);
  4356. 18001bfa: 02051793 slli a5,a0,0x20
  4357. 18001bfe: 9381 srli a5,a5,0x20
  4358. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  4359. 18001c00: 4398 lw a4,0(a5)
  4360. reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
  4361. 18001c02: 9b79 andi a4,a4,-2
  4362. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  4363. 18001c04: c398 sw a4,0(a5)
  4364. writel(reg, (u32)reg_base + CQSPI_REG_DELAY);
  4365. 18001c06: 2531 addiw a0,a0,12
  4366. 18001c08: 1502 slli a0,a0,0x20
  4367. 18001c0a: 01010737 lui a4,0x1010
  4368. 18001c0e: 9101 srli a0,a0,0x20
  4369. 18001c10: 1017071b addiw a4,a4,257
  4370. 18001c14: c118 sw a4,0(a0)
  4371. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  4372. 18001c16: 4398 lw a4,0(a5)
  4373. reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
  4374. 18001c18: 00176713 ori a4,a4,1
  4375. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  4376. 18001c1c: c398 sw a4,0(a5)
  4377. }
  4378. 18001c1e: 8082 ret
  4379. 0000000018001c20 <cadence_qspi_apb_controller_init>:
  4380. reg = readl((u32)reg_base + CQSPI_REG_CONFIG);
  4381. 18001c20: 651c ld a5,8(a0)
  4382. 18001c22: 02079613 slli a2,a5,0x20
  4383. 18001c26: 9201 srli a2,a2,0x20
  4384. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  4385. 18001c28: 4218 lw a4,0(a2)
  4386. reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
  4387. 18001c2a: 9b79 andi a4,a4,-2
  4388. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  4389. 18001c2c: c218 sw a4,0(a2)
  4390. reg = readl((u32)plat->regbase + CQSPI_REG_SIZE);
  4391. 18001c2e: 0147859b addiw a1,a5,20
  4392. 18001c32: 1582 slli a1,a1,0x20
  4393. 18001c34: 2781 sext.w a5,a5
  4394. 18001c36: 9181 srli a1,a1,0x20
  4395. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  4396. 18001c38: 0005a883 lw a7,0(a1)
  4397. reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);
  4398. 18001c3c: 4d58 lw a4,28(a0)
  4399. reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
  4400. 18001c3e: 02052803 lw a6,32(a0)
  4401. reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
  4402. 18001c42: ffc006b7 lui a3,0xffc00
  4403. 18001c46: 06bd addi a3,a3,15
  4404. 18001c48: 0116f6b3 and a3,a3,a7
  4405. reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
  4406. 18001c4c: 0108181b slliw a6,a6,0x10
  4407. reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);
  4408. 18001c50: 0047171b slliw a4,a4,0x4
  4409. reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
  4410. 18001c54: 2681 sext.w a3,a3
  4411. reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
  4412. 18001c56: 01076733 or a4,a4,a6
  4413. 18001c5a: 8f55 or a4,a4,a3
  4414. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  4415. 18001c5c: c198 sw a4,0(a1)
  4416. writel(0,(u32) plat->regbase + CQSPI_REG_REMAP);
  4417. 18001c5e: 0247871b addiw a4,a5,36
  4418. 18001c62: 1702 slli a4,a4,0x20
  4419. 18001c64: 4581 li a1,0
  4420. 18001c66: 9301 srli a4,a4,0x20
  4421. 18001c68: c30c sw a1,0(a4)
  4422. writel((plat->sram_size/2), (u32)plat->regbase + CQSPI_REG_SRAMPARTITION);
  4423. 18001c6a: 5958 lw a4,52(a0)
  4424. 18001c6c: 0187869b addiw a3,a5,24
  4425. 18001c70: 1682 slli a3,a3,0x20
  4426. 18001c72: 9281 srli a3,a3,0x20
  4427. 18001c74: 0017571b srliw a4,a4,0x1
  4428. 18001c78: c298 sw a4,0(a3)
  4429. writel(0, (u32)plat->regbase + CQSPI_REG_IRQMASK);
  4430. 18001c7a: 0447879b addiw a5,a5,68
  4431. 18001c7e: 1782 slli a5,a5,0x20
  4432. 18001c80: 9381 srli a5,a5,0x20
  4433. 18001c82: c38c sw a1,0(a5)
  4434. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  4435. 18001c84: 421c lw a5,0(a2)
  4436. reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
  4437. 18001c86: 0017e793 ori a5,a5,1
  4438. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  4439. 18001c8a: c21c sw a5,0(a2)
  4440. }
  4441. 18001c8c: 8082 ret
  4442. 0000000018001c8e <cadence_qspi_apb_command_read>:
  4443. /* For command RDID, RDSR. */
  4444. int cadence_qspi_apb_command_read(void * reg_base,
  4445. unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen,
  4446. u8 *rxbuf)
  4447. {
  4448. 18001c8e: 7139 addi sp,sp,-64
  4449. 18001c90: fc06 sd ra,56(sp)
  4450. 18001c92: f822 sd s0,48(sp)
  4451. 18001c94: f426 sd s1,40(sp)
  4452. 18001c96: f04a sd s2,32(sp)
  4453. 18001c98: ec4e sd s3,24(sp)
  4454. 18001c9a: e852 sd s4,16(sp)
  4455. unsigned int reg;
  4456. unsigned int read_len;
  4457. int status;
  4458. if (!cmdlen || rxlen > CQSPI_STIG_DATA_LEN_MAX || rxbuf == NULL) {
  4459. 18001c9c: cdc1 beqz a1,18001d34 <cadence_qspi_apb_command_read+0xa6>
  4460. 18001c9e: 47a1 li a5,8
  4461. 18001ca0: 84b6 mv s1,a3
  4462. 18001ca2: 08d7e963 bltu a5,a3,18001d34 <cadence_qspi_apb_command_read+0xa6>
  4463. 18001ca6: 89ba mv s3,a4
  4464. 18001ca8: c751 beqz a4,18001d34 <cadence_qspi_apb_command_read+0xa6>
  4465. //uart_printf("QSPI: Invalid input arguments cmdlen %d rxlen %d\n",
  4466. //cmdlen, rxlen);
  4467. return -1;
  4468. }
  4469. reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
  4470. 18001caa: 00064783 lbu a5,0(a2)
  4471. reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
  4472. /* 0 means 1 byte. */
  4473. reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
  4474. 18001cae: fff6859b addiw a1,a3,-1
  4475. << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
  4476. 18001cb2: 00700737 lui a4,0x700
  4477. 18001cb6: 0145959b slliw a1,a1,0x14
  4478. 18001cba: 8df9 and a1,a1,a4
  4479. reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
  4480. 18001cbc: 0187979b slliw a5,a5,0x18
  4481. reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
  4482. 18001cc0: 8ddd or a1,a1,a5
  4483. 18001cc2: 008007b7 lui a5,0x800
  4484. 18001cc6: 8ddd or a1,a1,a5
  4485. status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
  4486. 18001cc8: 0005041b sext.w s0,a0
  4487. reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
  4488. 18001ccc: 2581 sext.w a1,a1
  4489. status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
  4490. 18001cce: 8522 mv a0,s0
  4491. reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
  4492. 18001cd0: c62e sw a1,12(sp)
  4493. status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
  4494. 18001cd2: da3ff0ef jal ra,18001a74 <cadence_qspi_apb_exec_flash_cmd>
  4495. 18001cd6: 892a mv s2,a0
  4496. if (status != 0)
  4497. 18001cd8: c911 beqz a0,18001cec <cadence_qspi_apb_command_read+0x5e>
  4498. read_len = rxlen - read_len;
  4499. sys_memcpy(rxbuf, &reg, read_len);
  4500. }
  4501. return 0;
  4502. }
  4503. 18001cda: 70e2 ld ra,56(sp)
  4504. 18001cdc: 7442 ld s0,48(sp)
  4505. 18001cde: 74a2 ld s1,40(sp)
  4506. 18001ce0: 69e2 ld s3,24(sp)
  4507. 18001ce2: 6a42 ld s4,16(sp)
  4508. 18001ce4: 854a mv a0,s2
  4509. 18001ce6: 7902 ld s2,32(sp)
  4510. 18001ce8: 6121 addi sp,sp,64
  4511. 18001cea: 8082 ret
  4512. reg = readl((u32)reg_base + CQSPI_REG_CMDREADDATALOWER);
  4513. 18001cec: 0a04079b addiw a5,s0,160
  4514. 18001cf0: 1782 slli a5,a5,0x20
  4515. 18001cf2: 9381 srli a5,a5,0x20
  4516. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  4517. 18001cf4: 439c lw a5,0(a5)
  4518. read_len = (rxlen > 4) ? 4 : rxlen;
  4519. 18001cf6: 4711 li a4,4
  4520. reg = readl((u32)reg_base + CQSPI_REG_CMDREADDATALOWER);
  4521. 18001cf8: c63e sw a5,12(sp)
  4522. read_len = (rxlen > 4) ? 4 : rxlen;
  4523. 18001cfa: 8a26 mv s4,s1
  4524. 18001cfc: 00977363 bgeu a4,s1,18001d02 <cadence_qspi_apb_command_read+0x74>
  4525. 18001d00: 4a11 li s4,4
  4526. sys_memcpy(rxbuf, &reg, read_len);
  4527. 18001d02: 000a061b sext.w a2,s4
  4528. 18001d06: 006c addi a1,sp,12
  4529. 18001d08: 854e mv a0,s3
  4530. 18001d0a: d05fe0ef jal ra,18000a0e <sys_memcpy>
  4531. if (rxlen > 4) {
  4532. 18001d0e: 4791 li a5,4
  4533. 18001d10: fc97f5e3 bgeu a5,s1,18001cda <cadence_qspi_apb_command_read+0x4c>
  4534. reg = readl((u32)reg_base + CQSPI_REG_CMDREADDATAUPPER);
  4535. 18001d14: 0a44041b addiw s0,s0,164
  4536. 18001d18: 1402 slli s0,s0,0x20
  4537. 18001d1a: 9001 srli s0,s0,0x20
  4538. 18001d1c: 4000 lw s0,0(s0)
  4539. rxbuf += read_len;
  4540. 18001d1e: 020a1513 slli a0,s4,0x20
  4541. 18001d22: 9101 srli a0,a0,0x20
  4542. sys_memcpy(rxbuf, &reg, read_len);
  4543. 18001d24: 4144863b subw a2,s1,s4
  4544. 18001d28: 006c addi a1,sp,12
  4545. 18001d2a: 954e add a0,a0,s3
  4546. reg = readl((u32)reg_base + CQSPI_REG_CMDREADDATAUPPER);
  4547. 18001d2c: c622 sw s0,12(sp)
  4548. sys_memcpy(rxbuf, &reg, read_len);
  4549. 18001d2e: ce1fe0ef jal ra,18000a0e <sys_memcpy>
  4550. 18001d32: b765 j 18001cda <cadence_qspi_apb_command_read+0x4c>
  4551. return -1;
  4552. 18001d34: 597d li s2,-1
  4553. 18001d36: b755 j 18001cda <cadence_qspi_apb_command_read+0x4c>
  4554. 0000000018001d38 <cadence_qspi_apb_command_write>:
  4555. unsigned int reg = 0;
  4556. unsigned int addr_value;
  4557. unsigned int wr_data;
  4558. unsigned int wr_len;
  4559. if (!cmdlen || cmdlen > 5 || txlen > 8 || cmdbuf == NULL) {
  4560. 18001d38: fff5881b addiw a6,a1,-1
  4561. 18001d3c: 4791 li a5,4
  4562. 18001d3e: 1107e163 bltu a5,a6,18001e40 <cadence_qspi_apb_command_write+0x108>
  4563. {
  4564. 18001d42: 7139 addi sp,sp,-64
  4565. 18001d44: f04a sd s2,32(sp)
  4566. 18001d46: fc06 sd ra,56(sp)
  4567. 18001d48: f822 sd s0,48(sp)
  4568. 18001d4a: f426 sd s1,40(sp)
  4569. 18001d4c: ec4e sd s3,24(sp)
  4570. 18001d4e: e852 sd s4,16(sp)
  4571. if (!cmdlen || cmdlen > 5 || txlen > 8 || cmdbuf == NULL) {
  4572. 18001d50: 47a1 li a5,8
  4573. 18001d52: 8936 mv s2,a3
  4574. 18001d54: 0ed7e463 bltu a5,a3,18001e3c <cadence_qspi_apb_command_write+0x104>
  4575. 18001d58: c275 beqz a2,18001e3c <cadence_qspi_apb_command_write+0x104>
  4576. //uart_printf("QSPI: Invalid input arguments cmdlen %d txlen %d\n",
  4577. //cmdlen, txlen);
  4578. return -1;
  4579. }
  4580. reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
  4581. 18001d5a: 00064803 lbu a6,0(a2)
  4582. 18001d5e: 89ba mv s3,a4
  4583. if (cmdlen == 4 || cmdlen == 5) {
  4584. 18001d60: ffc5879b addiw a5,a1,-4
  4585. reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
  4586. 18001d64: 0188181b slliw a6,a6,0x18
  4587. if (cmdlen == 4 || cmdlen == 5) {
  4588. 18001d68: 4705 li a4,1
  4589. reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
  4590. 18001d6a: 0008049b sext.w s1,a6
  4591. << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
  4592. /* Get address */
  4593. addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1],
  4594. cmdlen >= 5 ? 4 : 3);
  4595. writel(addr_value, (u32)reg_base + CQSPI_REG_CMDADDRESS);
  4596. 18001d6e: 0005041b sext.w s0,a0
  4597. if (cmdlen == 4 || cmdlen == 5) {
  4598. 18001d72: 02f77063 bgeu a4,a5,18001d92 <cadence_qspi_apb_command_write+0x5a>
  4599. }
  4600. if (txlen) {
  4601. 18001d76: 06091663 bnez s2,18001de2 <cadence_qspi_apb_command_write+0xaa>
  4602. CQSPI_REG_CMDWRITEDATAUPPER);
  4603. }
  4604. }
  4605. /* Execute the command */
  4606. return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
  4607. 18001d7a: 85a6 mv a1,s1
  4608. 18001d7c: 8522 mv a0,s0
  4609. 18001d7e: cf7ff0ef jal ra,18001a74 <cadence_qspi_apb_exec_flash_cmd>
  4610. }
  4611. 18001d82: 70e2 ld ra,56(sp)
  4612. 18001d84: 7442 ld s0,48(sp)
  4613. 18001d86: 74a2 ld s1,40(sp)
  4614. 18001d88: 7902 ld s2,32(sp)
  4615. 18001d8a: 69e2 ld s3,24(sp)
  4616. 18001d8c: 6a42 ld s4,16(sp)
  4617. 18001d8e: 6121 addi sp,sp,64
  4618. 18001d90: 8082 ret
  4619. addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
  4620. 18001d92: 00164783 lbu a5,1(a2)
  4621. 18001d96: 00264703 lbu a4,2(a2)
  4622. 18001d9a: 00364683 lbu a3,3(a2)
  4623. reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
  4624. 18001d9e: ffe5849b addiw s1,a1,-2
  4625. addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
  4626. 18001da2: 0087171b slliw a4,a4,0x8
  4627. << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
  4628. 18001da6: 0104949b slliw s1,s1,0x10
  4629. addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
  4630. 18001daa: 0107979b slliw a5,a5,0x10
  4631. reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
  4632. 18001dae: 0104e4b3 or s1,s1,a6
  4633. addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
  4634. 18001db2: 8fd9 or a5,a5,a4
  4635. reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
  4636. 18001db4: 00080837 lui a6,0x80
  4637. 18001db8: 0104e4b3 or s1,s1,a6
  4638. addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
  4639. 18001dbc: 8fd5 or a5,a5,a3
  4640. addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1],
  4641. 18001dbe: 4715 li a4,5
  4642. reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
  4643. 18001dc0: 2481 sext.w s1,s1
  4644. addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
  4645. 18001dc2: 2781 sext.w a5,a5
  4646. addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1],
  4647. 18001dc4: 00e59863 bne a1,a4,18001dd4 <cadence_qspi_apb_command_write+0x9c>
  4648. addr = (addr << 8) | addr_buf[3];
  4649. 18001dc8: 00464703 lbu a4,4(a2)
  4650. 18001dcc: 0087979b slliw a5,a5,0x8
  4651. 18001dd0: 8fd9 or a5,a5,a4
  4652. 18001dd2: 2781 sext.w a5,a5
  4653. writel(addr_value, (u32)reg_base + CQSPI_REG_CMDADDRESS);
  4654. 18001dd4: 0944071b addiw a4,s0,148
  4655. 18001dd8: 1702 slli a4,a4,0x20
  4656. 18001dda: 9301 srli a4,a4,0x20
  4657. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  4658. 18001ddc: c31c sw a5,0(a4)
  4659. if (txlen) {
  4660. 18001dde: f8090ee3 beqz s2,18001d7a <cadence_qspi_apb_command_write+0x42>
  4661. reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
  4662. 18001de2: fff9079b addiw a5,s2,-1
  4663. << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
  4664. 18001de6: 00c7979b slliw a5,a5,0xc
  4665. 18001dea: 8cdd or s1,s1,a5
  4666. reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
  4667. 18001dec: 67a1 lui a5,0x8
  4668. 18001dee: 8cdd or s1,s1,a5
  4669. wr_len = txlen > 4 ? 4 : txlen;
  4670. 18001df0: 4791 li a5,4
  4671. reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
  4672. 18001df2: 2481 sext.w s1,s1
  4673. wr_len = txlen > 4 ? 4 : txlen;
  4674. 18001df4: 8a4a mv s4,s2
  4675. 18001df6: 0527e163 bltu a5,s2,18001e38 <cadence_qspi_apb_command_write+0x100>
  4676. sys_memcpy(&wr_data, txbuf, wr_len);
  4677. 18001dfa: 000a061b sext.w a2,s4
  4678. 18001dfe: 85ce mv a1,s3
  4679. 18001e00: 0068 addi a0,sp,12
  4680. 18001e02: c0dfe0ef jal ra,18000a0e <sys_memcpy>
  4681. writel(wr_data, (u32)reg_base +
  4682. 18001e06: 0a84079b addiw a5,s0,168
  4683. 18001e0a: 1782 slli a5,a5,0x20
  4684. 18001e0c: 4732 lw a4,12(sp)
  4685. 18001e0e: 9381 srli a5,a5,0x20
  4686. 18001e10: c398 sw a4,0(a5)
  4687. if (txlen > 4) {
  4688. 18001e12: 4791 li a5,4
  4689. 18001e14: f727f3e3 bgeu a5,s2,18001d7a <cadence_qspi_apb_command_write+0x42>
  4690. txbuf += wr_len;
  4691. 18001e18: 020a1593 slli a1,s4,0x20
  4692. 18001e1c: 9181 srli a1,a1,0x20
  4693. sys_memcpy(&wr_data, txbuf, wr_len);
  4694. 18001e1e: 4149063b subw a2,s2,s4
  4695. 18001e22: 95ce add a1,a1,s3
  4696. 18001e24: 0068 addi a0,sp,12
  4697. 18001e26: be9fe0ef jal ra,18000a0e <sys_memcpy>
  4698. writel(wr_data, (u32)reg_base +
  4699. 18001e2a: 0ac4079b addiw a5,s0,172
  4700. 18001e2e: 1782 slli a5,a5,0x20
  4701. 18001e30: 4732 lw a4,12(sp)
  4702. 18001e32: 9381 srli a5,a5,0x20
  4703. 18001e34: c398 sw a4,0(a5)
  4704. }
  4705. 18001e36: b791 j 18001d7a <cadence_qspi_apb_command_write+0x42>
  4706. wr_len = txlen > 4 ? 4 : txlen;
  4707. 18001e38: 4a11 li s4,4
  4708. 18001e3a: b7c1 j 18001dfa <cadence_qspi_apb_command_write+0xc2>
  4709. return -1;
  4710. 18001e3c: 557d li a0,-1
  4711. 18001e3e: b791 j 18001d82 <cadence_qspi_apb_command_write+0x4a>
  4712. 18001e40: 557d li a0,-1
  4713. }
  4714. 18001e42: 8082 ret
  4715. 0000000018001e44 <cadence_qspi_apb_indirect_read_setup>:
  4716. * which always expecting 1 dummy byte, 1 cmd byte and 3/4 addr byte.
  4717. * With that, the length is in value of 5 or 6. Only FRAM chip from
  4718. * ramtron using normal read (which won't need dummy byte).
  4719. * Unlikely NOR flash using normal read due to performance issue.
  4720. */
  4721. if (cmdlen >= 5)
  4722. 18001e44: 4791 li a5,4
  4723. 18001e46: 0ab7e163 bltu a5,a1,18001ee8 <cadence_qspi_apb_indirect_read_setup+0xa4>
  4724. /* to cater fast read where cmd + addr + dummy */
  4725. addr_bytes = cmdlen - 2;
  4726. else
  4727. /* for normal read (only ramtron as of now) */
  4728. addr_bytes = cmdlen - 1;
  4729. 18001e4a: 35fd addiw a1,a1,-1
  4730. 18001e4c: 4801 li a6,0
  4731. /* Setup the indirect trigger address */
  4732. writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
  4733. (u32)plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
  4734. 18001e4e: 4518 lw a4,8(a0)
  4735. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  4736. 18001e50: 4681 li a3,0
  4737. 18001e52: 01c7079b addiw a5,a4,28
  4738. 18001e56: 1782 slli a5,a5,0x20
  4739. 18001e58: 9381 srli a5,a5,0x20
  4740. 18001e5a: c394 sw a3,0(a5)
  4741. /* Configure the opcode */
  4742. rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
  4743. 18001e5c: 00064783 lbu a5,0(a2)
  4744. if(plat->bit_mode == 4)
  4745. 18001e60: 03852883 lw a7,56(a0)
  4746. 18001e64: 4691 li a3,4
  4747. rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
  4748. 18001e66: 0007851b sext.w a0,a5
  4749. if(plat->bit_mode == 4)
  4750. 18001e6a: 00d89763 bne a7,a3,18001e78 <cadence_qspi_apb_indirect_read_setup+0x34>
  4751. {
  4752. /* Instruction and address at DQ0, data at DQ0-3. */
  4753. rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
  4754. 18001e6e: 00020537 lui a0,0x20
  4755. 18001e72: 8fc9 or a5,a5,a0
  4756. 18001e74: 0007851b sext.w a0,a5
  4757. addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
  4758. 18001e78: 00164783 lbu a5,1(a2)
  4759. 18001e7c: 00264683 lbu a3,2(a2)
  4760. 18001e80: 00364883 lbu a7,3(a2)
  4761. 18001e84: 0107979b slliw a5,a5,0x10
  4762. 18001e88: 0086969b slliw a3,a3,0x8
  4763. 18001e8c: 8fd5 or a5,a5,a3
  4764. 18001e8e: 0117e7b3 or a5,a5,a7
  4765. if (addr_width == 4)
  4766. 18001e92: 4691 li a3,4
  4767. addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
  4768. 18001e94: 2781 sext.w a5,a5
  4769. if (addr_width == 4)
  4770. 18001e96: 00d59863 bne a1,a3,18001ea6 <cadence_qspi_apb_indirect_read_setup+0x62>
  4771. addr = (addr << 8) | addr_buf[3];
  4772. 18001e9a: 00464683 lbu a3,4(a2)
  4773. 18001e9e: 0087979b slliw a5,a5,0x8
  4774. 18001ea2: 8fd5 or a5,a5,a3
  4775. 18001ea4: 2781 sext.w a5,a5
  4776. {
  4777. rd_reg &= ~(CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB);
  4778. }
  4779. /* Get address */
  4780. addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
  4781. writel(addr_value, (u32)plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
  4782. 18001ea6: 0687069b addiw a3,a4,104
  4783. 18001eaa: 1682 slli a3,a3,0x20
  4784. 18001eac: 9281 srli a3,a3,0x20
  4785. 18001eae: c29c sw a5,0(a3)
  4786. /* The remaining lenght is dummy bytes. */
  4787. dummy_bytes = cmdlen - addr_bytes - 1;
  4788. if (dummy_bytes) {
  4789. 18001eb0: 00080c63 beqz a6,18001ec8 <cadence_qspi_apb_indirect_read_setup+0x84>
  4790. rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
  4791. #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
  4792. writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
  4793. #else
  4794. writel(0xFF, (u32)plat->regbase + CQSPI_REG_MODE_BIT);
  4795. 18001eb4: 0287079b addiw a5,a4,40
  4796. rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
  4797. 18001eb8: 001006b7 lui a3,0x100
  4798. writel(0xFF, (u32)plat->regbase + CQSPI_REG_MODE_BIT);
  4799. 18001ebc: 1782 slli a5,a5,0x20
  4800. rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
  4801. 18001ebe: 8d55 or a0,a0,a3
  4802. writel(0xFF, (u32)plat->regbase + CQSPI_REG_MODE_BIT);
  4803. 18001ec0: 9381 srli a5,a5,0x20
  4804. 18001ec2: 0ff00693 li a3,255
  4805. 18001ec6: c394 sw a3,0(a5)
  4806. if (dummy_clk)
  4807. rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
  4808. << CQSPI_REG_RD_INSTR_DUMMY_LSB;
  4809. }
  4810. writel(rd_reg, (u32)plat->regbase + CQSPI_REG_RD_INSTR);
  4811. 18001ec8: 0047079b addiw a5,a4,4
  4812. 18001ecc: 1782 slli a5,a5,0x20
  4813. 18001ece: 9381 srli a5,a5,0x20
  4814. 18001ed0: c388 sw a0,0(a5)
  4815. //writel(0x0012006b, (u32)plat->regbase + CQSPI_REG_RD_INSTR);
  4816. //writel(0x041220eb, (u32)plat->regbase + CQSPI_REG_RD_INSTR);
  4817. /* set device size */
  4818. reg = readl((u32)plat->regbase + CQSPI_REG_SIZE);
  4819. 18001ed2: 2751 addiw a4,a4,20
  4820. 18001ed4: 1702 slli a4,a4,0x20
  4821. 18001ed6: 9301 srli a4,a4,0x20
  4822. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  4823. 18001ed8: 431c lw a5,0(a4)
  4824. reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
  4825. 18001eda: 9bc1 andi a5,a5,-16
  4826. reg |= (addr_bytes - 1);
  4827. 18001edc: 35fd addiw a1,a1,-1
  4828. reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
  4829. 18001ede: 2781 sext.w a5,a5
  4830. reg |= (addr_bytes - 1);
  4831. 18001ee0: 8fcd or a5,a5,a1
  4832. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  4833. 18001ee2: c31c sw a5,0(a4)
  4834. writel(reg, (u32)plat->regbase + CQSPI_REG_SIZE);
  4835. return 0;
  4836. }
  4837. 18001ee4: 4501 li a0,0
  4838. 18001ee6: 8082 ret
  4839. addr_bytes = cmdlen - 2;
  4840. 18001ee8: 35f9 addiw a1,a1,-2
  4841. 18001eea: 4805 li a6,1
  4842. 18001eec: b78d j 18001e4e <cadence_qspi_apb_indirect_read_setup+0xa>
  4843. 0000000018001eee <cadence_qspi_apb_indirect_read_execute>:
  4844. int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
  4845. unsigned int rxlen, u8 *rxbuf)
  4846. {
  4847. unsigned int reg;
  4848. writel(rxlen, (u32)plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
  4849. 18001eee: 4518 lw a4,8(a0)
  4850. {
  4851. 18001ef0: 7159 addi sp,sp,-112
  4852. 18001ef2: f486 sd ra,104(sp)
  4853. writel(rxlen, (u32)plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
  4854. 18001ef4: 06c7079b addiw a5,a4,108
  4855. 18001ef8: 1782 slli a5,a5,0x20
  4856. {
  4857. 18001efa: f0a2 sd s0,96(sp)
  4858. 18001efc: eca6 sd s1,88(sp)
  4859. 18001efe: e8ca sd s2,80(sp)
  4860. 18001f00: e4ce sd s3,72(sp)
  4861. 18001f02: e0d2 sd s4,64(sp)
  4862. 18001f04: fc56 sd s5,56(sp)
  4863. 18001f06: f85a sd s6,48(sp)
  4864. 18001f08: f45e sd s7,40(sp)
  4865. 18001f0a: f062 sd s8,32(sp)
  4866. 18001f0c: ec66 sd s9,24(sp)
  4867. writel(rxlen, (u32)plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
  4868. 18001f0e: 9381 srli a5,a5,0x20
  4869. 18001f10: c38c sw a1,0(a5)
  4870. /* Start the indirect read transfer */
  4871. writel(CQSPI_REG_INDIRECTRD_START_MASK,
  4872. (u32)plat->regbase + CQSPI_REG_INDIRECTRD);
  4873. 18001f12: 0607079b addiw a5,a4,96
  4874. 18001f16: 1782 slli a5,a5,0x20
  4875. 18001f18: 9381 srli a5,a5,0x20
  4876. 18001f1a: 4685 li a3,1
  4877. 18001f1c: c394 sw a3,0(a5)
  4878. if (qspi_read_sram_fifo_poll(plat->regbase, (void *)rxbuf,
  4879. (const void *)plat->ahbbase, rxlen))
  4880. 18001f1e: 01053983 ld s3,16(a0) # 20010 <__stack_size+0x1f810>
  4881. while (remaining > 0) {
  4882. 18001f22: c5f9 beqz a1,18001ff0 <cadence_qspi_apb_indirect_read_execute+0x102>
  4883. sram_level = CQSPI_GET_RD_SRAM_LEVEL((u32)reg_base);
  4884. 18001f24: 02c7071b addiw a4,a4,44
  4885. 18001f28: 02071413 slli s0,a4,0x20
  4886. 18001f2c: 64c1 lui s1,0x10
  4887. while (retry--) {
  4888. 18001f2e: 6a89 lui s5,0x2
  4889. 18001f30: 8baa mv s7,a0
  4890. 18001f32: 8a2e mv s4,a1
  4891. 18001f34: 8cb2 mv s9,a2
  4892. sram_level = CQSPI_GET_RD_SRAM_LEVEL((u32)reg_base);
  4893. 18001f36: 9001 srli s0,s0,0x20
  4894. 18001f38: 14fd addi s1,s1,-1
  4895. while (retry--) {
  4896. 18001f3a: 70ea8a93 addi s5,s5,1806 # 270e <__stack_size+0x1f0e>
  4897. 18001f3e: 597d li s2,-1
  4898. while (remaining >= 4) {
  4899. 18001f40: 4b0d li s6,3
  4900. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  4901. 18001f42: 401c lw a5,0(s0)
  4902. sram_level = CQSPI_GET_RD_SRAM_LEVEL((u32)reg_base);
  4903. 18001f44: 8fe5 and a5,a5,s1
  4904. 18001f46: 2781 sext.w a5,a5
  4905. if (sram_level)
  4906. 18001f48: e785 bnez a5,18001f70 <cadence_qspi_apb_indirect_read_execute+0x82>
  4907. delay(100);
  4908. 18001f4a: 06400513 li a0,100
  4909. 18001f4e: 312000ef jal ra,18002260 <udelay>
  4910. while (retry--) {
  4911. 18001f52: 8c56 mv s8,s5
  4912. 18001f54: a031 j 18001f60 <cadence_qspi_apb_indirect_read_execute+0x72>
  4913. 18001f56: 3c7d addiw s8,s8,-1
  4914. delay(100);
  4915. 18001f58: 308000ef jal ra,18002260 <udelay>
  4916. while (retry--) {
  4917. 18001f5c: 0b2c0f63 beq s8,s2,1800201a <cadence_qspi_apb_indirect_read_execute+0x12c>
  4918. 18001f60: 401c lw a5,0(s0)
  4919. sram_level = CQSPI_GET_RD_SRAM_LEVEL((u32)reg_base);
  4920. 18001f62: 8fe5 and a5,a5,s1
  4921. 18001f64: 2781 sext.w a5,a5
  4922. delay(100);
  4923. 18001f66: 06400513 li a0,100
  4924. if (sram_level)
  4925. 18001f6a: d7f5 beqz a5,18001f56 <cadence_qspi_apb_indirect_read_execute+0x68>
  4926. if (!retry) {
  4927. 18001f6c: 0a0c0e63 beqz s8,18002028 <cadence_qspi_apb_indirect_read_execute+0x13a>
  4928. sram_level *= CQSPI_FIFO_WIDTH;
  4929. 18001f70: 0027979b slliw a5,a5,0x2
  4930. sram_level = sram_level > remaining ? remaining : sram_level;
  4931. 18001f74: 0007871b sext.w a4,a5
  4932. 18001f78: 00ea7363 bgeu s4,a4,18001f7e <cadence_qspi_apb_indirect_read_execute+0x90>
  4933. 18001f7c: 87d2 mv a5,s4
  4934. dest += sram_level;
  4935. 18001f7e: 02079c13 slli s8,a5,0x20
  4936. 18001f82: 020c5c13 srli s8,s8,0x20
  4937. sram_level = sram_level > remaining ? remaining : sram_level;
  4938. 18001f86: 0007861b sext.w a2,a5
  4939. dest += sram_level;
  4940. 18001f8a: 9c66 add s8,s8,s9
  4941. remaining -= sram_level;
  4942. 18001f8c: 40fa0a3b subw s4,s4,a5
  4943. while (remaining >= 4) {
  4944. 18001f90: 02cb7d63 bgeu s6,a2,18001fca <cadence_qspi_apb_indirect_read_execute+0xdc>
  4945. 18001f94: 37f1 addiw a5,a5,-4
  4946. 18001f96: 0027d79b srliw a5,a5,0x2
  4947. 18001f9a: 0017851b addiw a0,a5,1
  4948. 18001f9e: 050a slli a0,a0,0x2
  4949. 18001fa0: 9566 add a0,a0,s9
  4950. 18001fa2: 0009a703 lw a4,0(s3)
  4951. *dest_ptr = readl(src_ptr);
  4952. 18001fa6: 00eca023 sw a4,0(s9)
  4953. dest_ptr++;
  4954. 18001faa: 0c91 addi s9,s9,4
  4955. while (remaining >= 4) {
  4956. 18001fac: feac9be3 bne s9,a0,18001fa2 <cadence_qspi_apb_indirect_read_execute+0xb4>
  4957. 18001fb0: 3671 addiw a2,a2,-4
  4958. remaining -= 4;
  4959. 18001fb2: 0027979b slliw a5,a5,0x2
  4960. 18001fb6: 9e1d subw a2,a2,a5
  4961. if (remaining) {
  4962. 18001fb8: ea11 bnez a2,18001fcc <cadence_qspi_apb_indirect_read_execute+0xde>
  4963. delay(100);
  4964. 18001fba: 06400513 li a0,100
  4965. 18001fbe: 2a2000ef jal ra,18002260 <udelay>
  4966. while (remaining > 0) {
  4967. 18001fc2: 020a0163 beqz s4,18001fe4 <cadence_qspi_apb_indirect_read_execute+0xf6>
  4968. delay(100);
  4969. 18001fc6: 8ce2 mv s9,s8
  4970. 18001fc8: bfad j 18001f42 <cadence_qspi_apb_indirect_read_execute+0x54>
  4971. while (remaining >= 4) {
  4972. 18001fca: 8566 mv a0,s9
  4973. 18001fcc: 0009a783 lw a5,0(s3)
  4974. sys_memcpy(dest_ptr, &temp, remaining);
  4975. 18001fd0: 006c addi a1,sp,12
  4976. temp = readl(src_ptr);
  4977. 18001fd2: c63e sw a5,12(sp)
  4978. sys_memcpy(dest_ptr, &temp, remaining);
  4979. 18001fd4: a3bfe0ef jal ra,18000a0e <sys_memcpy>
  4980. delay(100);
  4981. 18001fd8: 06400513 li a0,100
  4982. 18001fdc: 284000ef jal ra,18002260 <udelay>
  4983. while (remaining > 0) {
  4984. 18001fe0: fe0a13e3 bnez s4,18001fc6 <cadence_qspi_apb_indirect_read_execute+0xd8>
  4985. goto failrd;
  4986. /* Check flash indirect controller */
  4987. reg = readl((u32)plat->regbase + CQSPI_REG_INDIRECTRD);
  4988. 18001fe4: 008bb783 ld a5,8(s7)
  4989. 18001fe8: 0607879b addiw a5,a5,96
  4990. 18001fec: 1782 slli a5,a5,0x20
  4991. 18001fee: 9381 srli a5,a5,0x20
  4992. 18001ff0: 4398 lw a4,0(a5)
  4993. if (!(reg & CQSPI_REG_INDIRECTRD_DONE_MASK)) {
  4994. 18001ff2: 02077713 andi a4,a4,32
  4995. 18001ff6: cb29 beqz a4,18002048 <cadence_qspi_apb_indirect_read_execute+0x15a>
  4996. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  4997. 18001ff8: 02000713 li a4,32
  4998. 18001ffc: c398 sw a4,0(a5)
  4999. }
  5000. /* Clear indirect completion status */
  5001. writel(CQSPI_REG_INDIRECTRD_DONE_MASK,
  5002. (u32)plat->regbase + CQSPI_REG_INDIRECTRD);
  5003. return 0;
  5004. 18001ffe: 4501 li a0,0
  5005. failrd:
  5006. /* Cancel the indirect read */
  5007. writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK,
  5008. (u32)plat->regbase + CQSPI_REG_INDIRECTRD);
  5009. return -1;
  5010. }
  5011. 18002000: 70a6 ld ra,104(sp)
  5012. 18002002: 7406 ld s0,96(sp)
  5013. 18002004: 64e6 ld s1,88(sp)
  5014. 18002006: 6946 ld s2,80(sp)
  5015. 18002008: 69a6 ld s3,72(sp)
  5016. 1800200a: 6a06 ld s4,64(sp)
  5017. 1800200c: 7ae2 ld s5,56(sp)
  5018. 1800200e: 7b42 ld s6,48(sp)
  5019. 18002010: 7ba2 ld s7,40(sp)
  5020. 18002012: 7c02 ld s8,32(sp)
  5021. 18002014: 6ce2 ld s9,24(sp)
  5022. 18002016: 6165 addi sp,sp,112
  5023. 18002018: 8082 ret
  5024. delay(100);
  5025. 1800201a: 06400513 li a0,100
  5026. 1800201e: 8c66 mv s8,s9
  5027. 18002020: 240000ef jal ra,18002260 <udelay>
  5028. 18002024: 8ce2 mv s9,s8
  5029. 18002026: bf31 j 18001f42 <cadence_qspi_apb_indirect_read_execute+0x54>
  5030. printk("fifo_poll timeout.\n");
  5031. 18002028: 00000517 auipc a0,0x0
  5032. 1800202c: 4a050513 addi a0,a0,1184 # 180024c8 <spi_flash_table+0x30>
  5033. 18002030: 9bbfe0ef jal ra,180009ea <printk>
  5034. (u32)plat->regbase + CQSPI_REG_INDIRECTRD);
  5035. 18002034: 008bb783 ld a5,8(s7)
  5036. 18002038: 0607879b addiw a5,a5,96
  5037. 1800203c: 1782 slli a5,a5,0x20
  5038. 1800203e: 9381 srli a5,a5,0x20
  5039. 18002040: 4709 li a4,2
  5040. 18002042: c398 sw a4,0(a5)
  5041. return -1;
  5042. 18002044: 557d li a0,-1
  5043. 18002046: bf6d j 18002000 <cadence_qspi_apb_indirect_read_execute+0x112>
  5044. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  5045. 18002048: 4398 lw a4,0(a5)
  5046. goto failrd;
  5047. 1800204a: bfdd j 18002040 <cadence_qspi_apb_indirect_read_execute+0x152>
  5048. 000000001800204c <cadence_qspi_apb_indirect_write_setup>:
  5049. /* Opcode + Address (3/4 bytes) */
  5050. int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
  5051. unsigned int cmdlen, const u8 *cmdbuf)
  5052. {
  5053. unsigned int reg;
  5054. unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
  5055. 1800204c: 4791 li a5,4
  5056. 1800204e: 08b7e663 bltu a5,a1,180020da <cadence_qspi_apb_indirect_write_setup+0x8e>
  5057. if (cmdlen < 4 || cmdbuf == NULL) {
  5058. 18002052: 08f59663 bne a1,a5,180020de <cadence_qspi_apb_indirect_write_setup+0x92>
  5059. unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
  5060. 18002056: 468d li a3,3
  5061. if (cmdlen < 4 || cmdbuf == NULL) {
  5062. 18002058: c259 beqz a2,180020de <cadence_qspi_apb_indirect_write_setup+0x92>
  5063. //cmdlen, (unsigned int)cmdbuf);
  5064. return -1;
  5065. }
  5066. /* Setup the indirect trigger address */
  5067. writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
  5068. (u32)plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
  5069. 1800205a: 4518 lw a4,8(a0)
  5070. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  5071. 1800205c: 4581 li a1,0
  5072. 1800205e: 01c7079b addiw a5,a4,28
  5073. 18002062: 1782 slli a5,a5,0x20
  5074. 18002064: 9381 srli a5,a5,0x20
  5075. 18002066: c38c sw a1,0(a5)
  5076. /* Configure the opcode */
  5077. reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
  5078. 18002068: 00064783 lbu a5,0(a2)
  5079. if(plat->bit_mode == 4)
  5080. 1800206c: 03852803 lw a6,56(a0)
  5081. 18002070: 4511 li a0,4
  5082. reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
  5083. 18002072: 0007859b sext.w a1,a5
  5084. if(plat->bit_mode == 4)
  5085. 18002076: 00a81763 bne a6,a0,18002084 <cadence_qspi_apb_indirect_write_setup+0x38>
  5086. {
  5087. /* Instruction and address at DQ0, data at DQ0-3. */
  5088. reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;
  5089. 1800207a: 000205b7 lui a1,0x20
  5090. 1800207e: 8fcd or a5,a5,a1
  5091. 18002080: 0007859b sext.w a1,a5
  5092. }
  5093. else
  5094. {
  5095. reg &= ~(CQSPI_INST_TYPE_QUAD << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB);
  5096. }
  5097. writel(reg, (u32)plat->regbase + CQSPI_REG_WR_INSTR);
  5098. 18002084: 0087079b addiw a5,a4,8
  5099. 18002088: 1782 slli a5,a5,0x20
  5100. 1800208a: 9381 srli a5,a5,0x20
  5101. 1800208c: c38c sw a1,0(a5)
  5102. addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
  5103. 1800208e: 00164783 lbu a5,1(a2)
  5104. 18002092: 00264583 lbu a1,2(a2)
  5105. 18002096: 00364503 lbu a0,3(a2)
  5106. 1800209a: 0107979b slliw a5,a5,0x10
  5107. 1800209e: 0085959b slliw a1,a1,0x8
  5108. 180020a2: 8fcd or a5,a5,a1
  5109. 180020a4: 8fc9 or a5,a5,a0
  5110. if (addr_width == 4)
  5111. 180020a6: 4591 li a1,4
  5112. addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
  5113. 180020a8: 2781 sext.w a5,a5
  5114. if (addr_width == 4)
  5115. 180020aa: 00b69863 bne a3,a1,180020ba <cadence_qspi_apb_indirect_write_setup+0x6e>
  5116. addr = (addr << 8) | addr_buf[3];
  5117. 180020ae: 00464603 lbu a2,4(a2)
  5118. 180020b2: 0087979b slliw a5,a5,0x8
  5119. 180020b6: 8fd1 or a5,a5,a2
  5120. 180020b8: 2781 sext.w a5,a5
  5121. //writel(0x00020032, (u32)plat->regbase + CQSPI_REG_WR_INSTR);
  5122. /* Setup write address. */
  5123. reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
  5124. writel(reg, (u32)plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
  5125. 180020ba: 0787061b addiw a2,a4,120
  5126. 180020be: 1602 slli a2,a2,0x20
  5127. 180020c0: 9201 srli a2,a2,0x20
  5128. 180020c2: c21c sw a5,0(a2)
  5129. reg = readl((u32)plat->regbase + CQSPI_REG_SIZE);
  5130. 180020c4: 2751 addiw a4,a4,20
  5131. 180020c6: 1702 slli a4,a4,0x20
  5132. 180020c8: 9301 srli a4,a4,0x20
  5133. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  5134. 180020ca: 431c lw a5,0(a4)
  5135. reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
  5136. 180020cc: 9bc1 andi a5,a5,-16
  5137. reg |= (addr_bytes - 1);
  5138. 180020ce: 36fd addiw a3,a3,-1
  5139. reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
  5140. 180020d0: 2781 sext.w a5,a5
  5141. reg |= (addr_bytes - 1);
  5142. 180020d2: 8fd5 or a5,a5,a3
  5143. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  5144. 180020d4: c31c sw a5,0(a4)
  5145. writel(reg, (u32)plat->regbase + CQSPI_REG_SIZE);
  5146. return 0;
  5147. 180020d6: 4501 li a0,0
  5148. 180020d8: 8082 ret
  5149. unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
  5150. 180020da: 4691 li a3,4
  5151. 180020dc: bfb5 j 18002058 <cadence_qspi_apb_indirect_write_setup+0xc>
  5152. return -1;
  5153. 180020de: 557d li a0,-1
  5154. }
  5155. 180020e0: 8082 ret
  5156. 00000000180020e2 <cadence_qspi_apb_indirect_write_execute>:
  5157. {
  5158. unsigned int reg = 0;
  5159. unsigned int retry;
  5160. /* Configure the indirect read transfer bytes */
  5161. writel(txlen, (u32)plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
  5162. 180020e2: 651c ld a5,8(a0)
  5163. {
  5164. 180020e4: 7119 addi sp,sp,-128
  5165. 180020e6: ecce sd s3,88(sp)
  5166. writel(txlen, (u32)plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
  5167. 180020e8: 07c7869b addiw a3,a5,124
  5168. 180020ec: 1682 slli a3,a3,0x20
  5169. {
  5170. 180020ee: e0da sd s6,64(sp)
  5171. 180020f0: fc86 sd ra,120(sp)
  5172. 180020f2: f8a2 sd s0,112(sp)
  5173. 180020f4: f4a6 sd s1,104(sp)
  5174. 180020f6: f0ca sd s2,96(sp)
  5175. 180020f8: e8d2 sd s4,80(sp)
  5176. 180020fa: e4d6 sd s5,72(sp)
  5177. 180020fc: fc5e sd s7,56(sp)
  5178. 180020fe: f862 sd s8,48(sp)
  5179. 18002100: f466 sd s9,40(sp)
  5180. 18002102: f06a sd s10,32(sp)
  5181. 18002104: ec6e sd s11,24(sp)
  5182. 18002106: 89aa mv s3,a0
  5183. 18002108: 8b32 mv s6,a2
  5184. writel(txlen, (u32)plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
  5185. 1800210a: 0007871b sext.w a4,a5
  5186. 1800210e: 9281 srli a3,a3,0x20
  5187. 18002110: c28c sw a1,0(a3)
  5188. /* Start the indirect write transfer */
  5189. writel(CQSPI_REG_INDIRECTWR_START_MASK,
  5190. (u32)plat->regbase + CQSPI_REG_INDIRECTWR);
  5191. 18002112: 0707069b addiw a3,a4,112
  5192. 18002116: 1682 slli a3,a3,0x20
  5193. 18002118: 9281 srli a3,a3,0x20
  5194. 1800211a: 4605 li a2,1
  5195. 1800211c: c290 sw a2,0(a3)
  5196. void *dest_addr = plat->ahbbase;
  5197. 1800211e: 01053a83 ld s5,16(a0)
  5198. unsigned int page_size = plat->page_size;
  5199. 18002122: 01c52c03 lw s8,28(a0)
  5200. while (remaining > 0) {
  5201. 18002126: 08b05663 blez a1,180021b2 <cadence_qspi_apb_indirect_write_execute+0xd0>
  5202. 1800212a: 02c7071b addiw a4,a4,44
  5203. 1800212e: 02071413 slli s0,a4,0x20
  5204. while (retry--) {
  5205. 18002132: 6b89 lui s7,0x2
  5206. 18002134: 0005869b sext.w a3,a1
  5207. 18002138: 9001 srli s0,s0,0x20
  5208. 1800213a: 70fb8b93 addi s7,s7,1807 # 270f <__stack_size+0x1f0f>
  5209. if (sram_level <= sram_threshold_words)
  5210. 1800213e: 03200493 li s1,50
  5211. while (retry--) {
  5212. 18002142: 597d li s2,-1
  5213. wr_bytes = (remaining > page_size) ?
  5214. 18002144: 8d62 mv s10,s8
  5215. while (remaining >= CQSPI_FIFO_WIDTH) {
  5216. 18002146: 4c8d li s9,3
  5217. while (retry--) {
  5218. 18002148: 875e mv a4,s7
  5219. 1800214a: a021 j 18002152 <cadence_qspi_apb_indirect_write_execute+0x70>
  5220. 1800214c: 377d addiw a4,a4,-1
  5221. 1800214e: 01270863 beq a4,s2,1800215e <cadence_qspi_apb_indirect_write_execute+0x7c>
  5222. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  5223. 18002152: 401c lw a5,0(s0)
  5224. if (sram_level <= sram_threshold_words)
  5225. 18002154: 0107d79b srliw a5,a5,0x10
  5226. 18002158: fef4eae3 bltu s1,a5,1800214c <cadence_qspi_apb_indirect_write_execute+0x6a>
  5227. if (!retry) {
  5228. 1800215c: c369 beqz a4,1800221e <cadence_qspi_apb_indirect_write_execute+0x13c>
  5229. page_size : remaining;
  5230. 1800215e: 00068d9b sext.w s11,a3
  5231. wr_bytes = (remaining > page_size) ?
  5232. 18002162: 87ea mv a5,s10
  5233. 18002164: 0186f363 bgeu a3,s8,1800216a <cadence_qspi_apb_indirect_write_execute+0x88>
  5234. 18002168: 87ee mv a5,s11
  5235. 1800216a: 00078a1b sext.w s4,a5
  5236. unsigned int temp = 0;
  5237. 1800216e: c602 sw zero,12(sp)
  5238. int remaining = bytes;
  5239. 18002170: 8652 mv a2,s4
  5240. while (remaining >= CQSPI_FIFO_WIDTH) {
  5241. 18002172: 0b4cf463 bgeu s9,s4,1800221a <cadence_qspi_apb_indirect_write_execute+0x138>
  5242. 18002176: 37f1 addiw a5,a5,-4
  5243. 18002178: 0027d51b srliw a0,a5,0x2
  5244. 1800217c: 0015059b addiw a1,a0,1
  5245. 18002180: 058a slli a1,a1,0x2
  5246. 18002182: 95da add a1,a1,s6
  5247. 18002184: 87da mv a5,s6
  5248. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  5249. 18002186: 4398 lw a4,0(a5)
  5250. 18002188: 00eaa023 sw a4,0(s5)
  5251. src_ptr += CQSPI_FIFO_WIDTH/4;
  5252. 1800218c: 0791 addi a5,a5,4
  5253. while (remaining >= CQSPI_FIFO_WIDTH) {
  5254. 1800218e: feb79ce3 bne a5,a1,18002186 <cadence_qspi_apb_indirect_write_execute+0xa4>
  5255. 18002192: ffca061b addiw a2,s4,-4
  5256. remaining -= CQSPI_FIFO_WIDTH;
  5257. 18002196: 0025151b slliw a0,a0,0x2
  5258. 1800219a: 9e09 subw a2,a2,a0
  5259. if (remaining) {
  5260. 1800219c: ea25 bnez a2,1800220c <cadence_qspi_apb_indirect_write_execute+0x12a>
  5261. src += wr_bytes;
  5262. 1800219e: 020a1793 slli a5,s4,0x20
  5263. 180021a2: 9381 srli a5,a5,0x20
  5264. remaining -= wr_bytes;
  5265. 180021a4: 414d86bb subw a3,s11,s4
  5266. src += wr_bytes;
  5267. 180021a8: 9b3e add s6,s6,a5
  5268. while (remaining > 0) {
  5269. 180021aa: f8d04fe3 bgtz a3,18002148 <cadence_qspi_apb_indirect_write_execute+0x66>
  5270. goto failwr;
  5271. #if 1
  5272. /* Wait until last write is completed (FIFO empty) */
  5273. retry = CQSPI_REG_RETRY;
  5274. while (retry--) {
  5275. reg = CQSPI_GET_WR_SRAM_LEVEL((u32)plat->regbase);
  5276. 180021ae: 0089b783 ld a5,8(s3)
  5277. while (remaining >= CQSPI_FIFO_WIDTH) {
  5278. 180021b2: 6409 lui s0,0x2
  5279. 180021b4: 71040413 addi s0,s0,1808 # 2710 <__stack_size+0x1f10>
  5280. 180021b8: a031 j 180021c4 <cadence_qspi_apb_indirect_write_execute+0xe2>
  5281. if (reg == 0)
  5282. break;
  5283. delay(1000);
  5284. 180021ba: 0a6000ef jal ra,18002260 <udelay>
  5285. while (retry--) {
  5286. 180021be: c025 beqz s0,1800221e <cadence_qspi_apb_indirect_write_execute+0x13c>
  5287. reg = CQSPI_GET_WR_SRAM_LEVEL((u32)plat->regbase);
  5288. 180021c0: 0089b783 ld a5,8(s3)
  5289. 180021c4: 02c7871b addiw a4,a5,44
  5290. 180021c8: 1702 slli a4,a4,0x20
  5291. 180021ca: 9301 srli a4,a4,0x20
  5292. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  5293. 180021cc: 4318 lw a4,0(a4)
  5294. if (reg == 0)
  5295. 180021ce: 0107571b srliw a4,a4,0x10
  5296. delay(1000);
  5297. 180021d2: 3e800513 li a0,1000
  5298. while (retry--) {
  5299. 180021d6: 347d addiw s0,s0,-1
  5300. if (reg == 0)
  5301. 180021d8: f36d bnez a4,180021ba <cadence_qspi_apb_indirect_write_execute+0xd8>
  5302. 180021da: 6409 lui s0,0x2
  5303. 180021dc: 71040413 addi s0,s0,1808 # 2710 <__stack_size+0x1f10>
  5304. 180021e0: a031 j 180021ec <cadence_qspi_apb_indirect_write_execute+0x10a>
  5305. retry = CQSPI_REG_RETRY;
  5306. while (retry--) {
  5307. reg = readl((u32)plat->regbase + CQSPI_REG_INDIRECTWR);
  5308. if (reg & CQSPI_REG_INDIRECTWR_DONE_MASK)
  5309. break;
  5310. delay(1000);
  5311. 180021e2: 07e000ef jal ra,18002260 <udelay>
  5312. while (retry--) {
  5313. 180021e6: cc05 beqz s0,1800221e <cadence_qspi_apb_indirect_write_execute+0x13c>
  5314. reg = readl((u32)plat->regbase + CQSPI_REG_INDIRECTWR);
  5315. 180021e8: 0089b783 ld a5,8(s3)
  5316. 180021ec: 0707879b addiw a5,a5,112
  5317. 180021f0: 1782 slli a5,a5,0x20
  5318. 180021f2: 9381 srli a5,a5,0x20
  5319. 180021f4: 4398 lw a4,0(a5)
  5320. if (reg & CQSPI_REG_INDIRECTWR_DONE_MASK)
  5321. 180021f6: 02077713 andi a4,a4,32
  5322. delay(1000);
  5323. 180021fa: 3e800513 li a0,1000
  5324. while (retry--) {
  5325. 180021fe: 347d addiw s0,s0,-1
  5326. if (reg & CQSPI_REG_INDIRECTWR_DONE_MASK)
  5327. 18002200: d36d beqz a4,180021e2 <cadence_qspi_apb_indirect_write_execute+0x100>
  5328. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  5329. 18002202: 02000713 li a4,32
  5330. 18002206: c398 sw a4,0(a5)
  5331. /* Clear indirect completion status */
  5332. writel(CQSPI_REG_INDIRECTWR_DONE_MASK,
  5333. (u32)plat->regbase + CQSPI_REG_INDIRECTWR);
  5334. #endif
  5335. return 0;
  5336. 18002208: 4501 li a0,0
  5337. 1800220a: a01d j 18002230 <cadence_qspi_apb_indirect_write_execute+0x14e>
  5338. sys_memcpy(&temp, src_ptr+i, remaining % 4);
  5339. 1800220c: 0068 addi a0,sp,12
  5340. 1800220e: 801fe0ef jal ra,18000a0e <sys_memcpy>
  5341. 18002212: 47b2 lw a5,12(sp)
  5342. 18002214: 00faa023 sw a5,0(s5)
  5343. for (--i; i >= 0; i--)
  5344. 18002218: b759 j 1800219e <cadence_qspi_apb_indirect_write_execute+0xbc>
  5345. while (remaining >= CQSPI_FIFO_WIDTH) {
  5346. 1800221a: 85da mv a1,s6
  5347. 1800221c: b741 j 1800219c <cadence_qspi_apb_indirect_write_execute+0xba>
  5348. failwr:
  5349. /* Cancel the indirect write */
  5350. writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
  5351. (u32)plat->regbase + CQSPI_REG_INDIRECTWR);
  5352. 1800221e: 0089b783 ld a5,8(s3)
  5353. 18002222: 4709 li a4,2
  5354. 18002224: 0707879b addiw a5,a5,112
  5355. 18002228: 1782 slli a5,a5,0x20
  5356. 1800222a: 9381 srli a5,a5,0x20
  5357. 1800222c: c398 sw a4,0(a5)
  5358. return -1;
  5359. 1800222e: 557d li a0,-1
  5360. }
  5361. 18002230: 70e6 ld ra,120(sp)
  5362. 18002232: 7446 ld s0,112(sp)
  5363. 18002234: 74a6 ld s1,104(sp)
  5364. 18002236: 7906 ld s2,96(sp)
  5365. 18002238: 69e6 ld s3,88(sp)
  5366. 1800223a: 6a46 ld s4,80(sp)
  5367. 1800223c: 6aa6 ld s5,72(sp)
  5368. 1800223e: 6b06 ld s6,64(sp)
  5369. 18002240: 7be2 ld s7,56(sp)
  5370. 18002242: 7c42 ld s8,48(sp)
  5371. 18002244: 7ca2 ld s9,40(sp)
  5372. 18002246: 7d02 ld s10,32(sp)
  5373. 18002248: 6de2 ld s11,24(sp)
  5374. 1800224a: 6109 addi sp,sp,128
  5375. 1800224c: 8082 ret
  5376. 000000001800224e <usec_to_tick>:
  5377. #define TIMER_CLK_HZ 25000000
  5378. u64 usec_to_tick(u32 usec)
  5379. {
  5380. u64 value;
  5381. value = usec*(TIMER_CLK_HZ/1000000);
  5382. 1800224e: 0015179b slliw a5,a0,0x1
  5383. 18002252: 9fa9 addw a5,a5,a0
  5384. 18002254: 0037979b slliw a5,a5,0x3
  5385. 18002258: 9d3d addw a0,a0,a5
  5386. return value;
  5387. }
  5388. 1800225a: 1502 slli a0,a0,0x20
  5389. 1800225c: 9101 srli a0,a0,0x20
  5390. 1800225e: 8082 ret
  5391. 0000000018002260 <udelay>:
  5392. asm volatile("ld %0, 0(%1)" : "=r" (val) : "r" (addr));
  5393. 18002260: 0200c6b7 lui a3,0x200c
  5394. 18002264: 16e1 addi a3,a3,-8
  5395. 18002266: 6298 ld a4,0(a3)
  5396. value = usec*(TIMER_CLK_HZ/1000000);
  5397. 18002268: 0015179b slliw a5,a0,0x1
  5398. 1800226c: 9fa9 addw a5,a5,a0
  5399. 1800226e: 0037979b slliw a5,a5,0x3
  5400. 18002272: 9fa9 addw a5,a5,a0
  5401. 18002274: 1782 slli a5,a5,0x20
  5402. 18002276: 9381 srli a5,a5,0x20
  5403. /* delay x useconds */
  5404. void udelay(unsigned long usec)
  5405. {
  5406. unsigned long tmp;
  5407. tmp = readq((volatile void *)CLINT_CTRL_MTIME) + usec_to_tick(usec); /* get current timestamp */
  5408. 18002278: 97ba add a5,a5,a4
  5409. 1800227a: 6298 ld a4,0(a3)
  5410. while (readq((volatile void *)CLINT_CTRL_MTIME) < tmp);
  5411. 1800227c: fef76fe3 bltu a4,a5,1800227a <udelay+0x1a>
  5412. }
  5413. 18002280: 8082 ret
  5414. 0000000018002282 <memset>:
  5415. 18002282: 433d li t1,15
  5416. 18002284: 872a mv a4,a0
  5417. 18002286: 02c37163 bgeu t1,a2,180022a8 <memset+0x26>
  5418. 1800228a: 00f77793 andi a5,a4,15
  5419. 1800228e: e3c1 bnez a5,1800230e <memset+0x8c>
  5420. 18002290: e1bd bnez a1,180022f6 <memset+0x74>
  5421. 18002292: ff067693 andi a3,a2,-16
  5422. 18002296: 8a3d andi a2,a2,15
  5423. 18002298: 96ba add a3,a3,a4
  5424. 1800229a: e30c sd a1,0(a4)
  5425. 1800229c: e70c sd a1,8(a4)
  5426. 1800229e: 0741 addi a4,a4,16
  5427. 180022a0: fed76de3 bltu a4,a3,1800229a <memset+0x18>
  5428. 180022a4: e211 bnez a2,180022a8 <memset+0x26>
  5429. 180022a6: 8082 ret
  5430. 180022a8: 40c306b3 sub a3,t1,a2
  5431. 180022ac: 068a slli a3,a3,0x2
  5432. 180022ae: 00000297 auipc t0,0x0
  5433. 180022b2: 9696 add a3,a3,t0
  5434. 180022b4: 00a68067 jr 10(a3) # 200c00a <__stack_size+0x200b80a>
  5435. 180022b8: 00b70723 sb a1,14(a4) # 70000e <__stack_size+0x6ff80e>
  5436. 180022bc: 00b706a3 sb a1,13(a4)
  5437. 180022c0: 00b70623 sb a1,12(a4)
  5438. 180022c4: 00b705a3 sb a1,11(a4)
  5439. 180022c8: 00b70523 sb a1,10(a4)
  5440. 180022cc: 00b704a3 sb a1,9(a4)
  5441. 180022d0: 00b70423 sb a1,8(a4)
  5442. 180022d4: 00b703a3 sb a1,7(a4)
  5443. 180022d8: 00b70323 sb a1,6(a4)
  5444. 180022dc: 00b702a3 sb a1,5(a4)
  5445. 180022e0: 00b70223 sb a1,4(a4)
  5446. 180022e4: 00b701a3 sb a1,3(a4)
  5447. 180022e8: 00b70123 sb a1,2(a4)
  5448. 180022ec: 00b700a3 sb a1,1(a4)
  5449. 180022f0: 00b70023 sb a1,0(a4)
  5450. 180022f4: 8082 ret
  5451. 180022f6: 0ff5f593 zext.b a1,a1
  5452. 180022fa: 00859693 slli a3,a1,0x8
  5453. 180022fe: 8dd5 or a1,a1,a3
  5454. 18002300: 01059693 slli a3,a1,0x10
  5455. 18002304: 8dd5 or a1,a1,a3
  5456. 18002306: 02059693 slli a3,a1,0x20
  5457. 1800230a: 8dd5 or a1,a1,a3
  5458. 1800230c: b759 j 18002292 <memset+0x10>
  5459. 1800230e: 00279693 slli a3,a5,0x2
  5460. 18002312: 00000297 auipc t0,0x0
  5461. 18002316: 9696 add a3,a3,t0
  5462. 18002318: 8286 mv t0,ra
  5463. 1800231a: fa2680e7 jalr -94(a3)
  5464. 1800231e: 8096 mv ra,t0
  5465. 18002320: 17c1 addi a5,a5,-16
  5466. 18002322: 8f1d sub a4,a4,a5
  5467. 18002324: 963e add a2,a2,a5
  5468. 18002326: f8c371e3 bgeu t1,a2,180022a8 <memset+0x26>
  5469. 1800232a: b79d j 18002290 <memset+0xe>