mmc.h 19 KB

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  1. /*
  2. * Copyright 2008,2010 Freescale Semiconductor, Inc
  3. * Andy Fleming
  4. *
  5. * Based (loosely) on the Linux code
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #ifndef _MMC_H_
  10. #define _MMC_H_
  11. /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
  12. #define SD_VERSION_SD (1U << 31)
  13. #define MMC_VERSION_MMC (1U << 30)
  14. #define MAKE_SDMMC_VERSION(a, b, c) \
  15. ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
  16. #define MAKE_SD_VERSION(a, b, c) \
  17. (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
  18. #define MAKE_MMC_VERSION(a, b, c) \
  19. (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
  20. #define EXTRACT_SDMMC_MAJOR_VERSION(x) \
  21. (((u32)(x) >> 16) & 0xff)
  22. #define EXTRACT_SDMMC_MINOR_VERSION(x) \
  23. (((u32)(x) >> 8) & 0xff)
  24. #define EXTRACT_SDMMC_CHANGE_VERSION(x) \
  25. ((u32)(x) & 0xff)
  26. #define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0)
  27. #define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0)
  28. #define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0)
  29. #define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0)
  30. #define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0)
  31. #define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0)
  32. #define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0)
  33. #define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0)
  34. #define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0)
  35. #define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0)
  36. #define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0)
  37. #define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0)
  38. #define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0)
  39. #define MMC_VERSION_4_4 MAKE_MMC_VERSION(4, 4, 0)
  40. #define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1)
  41. #define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0)
  42. #define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0)
  43. #define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0)
  44. #define MMC_CAP(mode) (1 << mode)
  45. #define MMC_MODE_HS (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))
  46. #define MMC_MODE_HS_52MHz MMC_CAP(MMC_HS_52)
  47. #define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52)
  48. #define MMC_MODE_HS200 MMC_CAP(MMC_HS_200)
  49. #define MMC_MODE_8BIT BIT(30)
  50. #define MMC_MODE_4BIT BIT(29)
  51. #define MMC_MODE_1BIT BIT(28)
  52. #define MMC_MODE_SPI BIT(27)
  53. #define SD_DATA_4BIT 0x00040000
  54. #define IS_SD(x) ((x)->version & SD_VERSION_SD)
  55. #define IS_MMC(x) ((x)->version & MMC_VERSION_MMC)
  56. #define MMC_DATA_READ 1
  57. #define MMC_DATA_WRITE 2
  58. #define MMC_CMD_GO_IDLE_STATE 0
  59. #define MMC_CMD_SEND_OP_COND 1
  60. #define MMC_CMD_ALL_SEND_CID 2
  61. #define MMC_CMD_SET_RELATIVE_ADDR 3
  62. #define MMC_CMD_SET_DSR 4
  63. #define MMC_CMD_SWITCH 6
  64. #define MMC_CMD_SELECT_CARD 7
  65. #define MMC_CMD_SEND_EXT_CSD 8
  66. #define MMC_CMD_SEND_CSD 9
  67. #define MMC_CMD_SEND_CID 10
  68. #define MMC_CMD_STOP_TRANSMISSION 12
  69. #define MMC_CMD_SEND_STATUS 13
  70. #define MMC_CMD_SET_BLOCKLEN 16
  71. #define MMC_CMD_READ_SINGLE_BLOCK 17
  72. #define MMC_CMD_READ_MULTIPLE_BLOCK 18
  73. #define MMC_CMD_SEND_TUNING_BLOCK 19
  74. #define MMC_CMD_SEND_TUNING_BLOCK_HS200 21
  75. #define MMC_CMD_SET_BLOCK_COUNT 23
  76. #define MMC_CMD_WRITE_SINGLE_BLOCK 24
  77. #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
  78. #define MMC_CMD_ERASE_GROUP_START 35
  79. #define MMC_CMD_ERASE_GROUP_END 36
  80. #define MMC_CMD_ERASE 38
  81. #define MMC_CMD_APP_CMD 55
  82. #define MMC_CMD_SPI_READ_OCR 58
  83. #define MMC_CMD_SPI_CRC_ON_OFF 59
  84. #define MMC_CMD_RES_MAN 62
  85. #define MMC_CMD62_ARG1 0xefac62ec
  86. #define MMC_CMD62_ARG2 0xcbaea7
  87. #define SD_CMD_SEND_RELATIVE_ADDR 3
  88. #define SD_CMD_SWITCH_FUNC 6
  89. #define SD_CMD_SEND_IF_COND 8
  90. #define SD_CMD_SWITCH_UHS18V 11
  91. #define SD_CMD_APP_SET_BUS_WIDTH 6
  92. #define SD_CMD_APP_SD_STATUS 13
  93. #define SD_CMD_ERASE_WR_BLK_START 32
  94. #define SD_CMD_ERASE_WR_BLK_END 33
  95. #define SD_CMD_APP_SEND_OP_COND 41
  96. #define SD_CMD_APP_SEND_SCR 51
  97. static inline bool mmc_is_tuning_cmd(u32 cmdidx)
  98. {
  99. if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) ||
  100. (cmdidx == MMC_CMD_SEND_TUNING_BLOCK))
  101. return true;
  102. return false;
  103. }
  104. /* SCR definitions in different words */
  105. #define SD_HIGHSPEED_BUSY 0x00020000
  106. #define SD_HIGHSPEED_SUPPORTED 0x00020000
  107. #define UHS_SDR12_BUS_SPEED 0
  108. #define HIGH_SPEED_BUS_SPEED 1
  109. #define UHS_SDR25_BUS_SPEED 1
  110. #define UHS_SDR50_BUS_SPEED 2
  111. #define UHS_SDR104_BUS_SPEED 3
  112. #define UHS_DDR50_BUS_SPEED 4
  113. #define SD_MODE_UHS_SDR12 BIT(UHS_SDR12_BUS_SPEED)
  114. #define SD_MODE_UHS_SDR25 BIT(UHS_SDR25_BUS_SPEED)
  115. #define SD_MODE_UHS_SDR50 BIT(UHS_SDR50_BUS_SPEED)
  116. #define SD_MODE_UHS_SDR104 BIT(UHS_SDR104_BUS_SPEED)
  117. #define SD_MODE_UHS_DDR50 BIT(UHS_DDR50_BUS_SPEED)
  118. #define OCR_BUSY 0x80000000
  119. #define OCR_HCS 0x40000000
  120. #define OCR_S18R 0x1000000
  121. #define OCR_VOLTAGE_MASK 0x007FFF80
  122. #define OCR_ACCESS_MODE 0x60000000
  123. #define MMC_ERASE_ARG 0x00000000
  124. #define MMC_SECURE_ERASE_ARG 0x80000000
  125. #define MMC_TRIM_ARG 0x00000001
  126. #define MMC_DISCARD_ARG 0x00000003
  127. #define MMC_SECURE_TRIM1_ARG 0x80000001
  128. #define MMC_SECURE_TRIM2_ARG 0x80008000
  129. #define MMC_STATUS_MASK (~0x0206BF7F)
  130. #define MMC_STATUS_SWITCH_ERROR (1 << 7)
  131. #define MMC_STATUS_RDY_FOR_DATA (1 << 8)
  132. #define MMC_STATUS_CURR_STATE (0xf << 9)
  133. #define MMC_STATUS_ERROR (1 << 19)
  134. #define MMC_STATE_PRG (7 << 9)
  135. #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
  136. #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
  137. #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
  138. #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
  139. #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
  140. #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
  141. #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
  142. #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
  143. #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
  144. #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
  145. #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
  146. #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
  147. #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
  148. #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
  149. #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
  150. #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
  151. #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
  152. #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
  153. #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
  154. addressed by index which are
  155. 1 in value field */
  156. #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
  157. addressed by index, which are
  158. 1 in value field */
  159. #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
  160. #define SD_SWITCH_CHECK 0
  161. #define SD_SWITCH_SWITCH 1
  162. /*
  163. * EXT_CSD fields
  164. */
  165. #define EXT_CSD_ENH_START_ADDR 136 /* R/W */
  166. #define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */
  167. #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
  168. #define EXT_CSD_PARTITION_SETTING 155 /* R/W */
  169. #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
  170. #define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */
  171. #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
  172. #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
  173. #define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */
  174. #define EXT_CSD_WR_REL_PARAM 166 /* R */
  175. #define EXT_CSD_WR_REL_SET 167 /* R/W */
  176. #define EXT_CSD_RPMB_MULT 168 /* RO */
  177. #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
  178. #define EXT_CSD_BOOT_BUS_WIDTH 177
  179. #define EXT_CSD_PART_CONF 179 /* R/W */
  180. #define EXT_CSD_BUS_WIDTH 183 /* R/W */
  181. #define EXT_CSD_HS_TIMING 185 /* R/W */
  182. #define EXT_CSD_REV 192 /* RO */
  183. #define EXT_CSD_CARD_TYPE 196 /* RO */
  184. #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
  185. #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
  186. #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
  187. #define EXT_CSD_BOOT_MULT 226 /* RO */
  188. #define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
  189. /*
  190. * EXT_CSD field definitions
  191. */
  192. #define EXT_CSD_CMD_SET_NORMAL (1 << 0)
  193. #define EXT_CSD_CMD_SET_SECURE (1 << 1)
  194. #define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
  195. #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
  196. #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
  197. #define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
  198. #define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
  199. #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
  200. | EXT_CSD_CARD_TYPE_DDR_1_2V)
  201. #define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */
  202. /* SDR mode @1.8V I/O */
  203. #define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */
  204. /* SDR mode @1.2V I/O */
  205. #define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
  206. EXT_CSD_CARD_TYPE_HS200_1_2V)
  207. #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
  208. #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
  209. #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
  210. #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
  211. #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
  212. #define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */
  213. #define EXT_CSD_TIMING_LEGACY 0 /* no high speed */
  214. #define EXT_CSD_TIMING_HS 1 /* HS */
  215. #define EXT_CSD_TIMING_HS200 2 /* HS200 */
  216. #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
  217. #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
  218. #define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0)
  219. #define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0)
  220. #define EXT_CSD_BOOT_ACK(x) (x << 6)
  221. #define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
  222. #define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
  223. #define EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1)
  224. #define EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7)
  225. #define EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7)
  226. #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3)
  227. #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
  228. #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
  229. #define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
  230. #define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */
  231. #define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */
  232. #define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */
  233. #define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */
  234. #define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */
  235. #define R1_ILLEGAL_COMMAND (1 << 22)
  236. #define R1_APP_CMD (1 << 5)
  237. #define MMC_RSP_PRESENT (1 << 0)
  238. #define MMC_RSP_136 (1 << 1) /* 136 bit response */
  239. #define MMC_RSP_CRC (1 << 2) /* expect valid crc */
  240. #define MMC_RSP_BUSY (1 << 3) /* card may send busy */
  241. #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
  242. #define MMC_RSP_NONE (0)
  243. #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
  244. #define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
  245. MMC_RSP_BUSY)
  246. #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
  247. #define MMC_RSP_R3 (MMC_RSP_PRESENT)
  248. #define MMC_RSP_R4 (MMC_RSP_PRESENT)
  249. #define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
  250. #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
  251. #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
  252. #define MMCPART_NOAVAILABLE (0xff)
  253. #define PART_ACCESS_MASK (0x7)
  254. #define PART_SUPPORT (0x1)
  255. #define ENHNCD_SUPPORT (0x2)
  256. #define PART_ENH_ATTRIB (0x1f)
  257. #define MMC_QUIRK_RETRY_SEND_CID BIT(0)
  258. #define MMC_QUIRK_RETRY_SET_BLOCKLEN BIT(1)
  259. enum mmc_voltage {
  260. MMC_SIGNAL_VOLTAGE_000 = 0,
  261. MMC_SIGNAL_VOLTAGE_120 = 1,
  262. MMC_SIGNAL_VOLTAGE_180 = 2,
  263. MMC_SIGNAL_VOLTAGE_330 = 4,
  264. };
  265. #define MMC_ALL_SIGNAL_VOLTAGE (MMC_SIGNAL_VOLTAGE_120 |\
  266. MMC_SIGNAL_VOLTAGE_180 |\
  267. MMC_SIGNAL_VOLTAGE_330)
  268. /* Maximum block size for MMC */
  269. #define MMC_MAX_BLOCK_LEN 512
  270. /* The number of MMC physical partitions. These consist of:
  271. * boot partitions (2), general purpose partitions (4) in MMC v4.4.
  272. */
  273. #define MMC_NUM_BOOT_PARTITION 2
  274. #define MMC_PART_RPMB 3 /* RPMB partition number */
  275. /* Driver model support */
  276. /**
  277. * struct mmc_uclass_priv - Holds information about a device used by the uclass
  278. */
  279. struct mmc_uclass_priv {
  280. struct mmc *mmc;
  281. };
  282. /* End of driver model support */
  283. struct mmc_cid {
  284. unsigned long psn;
  285. unsigned short oid;
  286. unsigned char mid;
  287. unsigned char prv;
  288. unsigned char mdt;
  289. char pnm[7];
  290. };
  291. struct mmc_cmd {
  292. u16 cmdidx;
  293. u32 resp_type;
  294. u32 cmdarg;
  295. u32 response[4];
  296. };
  297. struct mmc_data {
  298. union {
  299. char *dest;
  300. const char *src; /* src buffers don't get written to */
  301. };
  302. u32 flags;
  303. u32 blocks;
  304. u32 blocksize;
  305. };
  306. /* forward decl. */
  307. struct mmc;
  308. struct mmc_ops {
  309. int (*send_cmd)(struct mmc *mmc,
  310. struct mmc_cmd *cmd, struct mmc_data *data);
  311. void (*set_ios)(struct mmc *mmc);
  312. int (*init)(struct mmc *mmc);
  313. int (*getcd)(struct mmc *mmc);
  314. int (*getwp)(struct mmc *mmc);
  315. };
  316. struct mmc_config {
  317. const char *name;
  318. const struct mmc_ops *ops;
  319. u32 host_caps;
  320. u32 voltages;
  321. u32 f_min;
  322. u32 f_max;
  323. u32 b_max;
  324. unsigned char part_type;
  325. };
  326. struct sd_ssr {
  327. unsigned int au; /* In sectors */
  328. unsigned int erase_timeout; /* In milliseconds */
  329. unsigned int erase_offset; /* In milliseconds */
  330. };
  331. enum bus_mode {
  332. MMC_LEGACY,
  333. SD_LEGACY,
  334. MMC_HS,
  335. SD_HS,
  336. MMC_HS_52,
  337. MMC_DDR_52,
  338. UHS_SDR12,
  339. UHS_SDR25,
  340. UHS_SDR50,
  341. UHS_DDR50,
  342. UHS_SDR104,
  343. MMC_HS_200,
  344. MMC_MODES_END
  345. };
  346. /* Interface types: */
  347. enum if_type {
  348. IF_TYPE_UNKNOWN = 0,
  349. IF_TYPE_IDE,
  350. IF_TYPE_SCSI,
  351. IF_TYPE_ATAPI,
  352. IF_TYPE_USB,
  353. IF_TYPE_DOC,
  354. IF_TYPE_MMC,
  355. IF_TYPE_SD,
  356. IF_TYPE_SATA,
  357. IF_TYPE_HOST,
  358. IF_TYPE_NVME,
  359. IF_TYPE_EFI,
  360. IF_TYPE_COUNT, /* Number of interface types */
  361. };
  362. #define BLK_VEN_SIZE 40
  363. #define BLK_PRD_SIZE 20
  364. #define BLK_REV_SIZE 8
  365. /*
  366. * Identifies the partition table type (ie. MBR vs GPT GUID) signature
  367. */
  368. enum sig_type {
  369. SIG_TYPE_NONE,
  370. SIG_TYPE_MBR,
  371. SIG_TYPE_GUID,
  372. SIG_TYPE_COUNT /* Number of signature types */
  373. };
  374. typedef struct {
  375. u8 b[16];
  376. } efi_guid_t;
  377. typedef struct block_dev_desc {
  378. enum if_type if_type; /* type of the interface */
  379. int dev; /* device number */
  380. unsigned char part_type; /* partition type */
  381. unsigned char target; /* target SCSI ID */
  382. unsigned char lun; /* target LUN */
  383. unsigned char hwpart; /* HW partition, e.g. for eMMC */
  384. unsigned char type; /* device type */
  385. unsigned char removable; /* removable device */
  386. #ifdef CONFIG_LBA48
  387. unsigned char lba48; /* device can use 48bit addr (ATA/ATAPI v7) */
  388. #endif
  389. u32 lba; /* number of blocks */
  390. unsigned long blksz; /* block size */
  391. int log2blksz; /* for convenience: log2(blksz) */
  392. char vendor [40+1]; /* IDE model, SCSI Vendor */
  393. char product[20+1]; /* IDE Serial no, SCSI product */
  394. char revision[8+1]; /* firmware revision */
  395. enum sig_type sig_type; /* Partition table signature type */
  396. union {
  397. uint32_t mbr_sig; /* MBR integer signature */
  398. efi_guid_t guid_sig; /* GPT GUID Signature */
  399. };
  400. unsigned long (*block_read)(int dev_num, unsigned long start, unsigned long blkcnt, void *dst);
  401. unsigned long (*block_write)(int dev_num, unsigned int start, unsigned int blkcnt, const void *src);
  402. unsigned long (*block_erase)(int dev,
  403. u32 start,
  404. u32 blkcnt);
  405. void *priv; /* driver private struct pointer */
  406. }block_dev_desc_t;
  407. static inline bool mmc_is_mode_ddr(enum bus_mode mode)
  408. {
  409. if (mode == MMC_DDR_52)
  410. return true;
  411. else
  412. return false;
  413. }
  414. #define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \
  415. MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \
  416. MMC_CAP(UHS_DDR50))
  417. static inline bool supports_uhs(u32 caps)
  418. {
  419. return false;
  420. }
  421. /* TODO struct mmc should be in mmc_private but it's hard to fix right now */
  422. struct mmc {
  423. //struct list_head link;
  424. const struct mmc_config *cfg; /* provided configuration */
  425. u32 version;
  426. void *priv;
  427. u32 has_init;
  428. u32 high_capacity;
  429. bool clk_disable; /* true if the clock can be turned off */
  430. u32 bus_width;
  431. u32 clock;
  432. enum mmc_voltage signal_voltage;
  433. u32 card_caps;
  434. u32 host_caps;
  435. u32 ocr;
  436. u32 dsr;
  437. u32 dsr_imp;
  438. u32 scr[2];
  439. u32 csd[4];
  440. u32 cid[4];
  441. u16 rca;
  442. u8 part_support;
  443. u8 part_attr;
  444. u8 wr_rel_set;
  445. char part_config;
  446. u32 tran_speed;
  447. u32 legacy_speed; /* speed for the legacy mode provided by the card */
  448. u32 read_bl_len;
  449. u32 write_bl_len;
  450. u32 erase_grp_size; /* in 512-byte sectors */
  451. u32 hc_wp_grp_size; /* in 512-byte sectors */
  452. struct sd_ssr ssr; /* SD status register */
  453. UINT64 capacity;
  454. UINT64 capacity_user;
  455. UINT64 capacity_boot;
  456. UINT64 capacity_rpmb;
  457. UINT64 capacity_gp[4];
  458. UINT64 enh_user_start;
  459. UINT64 enh_user_size;
  460. block_dev_desc_t block_dev;
  461. char op_cond_pending; /* 1 if we are waiting on an op_cond command */
  462. char init_in_progress; /* 1 if we have done mmc_start_init() */
  463. char preinit; /* start init as early as possible */
  464. int ddr_mode;
  465. u8 *ext_csd;
  466. u32 cardtype; /* cardtype read from the MMC */
  467. enum mmc_voltage current_voltage;
  468. enum bus_mode selected_mode; /* mode currently used */
  469. enum bus_mode best_mode; /* best mode is the supported mode with the
  470. * highest bandwidth. It may not always be the
  471. * operating mode due to limitations when
  472. * accessing the boot partitions
  473. */
  474. u32 quirks;
  475. };
  476. struct mmc_hwpart_conf {
  477. struct {
  478. u32 enh_start; /* in 512-byte sectors */
  479. u32 enh_size; /* in 512-byte sectors, if 0 no enh area */
  480. unsigned wr_rel_change : 1;
  481. unsigned wr_rel_set : 1;
  482. } user;
  483. struct {
  484. u32 size; /* in 512-byte sectors */
  485. unsigned enhanced : 1;
  486. unsigned wr_rel_change : 1;
  487. unsigned wr_rel_set : 1;
  488. } gp_part[4];
  489. };
  490. enum mmc_hwpart_conf_mode {
  491. MMC_HWPART_CONF_CHECK,
  492. MMC_HWPART_CONF_SET,
  493. MMC_HWPART_CONF_COMPLETE,
  494. };
  495. int mmc_register(struct mmc *mmc);
  496. struct mmc *mmc_create(const struct mmc_config *cfg, void *priv, u32 dev_num);
  497. void mmc_destroy(struct mmc *mmc);
  498. int mmc_init(struct mmc *mmc);
  499. int mmc_read(struct mmc *mmc, UINT64 src, unsigned char *dst, int size);
  500. void mmc_set_clock(struct mmc *mmc, u32 clock, bool disable);
  501. #define MMC_CLK_ENABLE false
  502. #define MMC_CLK_DISABLE true
  503. int mmc_set_dev(int dev_num);
  504. void print_mmc_devices(char separator);
  505. int mmc_switch_part(int dev_num, unsigned int part_num);
  506. int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
  507. enum mmc_hwpart_conf_mode mode);
  508. int mmc_getcd(struct mmc *mmc);
  509. //int board_mmc_getcd(struct mmc *mmc);
  510. int mmc_getwp(struct mmc *mmc);
  511. int board_mmc_getwp(struct mmc *mmc);
  512. int mmc_set_dsr(struct mmc *mmc, u16 val);
  513. /* Function to change the size of boot partition and rpmb partitions */
  514. int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
  515. unsigned long rpmbsize);
  516. /* Function to modify the PARTITION_CONFIG field of EXT_CSD */
  517. int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
  518. /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
  519. int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
  520. /* Function to modify the RST_n_FUNCTION field of EXT_CSD */
  521. int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
  522. /* Functions to read / write the RPMB partition */
  523. int mmc_rpmb_set_key(struct mmc *mmc, void *key);
  524. int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
  525. int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
  526. unsigned short cnt, unsigned char *key);
  527. int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
  528. unsigned short cnt, unsigned char *key);
  529. /**
  530. * Start device initialization and return immediately; it does not block on
  531. * polling OCR (operation condition register) status. Then you should call
  532. * mmc_init, which would block on polling OCR status and complete the device
  533. * initializatin.
  534. *
  535. * @param mmc Pointer to a MMC device struct
  536. * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
  537. */
  538. int mmc_start_init(struct mmc *mmc);
  539. #define mmc_host_is_spi(mmc) 0
  540. void board_mmc_power_init(void);
  541. int board_mmc_init();
  542. int cpu_mmc_init();
  543. int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
  544. /* Set block count limit because of 16 bit register limit on some hardware*/
  545. #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
  546. #define CONFIG_SYS_MMC_MAX_BLK_COUNT 2048
  547. #endif
  548. #endif /* _MMC_H_ */