mmc.c 38 KB

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  1. /*
  2. * Copyright 2008, Freescale Semiconductor, Inc
  3. * Andy Fleming
  4. *
  5. * Based vaguely on the Linux code
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <comdef.h>
  10. #include <mmc.h>
  11. #include <uart.h>
  12. #include <sys.h>
  13. #include <timer.h>
  14. #include "mmc_private.h"
  15. #include "util.h"
  16. #include "sizes.h"
  17. #include "errno.h"
  18. extern struct mmc local_mmc0;
  19. static int cur_dev_num = -1;
  20. const char *mmc_mode_name(enum bus_mode mode)
  21. {
  22. static const char *const names[] = {
  23. [MMC_LEGACY] = "MMC legacy",
  24. [SD_LEGACY] = "SD Legacy",
  25. [MMC_HS] = "MMC High Speed (26MHz)",
  26. [SD_HS] = "SD High Speed (50MHz)",
  27. [UHS_SDR12] = "UHS SDR12 (25MHz)",
  28. [UHS_SDR25] = "UHS SDR25 (50MHz)",
  29. [UHS_SDR50] = "UHS SDR50 (100MHz)",
  30. [UHS_SDR104] = "UHS SDR104 (208MHz)",
  31. [UHS_DDR50] = "UHS DDR50 (50MHz)",
  32. [MMC_HS_52] = "MMC High Speed (52MHz)",
  33. [MMC_DDR_52] = "MMC DDR52 (52MHz)",
  34. [MMC_HS_200] = "HS200 (200MHz)",
  35. };
  36. if (mode >= MMC_MODES_END)
  37. return "Unknown mode";
  38. else
  39. return names[mode];
  40. }
  41. static u32 mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
  42. {
  43. static const int freqs[] = {
  44. [MMC_LEGACY] = 25000000,
  45. [SD_LEGACY] = 25000000,
  46. [MMC_HS] = 26000000,
  47. [SD_HS] = 50000000,
  48. [MMC_HS_52] = 52000000,
  49. [MMC_DDR_52] = 52000000,
  50. [UHS_SDR12] = 25000000,
  51. [UHS_SDR25] = 50000000,
  52. [UHS_SDR50] = 100000000,
  53. [UHS_DDR50] = 50000000,
  54. [UHS_SDR104] = 208000000,
  55. [MMC_HS_200] = 200000000,
  56. };
  57. if (mode == MMC_LEGACY)
  58. return mmc->legacy_speed;
  59. else if (mode >= MMC_MODES_END)
  60. return 0;
  61. else
  62. return freqs[mode];
  63. }
  64. static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
  65. {
  66. mmc->selected_mode = mode;
  67. mmc->tran_speed = mmc_mode2freq(mmc, mode);
  68. mmc->ddr_mode = mmc_is_mode_ddr(mode);
  69. // printk("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
  70. // mmc->tran_speed / 1000000);
  71. return 0;
  72. }
  73. int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
  74. {
  75. int ret;
  76. ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
  77. return ret;
  78. }
  79. int mmc_send_status(struct mmc *mmc, int timeout)
  80. {
  81. struct mmc_cmd cmd;
  82. int err, retries = 5;
  83. cmd.cmdidx = MMC_CMD_SEND_STATUS;
  84. cmd.resp_type = MMC_RSP_R1;
  85. if (!mmc_host_is_spi(mmc))
  86. cmd.cmdarg = mmc->rca << 16;
  87. while (1) {
  88. err = mmc_send_cmd(mmc, &cmd, NULL);
  89. if (!err) {
  90. if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
  91. (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
  92. MMC_STATE_PRG)
  93. break;
  94. else if (cmd.response[0] & MMC_STATUS_MASK) {
  95. return -ECOMM;
  96. }
  97. } else if (--retries < 0)
  98. return err;
  99. if (timeout-- <= 0)
  100. break;
  101. udelay(100);
  102. }
  103. if (timeout <= 0) {
  104. return -ETIMEDOUT;
  105. }
  106. return 0;
  107. }
  108. int mmc_set_blocklen(struct mmc *mmc, int len)
  109. {
  110. struct mmc_cmd cmd;
  111. if (mmc->ddr_mode)
  112. return 0;
  113. cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
  114. cmd.resp_type = MMC_RSP_R1;
  115. cmd.cmdarg = len;
  116. return mmc_send_cmd(mmc, &cmd, NULL);
  117. }
  118. static int mmc_read_blocks(struct mmc *mmc, void *dst, unsigned long start,
  119. unsigned long blkcnt)
  120. {
  121. struct mmc_cmd cmd;
  122. struct mmc_data data;
  123. if (blkcnt > 1)
  124. cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
  125. else
  126. cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
  127. if (mmc->high_capacity)
  128. cmd.cmdarg = start;
  129. else
  130. cmd.cmdarg = start * mmc->read_bl_len;
  131. cmd.resp_type = MMC_RSP_R1;
  132. data.dest = dst;
  133. data.blocks = blkcnt;
  134. data.blocksize = mmc->read_bl_len;
  135. data.flags = MMC_DATA_READ;
  136. if (mmc_send_cmd(mmc, &cmd, &data))
  137. return 0;
  138. if (blkcnt > 1) {
  139. cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
  140. cmd.cmdarg = 0;
  141. cmd.resp_type = MMC_RSP_R1b;
  142. if (mmc_send_cmd(mmc, &cmd, NULL)) {
  143. return 0;
  144. }
  145. }
  146. return blkcnt;
  147. }
  148. static unsigned long mmc_bread(int dev_num, unsigned long start, unsigned long blkcnt, void *dst)
  149. {
  150. unsigned long cur, blocks_todo = blkcnt;
  151. struct mmc *mmc;
  152. if (blkcnt == 0)
  153. return 0;
  154. if(dev_num == 0)
  155. mmc = &local_mmc0;
  156. if (!mmc)
  157. return 0;
  158. if ((start + blkcnt) > mmc->block_dev.lba) {
  159. return 0;
  160. }
  161. if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
  162. return 0;
  163. }
  164. do {
  165. cur = (blocks_todo > mmc->cfg->b_max) ?
  166. mmc->cfg->b_max : blocks_todo;
  167. if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
  168. return 0;
  169. }
  170. blocks_todo -= cur;
  171. start += cur;
  172. dst += cur * mmc->read_bl_len;
  173. } while (blocks_todo > 0);
  174. return blkcnt;
  175. }
  176. static int mmc_go_idle(struct mmc *mmc)
  177. {
  178. struct mmc_cmd cmd;
  179. int err;
  180. udelay(100);
  181. cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
  182. cmd.cmdarg = 0;
  183. cmd.resp_type = MMC_RSP_NONE;
  184. err = mmc_send_cmd(mmc, &cmd, NULL);
  185. if (err)
  186. return err;
  187. udelay(200);
  188. return 0;
  189. }
  190. static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
  191. {
  192. int timeout = 1000;
  193. int err;
  194. struct mmc_cmd cmd;
  195. while (1) {
  196. cmd.cmdidx = MMC_CMD_APP_CMD;
  197. cmd.resp_type = MMC_RSP_R1;
  198. cmd.cmdarg = 0;
  199. err = mmc_send_cmd(mmc, &cmd, NULL);
  200. if (err)
  201. return err;
  202. cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
  203. cmd.resp_type = MMC_RSP_R3;
  204. /*
  205. * Most cards do not answer if some reserved bits
  206. * in the ocr are set. However, Some controller
  207. * can set bit 7 (reserved for low voltages), but
  208. * how to manage low voltages SD card is not yet
  209. * specified.
  210. */
  211. cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
  212. (mmc->cfg->voltages & 0xff8000);
  213. if (mmc->version == SD_VERSION_2)
  214. cmd.cmdarg |= OCR_HCS;
  215. if (uhs_en)
  216. cmd.cmdarg |= OCR_S18R;
  217. err = mmc_send_cmd(mmc, &cmd, NULL);
  218. if (err)
  219. return err;
  220. if (cmd.response[0] & OCR_BUSY)
  221. break;
  222. if (timeout-- <= 0)
  223. return -EOPNOTSUPP;
  224. udelay(1000);
  225. }
  226. if (mmc->version != SD_VERSION_2)
  227. mmc->version = SD_VERSION_1_0;
  228. if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
  229. cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
  230. cmd.resp_type = MMC_RSP_R3;
  231. cmd.cmdarg = 0;
  232. err = mmc_send_cmd(mmc, &cmd, NULL);
  233. if (err)
  234. return err;
  235. }
  236. mmc->ocr = cmd.response[0];
  237. mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
  238. mmc->rca = 0;
  239. return 0;
  240. }
  241. static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
  242. {
  243. struct mmc_cmd cmd;
  244. int err;
  245. cmd.cmdidx = MMC_CMD_SEND_OP_COND;
  246. cmd.resp_type = MMC_RSP_R3;
  247. cmd.cmdarg = 0;
  248. if (use_arg && !mmc_host_is_spi(mmc))
  249. cmd.cmdarg = OCR_HCS |
  250. (mmc->cfg->voltages &
  251. (mmc->ocr & OCR_VOLTAGE_MASK)) |
  252. (mmc->ocr & OCR_ACCESS_MODE);
  253. err = mmc_send_cmd(mmc, &cmd, NULL);
  254. if (err)
  255. return err;
  256. mmc->ocr = cmd.response[0];
  257. return 0;
  258. }
  259. static int mmc_send_op_cond(struct mmc *mmc)
  260. {
  261. int err, i;
  262. /* Some cards seem to need this */
  263. mmc_go_idle(mmc);
  264. /* Asking to the card its capabilities */
  265. for (i = 0; i < 2; i++) {
  266. err = mmc_send_op_cond_iter(mmc, i != 0);
  267. if (err)
  268. return err;
  269. /* exit if not busy (flag seems to be inverted) */
  270. if (mmc->ocr & OCR_BUSY)
  271. break;
  272. }
  273. mmc->op_cond_pending = 1;
  274. return 0;
  275. }
  276. static int mmc_complete_op_cond(struct mmc *mmc)
  277. {
  278. struct mmc_cmd cmd;
  279. int timeout = 1000;
  280. u64 start;
  281. int err;
  282. mmc->op_cond_pending = 0;
  283. if (!(mmc->ocr & OCR_BUSY)) {
  284. /* Some cards seem to need this */
  285. mmc_go_idle(mmc);
  286. start = get_timer(0);
  287. while (1) {
  288. err = mmc_send_op_cond_iter(mmc, 1);
  289. if (err)
  290. return err;
  291. if (mmc->ocr & OCR_BUSY)
  292. break;
  293. if (get_timer(start) > timeout)
  294. return -EOPNOTSUPP;
  295. udelay(100);
  296. }
  297. }
  298. if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
  299. cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
  300. cmd.resp_type = MMC_RSP_R3;
  301. cmd.cmdarg = 0;
  302. err = mmc_send_cmd(mmc, &cmd, NULL);
  303. if (err)
  304. return err;
  305. mmc->ocr = cmd.response[0];
  306. }
  307. mmc->version = MMC_VERSION_UNKNOWN;
  308. mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
  309. mmc->rca = 1;
  310. return 0;
  311. }
  312. static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
  313. {
  314. struct mmc_cmd cmd;
  315. struct mmc_data data;
  316. int err;
  317. /* Get the Card Status Register */
  318. cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
  319. cmd.resp_type = MMC_RSP_R1;
  320. cmd.cmdarg = 0;
  321. data.dest = (char *)ext_csd;
  322. data.blocks = 1;
  323. data.blocksize = MMC_MAX_BLOCK_LEN;
  324. data.flags = MMC_DATA_READ;
  325. err = mmc_send_cmd(mmc, &cmd, &data);
  326. return err;
  327. }
  328. static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
  329. {
  330. struct mmc_cmd cmd;
  331. int timeout = 1000;
  332. int retries = 3;
  333. int ret;
  334. cmd.cmdidx = MMC_CMD_SWITCH;
  335. cmd.resp_type = MMC_RSP_R1b;
  336. cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
  337. (index << 16) |
  338. (value << 8);
  339. while (retries > 0) {
  340. ret = mmc_send_cmd(mmc, &cmd, NULL);
  341. /* Waiting for the ready status */
  342. if (!ret) {
  343. ret = mmc_send_status(mmc, timeout);
  344. return ret;
  345. }
  346. retries--;
  347. }
  348. return ret;
  349. }
  350. static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode)
  351. {
  352. int err;
  353. int speed_bits;
  354. ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
  355. switch (mode) {
  356. case MMC_HS:
  357. case MMC_HS_52:
  358. case MMC_DDR_52:
  359. speed_bits = EXT_CSD_TIMING_HS;
  360. break;
  361. case MMC_LEGACY:
  362. speed_bits = EXT_CSD_TIMING_LEGACY;
  363. break;
  364. default:
  365. return -EINVAL;
  366. }
  367. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
  368. speed_bits);
  369. if (err)
  370. return err;
  371. if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
  372. /* Now check to see that it worked */
  373. err = mmc_send_ext_csd(mmc, test_csd);
  374. if (err)
  375. return err;
  376. /* No high-speed support */
  377. if (!test_csd[EXT_CSD_HS_TIMING])
  378. return -ENOTSUPP;
  379. }
  380. return 0;
  381. }
  382. static int mmc_get_capabilities(struct mmc *mmc)
  383. {
  384. u8 *ext_csd = mmc->ext_csd;
  385. char cardtype;
  386. mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
  387. if (mmc_host_is_spi(mmc))
  388. return 0;
  389. /* Only version 4 supports high-speed */
  390. if (mmc->version < MMC_VERSION_4)
  391. return 0;
  392. if (!ext_csd) {
  393. printk("No ext_csd found!\n"); /* this should enver happen */
  394. return -ENOTSUPP;
  395. }
  396. mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
  397. cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0x3f;
  398. mmc->cardtype = cardtype;
  399. if (cardtype & EXT_CSD_CARD_TYPE_52) {
  400. if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
  401. mmc->card_caps |= MMC_MODE_DDR_52MHz;
  402. mmc->card_caps |= MMC_MODE_HS_52MHz;
  403. }
  404. if (cardtype & EXT_CSD_CARD_TYPE_26)
  405. mmc->card_caps |= MMC_MODE_HS;
  406. return 0;
  407. }
  408. static int mmc_set_capacity(struct mmc *mmc, int part_num)
  409. {
  410. switch (part_num) {
  411. case 0:
  412. mmc->capacity = mmc->capacity_user;
  413. break;
  414. case 1:
  415. case 2:
  416. mmc->capacity = mmc->capacity_boot;
  417. break;
  418. case 3:
  419. mmc->capacity = mmc->capacity_rpmb;
  420. break;
  421. case 4:
  422. case 5:
  423. case 6:
  424. case 7:
  425. mmc->capacity = mmc->capacity_gp[part_num - 4];
  426. break;
  427. default:
  428. return -1;
  429. }
  430. mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
  431. return 0;
  432. }
  433. static inline int bus_width(u32 cap)
  434. {
  435. if (cap == MMC_MODE_8BIT)
  436. return 8;
  437. if (cap == MMC_MODE_4BIT)
  438. return 4;
  439. if (cap == MMC_MODE_1BIT)
  440. return 1;
  441. printk("invalid bus witdh capability 0x%x\n", cap);
  442. return 0;
  443. }
  444. static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
  445. {
  446. struct mmc_cmd cmd;
  447. struct mmc_data data;
  448. /* Switch the frequency */
  449. cmd.cmdidx = SD_CMD_SWITCH_FUNC;
  450. cmd.resp_type = MMC_RSP_R1;
  451. cmd.cmdarg = (mode << 31) | 0xffffff;
  452. cmd.cmdarg &= ~(0xf << (group * 4));
  453. cmd.cmdarg |= value << (group * 4);
  454. data.dest = (char *)resp;
  455. data.blocksize = 64;
  456. data.blocks = 1;
  457. data.flags = MMC_DATA_READ;
  458. return mmc_send_cmd(mmc, &cmd, &data);
  459. }
  460. static int sd_get_capabilities(struct mmc *mmc)
  461. {
  462. int err;
  463. struct mmc_cmd cmd;
  464. ALLOC_CACHE_ALIGN_BUFFER(u32, scr, 2);
  465. ALLOC_CACHE_ALIGN_BUFFER(u32, switch_status, 16);
  466. struct mmc_data data;
  467. int timeout;
  468. mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(SD_LEGACY);
  469. if (mmc_host_is_spi(mmc))
  470. return 0;
  471. /* Read the SCR to find out if this card supports higher speeds */
  472. cmd.cmdidx = MMC_CMD_APP_CMD;
  473. cmd.resp_type = MMC_RSP_R1;
  474. cmd.cmdarg = mmc->rca << 16;
  475. err = mmc_send_cmd(mmc, &cmd, NULL);
  476. if (err)
  477. return err;
  478. cmd.cmdidx = SD_CMD_APP_SEND_SCR;
  479. cmd.resp_type = MMC_RSP_R1;
  480. cmd.cmdarg = 0;
  481. timeout = 3;
  482. retry_scr:
  483. data.dest = (char *)scr;
  484. data.blocksize = 8;
  485. data.blocks = 1;
  486. data.flags = MMC_DATA_READ;
  487. err = mmc_send_cmd(mmc, &cmd, &data);
  488. if (err) {
  489. if (timeout--)
  490. goto retry_scr;
  491. return err;
  492. }
  493. mmc->scr[0] = __be32_to_cpu(scr[0]);
  494. mmc->scr[1] = __be32_to_cpu(scr[1]);
  495. switch ((mmc->scr[0] >> 24) & 0xf) {
  496. case 0:
  497. mmc->version = SD_VERSION_1_0;
  498. break;
  499. case 1:
  500. mmc->version = SD_VERSION_1_10;
  501. break;
  502. case 2:
  503. mmc->version = SD_VERSION_2;
  504. if ((mmc->scr[0] >> 15) & 0x1)
  505. mmc->version = SD_VERSION_3;
  506. break;
  507. default:
  508. mmc->version = SD_VERSION_1_0;
  509. break;
  510. }
  511. if (mmc->scr[0] & SD_DATA_4BIT)
  512. mmc->card_caps |= MMC_MODE_4BIT;
  513. /* Version 1.0 doesn't support switching */
  514. if (mmc->version == SD_VERSION_1_0)
  515. return 0;
  516. timeout = 4;
  517. while (timeout--) {
  518. err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
  519. (u8 *)switch_status);
  520. if (err)
  521. return err;
  522. /* The high-speed function is busy. Try again */
  523. if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
  524. break;
  525. }
  526. /* If high-speed isn't supported, we return */
  527. if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
  528. mmc->card_caps |= MMC_CAP(SD_HS);
  529. return 0;
  530. }
  531. static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
  532. {
  533. int err;
  534. ALLOC_CACHE_ALIGN_BUFFER(u32, switch_status, 16);
  535. int speed;
  536. switch (mode) {
  537. case SD_LEGACY:
  538. speed = UHS_SDR12_BUS_SPEED;
  539. break;
  540. case SD_HS:
  541. speed = HIGH_SPEED_BUS_SPEED;
  542. break;
  543. default:
  544. return -EINVAL;
  545. }
  546. err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
  547. if (err)
  548. return err;
  549. if (((__be32_to_cpu(switch_status[4]) >> 24) & 0xF) != speed)
  550. return -ENOTSUPP;
  551. return 0;
  552. }
  553. static int sd_select_bus_width(struct mmc *mmc, int w)
  554. {
  555. int err;
  556. struct mmc_cmd cmd;
  557. if ((w != 4) && (w != 1))
  558. return -EINVAL;
  559. cmd.cmdidx = MMC_CMD_APP_CMD;
  560. cmd.resp_type = MMC_RSP_R1;
  561. cmd.cmdarg = mmc->rca << 16;
  562. err = mmc_send_cmd(mmc, &cmd, NULL);
  563. if (err)
  564. return err;
  565. cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
  566. cmd.resp_type = MMC_RSP_R1;
  567. if (w == 4)
  568. cmd.cmdarg = 2;
  569. else if (w == 1)
  570. cmd.cmdarg = 0;
  571. err = mmc_send_cmd(mmc, &cmd, NULL);
  572. if (err)
  573. return err;
  574. return 0;
  575. }
  576. static int sd_read_ssr(struct mmc *mmc)
  577. {
  578. static const unsigned int sd_au_size[] = {
  579. 0, SZ_16K / 512, SZ_32K / 512,
  580. SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
  581. SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
  582. SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
  583. SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512,
  584. SZ_64M / 512,
  585. };
  586. int err, i;
  587. struct mmc_cmd cmd;
  588. ALLOC_CACHE_ALIGN_BUFFER(u32, ssr, 16);
  589. struct mmc_data data;
  590. int timeout = 3;
  591. unsigned int au, eo, et, es;
  592. cmd.cmdidx = MMC_CMD_APP_CMD;
  593. cmd.resp_type = MMC_RSP_R1;
  594. cmd.cmdarg = mmc->rca << 16;
  595. err = mmc_send_cmd(mmc, &cmd, NULL);
  596. if (err)
  597. return err;
  598. cmd.cmdidx = SD_CMD_APP_SD_STATUS;
  599. cmd.resp_type = MMC_RSP_R1;
  600. cmd.cmdarg = 0;
  601. retry_ssr:
  602. data.dest = (char *)ssr;
  603. data.blocksize = 64;
  604. data.blocks = 1;
  605. data.flags = MMC_DATA_READ;
  606. err = mmc_send_cmd(mmc, &cmd, &data);
  607. if (err) {
  608. if (timeout--)
  609. goto retry_ssr;
  610. return err;
  611. }
  612. for (i = 0; i < 16; i++)
  613. ssr[i] = __be32_to_cpu(ssr[i]);
  614. au = (ssr[2] >> 12) & 0xF;
  615. if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
  616. mmc->ssr.au = sd_au_size[au];
  617. es = (ssr[3] >> 24) & 0xFF;
  618. es |= (ssr[2] & 0xFF) << 8;
  619. et = (ssr[3] >> 18) & 0x3F;
  620. if (es && et) {
  621. eo = (ssr[3] >> 16) & 0x3;
  622. mmc->ssr.erase_timeout = (et * 1000) / es;
  623. mmc->ssr.erase_offset = eo * 1000;
  624. }
  625. } else {
  626. printk("Invalid Allocation Unit Size.\n");
  627. }
  628. return 0;
  629. }
  630. /* frequency bases */
  631. /* divided by 10 to be nice to platforms without floating point */
  632. static const int fbase[] = {
  633. 10000,
  634. 100000,
  635. 1000000,
  636. 10000000,
  637. };
  638. /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
  639. * to platforms without floating point.
  640. */
  641. static const int multipliers[] = {
  642. 0, /* reserved */
  643. 10,
  644. 12,
  645. 13,
  646. 15,
  647. 20,
  648. 25,
  649. 30,
  650. 35,
  651. 40,
  652. 45,
  653. 50,
  654. 55,
  655. 60,
  656. 70,
  657. 80,
  658. };
  659. static void mmc_set_ios(struct mmc *mmc)
  660. {
  661. if (mmc->cfg->ops->set_ios)
  662. mmc->cfg->ops->set_ios(mmc);
  663. }
  664. void mmc_set_clock(struct mmc *mmc, u32 clock, bool disable)
  665. {
  666. if (!disable) {
  667. if (clock > mmc->cfg->f_max)
  668. clock = mmc->cfg->f_max;
  669. if (clock < mmc->cfg->f_min)
  670. clock = mmc->cfg->f_min;
  671. }
  672. mmc->clock = clock;
  673. mmc->clk_disable = disable;
  674. // printk("clock is %s (%dHz)\n", disable ? "disabled" : "enabled", clock);
  675. mmc_set_ios(mmc);
  676. }
  677. static void mmc_set_bus_width(struct mmc *mmc, u32 width)
  678. {
  679. mmc->bus_width = width;
  680. mmc_set_ios(mmc);
  681. }
  682. struct mode_width_tuning {
  683. enum bus_mode mode;
  684. u32 widths;
  685. };
  686. static const struct mode_width_tuning sd_modes_by_pref[] = {
  687. {
  688. .mode = SD_HS,
  689. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  690. },
  691. {
  692. .mode = SD_LEGACY,
  693. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  694. }
  695. };
  696. #define for_each_sd_mode_by_pref(caps, mwt) \
  697. for (mwt = sd_modes_by_pref;\
  698. mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
  699. mwt++) \
  700. if (caps & MMC_CAP(mwt->mode))
  701. static int sd_select_mode_and_width(struct mmc *mmc, u32 card_caps)
  702. {
  703. int err;
  704. u32 widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
  705. const struct mode_width_tuning *mwt;
  706. bool uhs_en = false;
  707. u32 caps;
  708. if (mmc_host_is_spi(mmc))
  709. {
  710. mmc_select_mode(mmc, SD_LEGACY);
  711. mmc_set_clock(mmc, mmc->tran_speed,
  712. MMC_CLK_ENABLE);
  713. return 0;
  714. }
  715. /* Restrict card's capabilities by what the host can do */
  716. caps = card_caps & mmc->host_caps;
  717. if (!uhs_en)
  718. caps &= ~UHS_CAPS;
  719. for_each_sd_mode_by_pref(caps, mwt) {
  720. u32 *w;
  721. for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
  722. if (*w & caps & mwt->widths) {
  723. // printk("trying mode %s width %d (at %d MHz)\n",
  724. // mmc_mode_name(mwt->mode),
  725. // bus_width(*w),
  726. // mmc_mode2freq(mmc, mwt->mode) / 1000000);
  727. /* configure the bus width (card + host) */
  728. err = sd_select_bus_width(mmc, bus_width(*w));
  729. if (err)
  730. goto error;
  731. mmc_set_bus_width(mmc, bus_width(*w));
  732. /* configure the bus mode (card) */
  733. err = sd_set_card_speed(mmc, mwt->mode);
  734. if (err)
  735. goto error;
  736. /* configure the bus mode (host) */
  737. mmc_select_mode(mmc, mwt->mode);
  738. mmc_set_clock(mmc, mmc->tran_speed,
  739. MMC_CLK_ENABLE);
  740. err = sd_read_ssr(mmc);
  741. if (err)
  742. printk("unable to read ssr\n");
  743. if (!err)
  744. return 0;
  745. error:
  746. /* revert to a safer bus speed */
  747. mmc_select_mode(mmc, SD_LEGACY);
  748. mmc_set_clock(mmc, mmc->tran_speed,
  749. MMC_CLK_ENABLE);
  750. }
  751. }
  752. }
  753. printk("unable to select a mode\n");
  754. return -ENOTSUPP;
  755. }
  756. /*
  757. * read the compare the part of ext csd that is constant.
  758. * This can be used to check that the transfer is working
  759. * as expected.
  760. */
  761. static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
  762. {
  763. int err;
  764. const u8 *ext_csd = mmc->ext_csd;
  765. ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
  766. if (mmc->version < MMC_VERSION_4)
  767. return 0;
  768. err = mmc_send_ext_csd(mmc, test_csd);
  769. if (err)
  770. return err;
  771. /* Only compare read only fields */
  772. if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
  773. == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
  774. ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
  775. == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
  776. ext_csd[EXT_CSD_REV]
  777. == test_csd[EXT_CSD_REV] &&
  778. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
  779. == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
  780. sys_memcmp(&ext_csd[EXT_CSD_SEC_CNT],
  781. &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
  782. return 0;
  783. return -EBADMSG;
  784. }
  785. static const struct mode_width_tuning mmc_modes_by_pref[] = {
  786. {
  787. .mode = MMC_DDR_52,
  788. .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
  789. },
  790. {
  791. .mode = MMC_HS_52,
  792. .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
  793. },
  794. {
  795. .mode = MMC_HS,
  796. .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
  797. },
  798. {
  799. .mode = MMC_LEGACY,
  800. .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
  801. }
  802. };
  803. #define for_each_mmc_mode_by_pref(caps, mwt) \
  804. for (mwt = mmc_modes_by_pref;\
  805. mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
  806. mwt++) \
  807. if (caps & MMC_CAP(mwt->mode))
  808. static const struct ext_csd_bus_width {
  809. u32 cap;
  810. bool is_ddr;
  811. u32 ext_csd_bits;
  812. } ext_csd_bus_width[] = {
  813. {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
  814. {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
  815. {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
  816. {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
  817. {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
  818. };
  819. #define for_each_supported_width(caps, ddr, ecbv) \
  820. for (ecbv = ext_csd_bus_width;\
  821. ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
  822. ecbv++) \
  823. if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
  824. static int mmc_select_mode_and_width(struct mmc *mmc, u32 card_caps)
  825. {
  826. int err;
  827. const struct mode_width_tuning *mwt;
  828. const struct ext_csd_bus_width *ecbw;
  829. /* Restrict card's capabilities by what the host can do */
  830. card_caps &= mmc->host_caps;
  831. /* Only version 4 of MMC supports wider bus widths */
  832. if (mmc->version < MMC_VERSION_4)
  833. return 0;
  834. if (!mmc->ext_csd) {
  835. printk("No ext_csd found!\n"); /* this should enver happen */
  836. return -ENOTSUPP;
  837. }
  838. mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE);
  839. for_each_mmc_mode_by_pref(card_caps, mwt) {
  840. for_each_supported_width(card_caps & mwt->widths,
  841. mmc_is_mode_ddr(mwt->mode), ecbw) {
  842. // printk("trying mode %s width %d (at %d MHz)\n",
  843. // mmc_mode_name(mwt->mode),
  844. // bus_width(ecbw->cap),
  845. // mmc_mode2freq(mmc, mwt->mode) / 1000000);
  846. /* configure the bus width (card + host) */
  847. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  848. EXT_CSD_BUS_WIDTH,
  849. ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
  850. if (err)
  851. goto error;
  852. mmc_set_bus_width(mmc, bus_width(ecbw->cap));
  853. /* configure the bus speed (card) */
  854. err = mmc_set_card_speed(mmc, mwt->mode);
  855. if (err)
  856. goto error;
  857. /*
  858. * configure the bus width AND the ddr mode (card)
  859. * The host side will be taken care of in the next step
  860. */
  861. if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
  862. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  863. EXT_CSD_BUS_WIDTH,
  864. ecbw->ext_csd_bits);
  865. if (err)
  866. goto error;
  867. }
  868. /* configure the bus mode (host) */
  869. mmc_select_mode(mmc, mwt->mode);
  870. mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
  871. /* do a transfer to check the configuration */
  872. err = mmc_read_and_compare_ext_csd(mmc);
  873. if (!err)
  874. return 0;
  875. error:
  876. /* if an error occured, revert to a safer bus mode */
  877. mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  878. EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
  879. mmc_select_mode(mmc, MMC_LEGACY);
  880. mmc_set_bus_width(mmc, 1);
  881. }
  882. }
  883. printk("unable to select a mode\n");
  884. return -ENOTSUPP;
  885. }
  886. static int mmc_startup_v4(struct mmc *mmc)
  887. {
  888. int err, i;
  889. u64 capacity;
  890. bool has_parts = false;
  891. bool part_completed;
  892. static const u32 mmc_versions[] = {
  893. MMC_VERSION_4,
  894. MMC_VERSION_4_1,
  895. MMC_VERSION_4_2,
  896. MMC_VERSION_4_3,
  897. MMC_VERSION_4_4,
  898. MMC_VERSION_4_41,
  899. MMC_VERSION_4_5,
  900. MMC_VERSION_5_0,
  901. MMC_VERSION_5_1
  902. };
  903. ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
  904. if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
  905. return 0;
  906. /* check ext_csd version and capacity */
  907. err = mmc_send_ext_csd(mmc, ext_csd);
  908. if (err)
  909. goto error;
  910. /* store the ext csd for future reference */
  911. sys_memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
  912. if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions))
  913. return -EINVAL;
  914. mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]];
  915. if (mmc->version >= MMC_VERSION_4_2) {
  916. /*
  917. * According to the JEDEC Standard, the value of
  918. * ext_csd's capacity is valid if the value is more
  919. * than 2GB
  920. */
  921. capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
  922. | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
  923. | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
  924. | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
  925. capacity *= MMC_MAX_BLOCK_LEN;
  926. if ((capacity >> 20) > 2 * 1024)
  927. mmc->capacity_user = capacity;
  928. }
  929. /* The partition data may be non-zero but it is only
  930. * effective if PARTITION_SETTING_COMPLETED is set in
  931. * EXT_CSD, so ignore any data if this bit is not set,
  932. * except for enabling the high-capacity group size
  933. * definition (see below).
  934. */
  935. part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
  936. EXT_CSD_PARTITION_SETTING_COMPLETED);
  937. /* store the partition info of emmc */
  938. mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
  939. if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
  940. ext_csd[EXT_CSD_BOOT_MULT])
  941. mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
  942. if (part_completed &&
  943. (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
  944. mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
  945. mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
  946. mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
  947. for (i = 0; i < 4; i++) {
  948. int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
  949. u32 mult = (ext_csd[idx + 2] << 16) +
  950. (ext_csd[idx + 1] << 8) + ext_csd[idx];
  951. if (mult)
  952. has_parts = true;
  953. if (!part_completed)
  954. continue;
  955. mmc->capacity_gp[i] = mult;
  956. mmc->capacity_gp[i] *=
  957. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
  958. mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
  959. mmc->capacity_gp[i] <<= 19;
  960. }
  961. if (part_completed) {
  962. mmc->enh_user_size =
  963. (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
  964. (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
  965. ext_csd[EXT_CSD_ENH_SIZE_MULT];
  966. mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
  967. mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
  968. mmc->enh_user_size <<= 19;
  969. mmc->enh_user_start =
  970. (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
  971. (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
  972. (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
  973. ext_csd[EXT_CSD_ENH_START_ADDR];
  974. if (mmc->high_capacity)
  975. mmc->enh_user_start <<= 9;
  976. }
  977. /*
  978. * Host needs to enable ERASE_GRP_DEF bit if device is
  979. * partitioned. This bit will be lost every time after a reset
  980. * or power off. This will affect erase size.
  981. */
  982. if (part_completed)
  983. has_parts = true;
  984. if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
  985. (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
  986. has_parts = true;
  987. if (has_parts) {
  988. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  989. EXT_CSD_ERASE_GROUP_DEF, 1);
  990. if (err)
  991. goto error;
  992. ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
  993. }
  994. if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
  995. /* Read out group size from ext_csd */
  996. mmc->erase_grp_size =
  997. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
  998. /*
  999. * if high capacity and partition setting completed
  1000. * SEC_COUNT is valid even if it is smaller than 2 GiB
  1001. * JEDEC Standard JESD84-B45, 6.2.4
  1002. */
  1003. if (mmc->high_capacity && part_completed) {
  1004. capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
  1005. (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
  1006. (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
  1007. (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
  1008. capacity *= MMC_MAX_BLOCK_LEN;
  1009. mmc->capacity_user = capacity;
  1010. }
  1011. }
  1012. else {
  1013. /* Calculate the group size from the csd value. */
  1014. int erase_gsz, erase_gmul;
  1015. erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
  1016. erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
  1017. mmc->erase_grp_size = (erase_gsz + 1)
  1018. * (erase_gmul + 1);
  1019. }
  1020. mmc->hc_wp_grp_size = 1024
  1021. * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
  1022. * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
  1023. mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
  1024. return 0;
  1025. error:
  1026. if (mmc->ext_csd) {
  1027. mmc->ext_csd = NULL;
  1028. }
  1029. return err;
  1030. }
  1031. static int mmc_startup(struct mmc *mmc)
  1032. {
  1033. int err, i;
  1034. u32 mult, freq;
  1035. UINT64 cmult, csize;
  1036. struct mmc_cmd cmd;
  1037. ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
  1038. ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
  1039. int timeout = 1000;
  1040. unsigned int has_parts = 0;
  1041. unsigned int part_completed;
  1042. /* Put the Card in Identify Mode */
  1043. cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
  1044. MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
  1045. cmd.resp_type = MMC_RSP_R2;
  1046. cmd.cmdarg = 0;
  1047. err = mmc_send_cmd(mmc, &cmd, NULL);
  1048. if (err)
  1049. return err;
  1050. sys_memcpy(mmc->cid, cmd.response, 16);
  1051. /*
  1052. * For MMC cards, set the Relative Address.
  1053. * For SD cards, get the Relatvie Address.
  1054. * This also printf the cards into Standby State
  1055. */
  1056. if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
  1057. cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
  1058. cmd.cmdarg = mmc->rca << 16;
  1059. cmd.resp_type = MMC_RSP_R6;
  1060. err = mmc_send_cmd(mmc, &cmd, NULL);
  1061. if (err)
  1062. return err;
  1063. if (IS_SD(mmc))
  1064. mmc->rca = (cmd.response[0] >> 16) & 0xffff;
  1065. }
  1066. /* Get the Card-Specific Data */
  1067. cmd.cmdidx = MMC_CMD_SEND_CSD;
  1068. cmd.resp_type = MMC_RSP_R2;
  1069. cmd.cmdarg = mmc->rca << 16;
  1070. err = mmc_send_cmd(mmc, &cmd, NULL);
  1071. if (err)
  1072. return err;
  1073. mmc->csd[0] = cmd.response[0];
  1074. mmc->csd[1] = cmd.response[1];
  1075. mmc->csd[2] = cmd.response[2];
  1076. mmc->csd[3] = cmd.response[3];
  1077. if (mmc->version == MMC_VERSION_UNKNOWN) {
  1078. int version = (cmd.response[0] >> 26) & 0xf;
  1079. switch (version) {
  1080. case 0:
  1081. mmc->version = MMC_VERSION_1_2;
  1082. break;
  1083. case 1:
  1084. mmc->version = MMC_VERSION_1_4;
  1085. break;
  1086. case 2:
  1087. mmc->version = MMC_VERSION_2_2;
  1088. break;
  1089. case 3:
  1090. mmc->version = MMC_VERSION_3;
  1091. break;
  1092. case 4:
  1093. mmc->version = MMC_VERSION_4;
  1094. break;
  1095. default:
  1096. mmc->version = MMC_VERSION_1_2;
  1097. break;
  1098. }
  1099. }
  1100. /* divide frequency by 10, since the mults are 10x bigger */
  1101. freq = fbase[(cmd.response[0] & 0x7)];
  1102. mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
  1103. mmc->legacy_speed = freq * mult;
  1104. mmc_select_mode(mmc, MMC_LEGACY);
  1105. mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
  1106. mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
  1107. if (IS_SD(mmc))
  1108. mmc->write_bl_len = mmc->read_bl_len;
  1109. else
  1110. mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
  1111. if (mmc->high_capacity) {
  1112. csize = (mmc->csd[1] & 0x3f) << 16
  1113. | (mmc->csd[2] & 0xffff0000) >> 16;
  1114. cmult = 8;
  1115. } else {
  1116. csize = (mmc->csd[1] & 0x3ff) << 2
  1117. | (mmc->csd[2] & 0xc0000000) >> 30;
  1118. cmult = (mmc->csd[2] & 0x00038000) >> 15;
  1119. }
  1120. mmc->capacity_user = (csize + 1) << (cmult + 2);
  1121. mmc->capacity_user *= mmc->read_bl_len;
  1122. //printf("mmc->capacity_user = %d\r\n", mmc->capacity_user);
  1123. mmc->capacity_boot = 0;
  1124. mmc->capacity_rpmb = 0;
  1125. for (i = 0; i < 4; i++)
  1126. mmc->capacity_gp[i] = 0;
  1127. if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
  1128. mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
  1129. if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
  1130. mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
  1131. if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
  1132. cmd.cmdidx = MMC_CMD_SET_DSR;
  1133. cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
  1134. cmd.resp_type = MMC_RSP_NONE;
  1135. if (mmc_send_cmd(mmc, &cmd, NULL))
  1136. rlSendString("MMC: SET_DSR failed\r\n");
  1137. }
  1138. /* Select the card, and put it into Transfer Mode */
  1139. if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
  1140. cmd.cmdidx = MMC_CMD_SELECT_CARD;
  1141. cmd.resp_type = MMC_RSP_R1;
  1142. cmd.cmdarg = mmc->rca << 16;
  1143. err = mmc_send_cmd(mmc, &cmd, NULL);
  1144. if (err)
  1145. return err;
  1146. }
  1147. /*
  1148. * For SD, its erase group is always one sector
  1149. */
  1150. mmc->erase_grp_size = 1;
  1151. mmc->part_config = MMCPART_NOAVAILABLE;
  1152. err = mmc_startup_v4(mmc);
  1153. if (err)
  1154. return err;
  1155. err = mmc_set_capacity(mmc, mmc->block_dev.hwpart);
  1156. if (err)
  1157. return err;
  1158. if (IS_SD(mmc)) {
  1159. err = sd_get_capabilities(mmc);
  1160. if (err)
  1161. return err;
  1162. err = sd_select_mode_and_width(mmc, mmc->card_caps);
  1163. } else {
  1164. err = mmc_get_capabilities(mmc);
  1165. if (err)
  1166. return err;
  1167. mmc_select_mode_and_width(mmc, mmc->card_caps);
  1168. }
  1169. if (err)
  1170. return err;
  1171. mmc->best_mode = mmc->selected_mode;
  1172. /* Fix the block length for DDR mode */
  1173. if (mmc->ddr_mode) {
  1174. mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
  1175. mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
  1176. }
  1177. /* fill in device description */
  1178. mmc->block_dev.lun = 0;
  1179. mmc->block_dev.hwpart = 0;
  1180. mmc->block_dev.type = 0;
  1181. mmc->block_dev.blksz = mmc->read_bl_len;
  1182. mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz);
  1183. mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
  1184. mmc->block_dev.vendor[0] = 0;
  1185. mmc->block_dev.product[0] = 0;
  1186. mmc->block_dev.revision[0] = 0;
  1187. return 0;
  1188. }
  1189. static int mmc_send_if_cond(struct mmc *mmc)
  1190. {
  1191. struct mmc_cmd cmd;
  1192. int err;
  1193. cmd.cmdidx = SD_CMD_SEND_IF_COND;
  1194. /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
  1195. cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
  1196. cmd.resp_type = MMC_RSP_R7;
  1197. err = mmc_send_cmd(mmc, &cmd, NULL);
  1198. if (err)
  1199. return err;
  1200. if ((cmd.response[0] & 0xff) != 0xaa)
  1201. return -EOPNOTSUPP;
  1202. else
  1203. mmc->version = SD_VERSION_2;
  1204. return 0;
  1205. }
  1206. struct mmc *mmc_create(const struct mmc_config *cfg, void *priv, u32 dev_num)
  1207. {
  1208. struct mmc *mmc;
  1209. if(dev_num != 0)
  1210. return NULL;
  1211. mmc = &local_mmc0;
  1212. /* quick validation */
  1213. if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL ||
  1214. cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0)
  1215. return NULL;
  1216. mmc->cfg = cfg;
  1217. mmc->priv = priv;
  1218. /* the following chunk was mmc_register() */
  1219. /* Setup dsr related values */
  1220. mmc->dsr_imp = 0;
  1221. mmc->dsr = 0xffffffff;
  1222. /* Setup the universal parts of the block interface just once */
  1223. mmc->block_dev.if_type = IF_TYPE_MMC;
  1224. mmc->block_dev.dev = cur_dev_num++;
  1225. mmc->block_dev.removable = 1;
  1226. mmc->block_dev.block_read = mmc_bread;
  1227. mmc->block_dev.block_write = mmc_bwrite;
  1228. mmc->block_dev.block_erase = mmc_berase;
  1229. /* setup initial part type */
  1230. mmc->block_dev.part_type = mmc->cfg->part_type;
  1231. return mmc;
  1232. }
  1233. static int mmc_power_init(struct mmc *mmc)
  1234. {
  1235. return 0;
  1236. }
  1237. /*
  1238. * put the host in the initial state:
  1239. * - turn on Vdd (card power supply)
  1240. * - configure the bus width and clock to minimal values
  1241. */
  1242. static void mmc_set_initial_state(struct mmc *mmc)
  1243. {
  1244. mmc_select_mode(mmc, MMC_LEGACY);
  1245. mmc_set_bus_width(mmc, 1);
  1246. mmc_set_clock(mmc, 0, MMC_CLK_ENABLE);
  1247. }
  1248. static int mmc_power_on(struct mmc *mmc)
  1249. {
  1250. return 0;
  1251. }
  1252. static int mmc_power_off(struct mmc *mmc)
  1253. {
  1254. mmc_set_clock(mmc, 0, MMC_CLK_DISABLE);
  1255. return 0;
  1256. }
  1257. static int mmc_power_cycle(struct mmc *mmc)
  1258. {
  1259. int ret;
  1260. ret = mmc_power_off(mmc);
  1261. if (ret)
  1262. return ret;
  1263. /*
  1264. * SD spec recommends at least 1ms of delay. Let's wait for 2ms
  1265. * to be on the safer side.
  1266. */
  1267. udelay(2000);
  1268. return mmc_power_on(mmc);
  1269. }
  1270. int mmc_get_op_cond(struct mmc *mmc)
  1271. {
  1272. bool uhs_en = supports_uhs(mmc->cfg->host_caps);
  1273. int err;
  1274. if (mmc->has_init)
  1275. return 0;
  1276. err = mmc_power_init(mmc);
  1277. if (err)
  1278. return err;
  1279. err = mmc_power_cycle(mmc);
  1280. if (err) {
  1281. /*
  1282. * if power cycling is not supported, we should not try
  1283. * to use the UHS modes, because we wouldn't be able to
  1284. * recover from an error during the UHS initialization.
  1285. */
  1286. printk("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
  1287. uhs_en = false;
  1288. mmc->host_caps &= ~UHS_CAPS;
  1289. err = mmc_power_on(mmc);
  1290. }
  1291. if (err)
  1292. return err;
  1293. /* made sure it's not NULL earlier */
  1294. err = mmc->cfg->ops->init(mmc);
  1295. if (err)
  1296. return err;
  1297. mmc->ddr_mode = 0;
  1298. retry:
  1299. mmc_set_initial_state(mmc);
  1300. /* Reset the Card */
  1301. err = mmc_go_idle(mmc);
  1302. if (err)
  1303. return err;
  1304. /* The internal partition reset to user partition(0) at every CMD0*/
  1305. mmc->block_dev.hwpart = 0;
  1306. /* Test for SD version 2 */
  1307. err = mmc_send_if_cond(mmc);
  1308. /* Now try to get the SD card's operating condition */
  1309. err = sd_send_op_cond(mmc, uhs_en);
  1310. if (err && uhs_en) {
  1311. uhs_en = false;
  1312. mmc_power_cycle(mmc);
  1313. goto retry;
  1314. }
  1315. /* If the command timed out, we check for an MMC card */
  1316. if (err == -ETIMEDOUT) {
  1317. err = mmc_send_op_cond(mmc);
  1318. if (err) {
  1319. printk("Card did not respond to voltage select!\n");
  1320. return -EOPNOTSUPP;
  1321. }
  1322. }
  1323. return err;
  1324. }
  1325. int mmc_start_init(struct mmc *mmc)
  1326. {
  1327. int err = 0;
  1328. /*
  1329. * all hosts are capable of 1 bit bus-width and able to use the legacy
  1330. * timings.
  1331. */
  1332. mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(SD_LEGACY) |
  1333. MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
  1334. err = mmc_get_op_cond(mmc);
  1335. if (!err)
  1336. mmc->init_in_progress = 1;
  1337. return err;
  1338. }
  1339. #if 0
  1340. static void print_mmcinfo(struct mmc *mmc)
  1341. {
  1342. int i;
  1343. printk("Device: %s\r\n", mmc->cfg->name);
  1344. printk("Manufacturer ID: %x\r\n", mmc->cid[0] >> 24);
  1345. printk("OEM: %x\r\n", (mmc->cid[0] >> 8) & 0xffff);
  1346. printk("Name: %c%c%c%c%c \r\n", mmc->cid[0] & 0xff,
  1347. (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
  1348. (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff);
  1349. printk("Tran Speed: %d\r\n", mmc->tran_speed);
  1350. printk("Rd Block Len: %d\r\n", mmc->read_bl_len);
  1351. printk("%s version %d.%d", IS_SD(mmc) ? "SD" : "MMC",
  1352. EXTRACT_SDMMC_MAJOR_VERSION(mmc->version),
  1353. EXTRACT_SDMMC_MINOR_VERSION(mmc->version));
  1354. if (EXTRACT_SDMMC_CHANGE_VERSION(mmc->version) != 0)
  1355. printk(".%d", EXTRACT_SDMMC_CHANGE_VERSION(mmc->version));
  1356. printk("\r\n");
  1357. printk("High Capacity: %s\r\n", mmc->high_capacity ? "Yes" : "No");
  1358. printk("Capacity: ");
  1359. print_size(mmc->capacity, "\r\n");
  1360. printk("Bus Width: %d-bit%s\r\n", mmc->bus_width,
  1361. mmc->ddr_mode ? " DDR" : "");
  1362. printk("Erase Group Size: 0x%x\r\n", ((u64)mmc->erase_grp_size) << 9);
  1363. //printf(((u64)mmc->erase_grp_size) << 9, "\r\n");
  1364. if (!IS_SD(mmc) && mmc->version >= MMC_VERSION_4_41) {
  1365. int has_enh = (mmc->part_support & ENHNCD_SUPPORT) != 0;
  1366. int usr_enh = has_enh && (mmc->part_attr & EXT_CSD_ENH_USR);
  1367. printk("HC WP Group Size: ");
  1368. printk(((u64)mmc->hc_wp_grp_size) << 9, "\n");
  1369. printk("User Capacity: ");
  1370. printk(mmc->capacity_user, usr_enh ? " ENH" : "");
  1371. if (mmc->wr_rel_set & EXT_CSD_WR_DATA_REL_USR)
  1372. printk(" WRREL\n");
  1373. else
  1374. printk('\n');
  1375. if (usr_enh) {
  1376. printk("User Enhanced Start: ");
  1377. printk(mmc->enh_user_start, "\r\n");
  1378. printk("User Enhanced Size: ");
  1379. printk(mmc->enh_user_size, "\r\n");
  1380. }
  1381. printk("Boot Capacity: ");
  1382. printk(mmc->capacity_boot, has_enh ? " ENH\r\n" : "\r\n");
  1383. printk("RPMB Capacity: ");
  1384. printk(mmc->capacity_rpmb, has_enh ? " ENH\r\n" : "\r\n");
  1385. for (i = 0; i < ARRAY_SIZE(mmc->capacity_gp); i++) {
  1386. int is_enh = has_enh &&
  1387. (mmc->part_attr & EXT_CSD_ENH_GP(i));
  1388. if (mmc->capacity_gp[i]) {
  1389. printk("GP%i Capacity: ", i+1);
  1390. printk(mmc->capacity_gp[i],
  1391. is_enh ? " ENH" : "");
  1392. if (mmc->wr_rel_set & EXT_CSD_WR_DATA_REL_GP(i))
  1393. printk(" WRREL\r\n");
  1394. else
  1395. printk("\r\n");
  1396. }
  1397. }
  1398. }
  1399. }
  1400. #endif
  1401. static int mmc_complete_init(struct mmc *mmc)
  1402. {
  1403. int err = 0;
  1404. mmc->init_in_progress = 0;
  1405. if (mmc->op_cond_pending)
  1406. err = mmc_complete_op_cond(mmc);
  1407. if (!err)
  1408. err = mmc_startup(mmc);
  1409. if (err)
  1410. mmc->has_init = 0;
  1411. else
  1412. mmc->has_init = 1;
  1413. // print_mmcinfo(mmc);
  1414. return err;
  1415. }
  1416. int mmc_init(struct mmc *mmc)
  1417. {
  1418. int err = 0;
  1419. if (mmc->has_init)
  1420. return 0;
  1421. //start = get_timer(0);
  1422. if (!mmc->init_in_progress)
  1423. err = mmc_start_init(mmc);
  1424. if (!err)
  1425. err = mmc_complete_init(mmc);
  1426. return err;
  1427. }
  1428. int mmc_set_dsr(struct mmc *mmc, u16 val)
  1429. {
  1430. mmc->dsr = val;
  1431. return 0;
  1432. }