dwmmc.h 5.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207
  1. /*
  2. * (C) Copyright 2012 SAMSUNG Electronics
  3. * Jaehoon Chung <jh80.chung@samsung.com>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #ifndef __DWMMC_HW_H
  8. #define __DWMMC_HW_H
  9. //#include <asm/io.h>
  10. #include <comdef.h>
  11. #include <mmc.h>
  12. #define DWMCI_CTRL 0x000
  13. #define DWMCI_PWREN 0x004
  14. #define DWMCI_CLKDIV 0x008
  15. #define DWMCI_CLKSRC 0x00C
  16. #define DWMCI_CLKENA 0x010
  17. #define DWMCI_TMOUT 0x014
  18. #define DWMCI_CTYPE 0x018
  19. #define DWMCI_BLKSIZ 0x01C
  20. #define DWMCI_BYTCNT 0x020
  21. #define DWMCI_INTMASK 0x024
  22. #define DWMCI_CMDARG 0x028
  23. #define DWMCI_CMD 0x02C
  24. #define DWMCI_RESP0 0x030
  25. #define DWMCI_RESP1 0x034
  26. #define DWMCI_RESP2 0x038
  27. #define DWMCI_RESP3 0x03C
  28. #define DWMCI_MINTSTS 0x040
  29. #define DWMCI_RINTSTS 0x044
  30. #define DWMCI_STATUS 0x048
  31. #define DWMCI_FIFOTH 0x04C
  32. #define DWMCI_CDETECT 0x050
  33. #define DWMCI_WRTPRT 0x054
  34. #define DWMCI_GPIO 0x058
  35. #define DWMCI_TCMCNT 0x05C
  36. #define DWMCI_TBBCNT 0x060
  37. #define DWMCI_DEBNCE 0x064
  38. #define DWMCI_USRID 0x068
  39. #define DWMCI_VERID 0x06C
  40. #define DWMCI_HCON 0x070
  41. #define DWMCI_UHS_REG 0x074
  42. #define DWMCI_BMOD 0x080
  43. #define DWMCI_PLDMND 0x084
  44. #define DWMCI_DBADDR 0x088
  45. #define DWMCI_IDSTS 0x08C
  46. #define DWMCI_IDINTEN 0x090
  47. #define DWMCI_DSCADDR 0x094
  48. #define DWMCI_BUFADDR 0x098
  49. #define DWMCI_DATA 0x200
  50. /* Interrupt Mask register */
  51. #define DWMCI_INTMSK_ALL 0xffffffff
  52. #define DWMCI_INTMSK_RE (1 << 1)
  53. #define DWMCI_INTMSK_CDONE (1 << 2)
  54. #define DWMCI_INTMSK_DTO (1 << 3)
  55. #define DWMCI_INTMSK_TXDR (1 << 4)
  56. #define DWMCI_INTMSK_RXDR (1 << 5)
  57. #define DWMCI_INTMSK_DCRC (1 << 7)
  58. #define DWMCI_INTMSK_RTO (1 << 8)
  59. #define DWMCI_INTMSK_DRTO (1 << 9)
  60. #define DWMCI_INTMSK_HTO (1 << 10)
  61. #define DWMCI_INTMSK_FRUN (1 << 11)
  62. #define DWMCI_INTMSK_HLE (1 << 12)
  63. #define DWMCI_INTMSK_SBE (1 << 13)
  64. #define DWMCI_INTMSK_ACD (1 << 14)
  65. #define DWMCI_INTMSK_EBE (1 << 15)
  66. /* Raw interrupt Regsiter */
  67. #define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\
  68. DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC)
  69. #define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO)
  70. /* CTRL register */
  71. #define DWMCI_CTRL_RESET (1 << 0)
  72. #define DWMCI_CTRL_FIFO_RESET (1 << 1)
  73. #define DWMCI_CTRL_DMA_RESET (1 << 2)
  74. #define DWMCI_DMA_EN (1 << 5)
  75. #define DWMCI_CTRL_SEND_AS_CCSD (1 << 10)
  76. #define DWMCI_IDMAC_EN (1 << 25)
  77. #define DWMCI_RESET_ALL (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\
  78. DWMCI_CTRL_DMA_RESET)
  79. /* CMD register */
  80. #define DWMCI_CMD_RESP_EXP (1 << 6)
  81. #define DWMCI_CMD_RESP_LENGTH (1 << 7)
  82. #define DWMCI_CMD_CHECK_CRC (1 << 8)
  83. #define DWMCI_CMD_DATA_EXP (1 << 9)
  84. #define DWMCI_CMD_RW (1 << 10)
  85. #define DWMCI_CMD_SEND_STOP (1 << 12)
  86. #define DWMCI_CMD_ABORT_STOP (1 << 14)
  87. #define DWMCI_CMD_PRV_DAT_WAIT (1 << 13)
  88. #define DWMCI_CMD_UPD_CLK (1 << 21)
  89. #define DWMCI_CMD_USE_HOLD_REG (1 << 29)
  90. #define DWMCI_CMD_START (1 << 31)
  91. /* CLKENA register */
  92. #define DWMCI_CLKEN_ENABLE (1 << 0)
  93. #define DWMCI_CLKEN_LOW_PWR (1 << 16)
  94. /* Card-type registe */
  95. #define DWMCI_CTYPE_1BIT 0
  96. #define DWMCI_CTYPE_4BIT (1 << 0)
  97. #define DWMCI_CTYPE_8BIT (1 << 16)
  98. /* Status Register */
  99. #define DWMCI_BUSY (1 << 9)
  100. #define DWMCI_FIFO_MASK 0x1ff
  101. #define DWMCI_FIFO_SHIFT 17
  102. /* FIFOTH Register */
  103. #define MSIZE(x) ((x) << 28)
  104. #define RX_WMARK(x) ((x) << 16)
  105. #define TX_WMARK(x) (x)
  106. #define RX_WMARK_SHIFT 16
  107. #define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT)
  108. #define DWMCI_IDMAC_OWN (1 << 31)
  109. #define DWMCI_IDMAC_CH (1 << 4)
  110. #define DWMCI_IDMAC_FS (1 << 3)
  111. #define DWMCI_IDMAC_LD (1 << 2)
  112. /* Bus Mode Register */
  113. #define DWMCI_BMOD_IDMAC_RESET (1 << 0)
  114. #define DWMCI_BMOD_IDMAC_FB (1 << 1)
  115. #define DWMCI_BMOD_IDMAC_EN (1 << 7)
  116. /* UHS register */
  117. #define DWMCI_DDR_MODE (1 << 16)
  118. /* quirks */
  119. #define DWMCI_QUIRK_DISABLE_SMU (1 << 0)
  120. /**
  121. * struct dwmci_host - Information about a designware MMC host
  122. *
  123. * @name: Device name
  124. * @ioaddr: Base I/O address of controller
  125. * @quirks: Quick flags - see DWMCI_QUIRK_...
  126. * @caps: Capabilities - see MMC_MODE_...
  127. * @bus_hz: Bus speed in Hz, if @get_mmc_clk() is NULL
  128. * @div: Arbitrary clock divider value for use by controller
  129. * @dev_index: Arbitrary device index for use by controller
  130. * @dev_id: Arbitrary device ID for use by controller
  131. * @buswidth: Bus width in bits (8 or 4)
  132. * @fifoth_val: Value for FIFOTH register (or 0 to leave unset)
  133. * @mmc: Pointer to generic MMC structure for this device
  134. * @priv: Private pointer for use by controller
  135. */
  136. struct dwmci_host {
  137. const char *name;
  138. void *ioaddr;
  139. unsigned int quirks;
  140. unsigned int caps;
  141. unsigned int version;
  142. unsigned int clock;
  143. unsigned int bus_hz;
  144. unsigned int div;
  145. int dev_index;
  146. int dev_id;
  147. int buswidth;
  148. u32 fifoth_val;
  149. struct mmc *mmc;
  150. void *priv;
  151. void (*clksel)(struct dwmci_host *host);
  152. void (*board_init)(struct dwmci_host *host);
  153. /**
  154. * Get / set a particular MMC clock frequency
  155. *
  156. * This is used to request the current clock frequency of the clock
  157. * that drives the DWMMC peripheral. The caller will then use this
  158. * information to work out the divider it needs to achieve the
  159. * required MMC bus clock frequency. If you want to handle the
  160. * clock external to DWMMC, use @freq to select the frequency and
  161. * return that value too. Then DWMMC will put itself in bypass mode.
  162. *
  163. * @host: DWMMC host
  164. * @freq: Frequency the host is trying to achieve
  165. */
  166. unsigned int (*get_mmc_clk)(struct dwmci_host *host, u32 freq);
  167. struct mmc_config cfg;
  168. /* use fifo mode to read and write data */
  169. unsigned int fifo_mode;
  170. };
  171. struct dwmci_idmac {
  172. u32 flags;
  173. u32 cnt;
  174. u32 addr;
  175. u32 next_addr;
  176. };
  177. static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val)
  178. {
  179. writel(val, host->ioaddr + reg);
  180. }
  181. static inline u32 dwmci_readl(struct dwmci_host *host, int reg)
  182. {
  183. return readl(host->ioaddr + reg);
  184. }
  185. int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk,u32 dev_num);
  186. #endif /* __DWMMC_HW_H */