gpio.c 2.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /**
  3. ******************************************************************************
  4. * @file gpio.c
  5. * @author StarFive Technology
  6. * @version V1.0
  7. * @date 08/13/2020
  8. * @brief
  9. ******************************************************************************
  10. * @copy
  11. *
  12. * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  13. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  14. * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
  15. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  16. * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  17. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  18. *
  19. * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
  20. */
  21. #include "gpio.h"
  22. #include <sys.h>
  23. //#include <ezGPIO_fullMux_ctrl_macro.h>
  24. #include <clkgen_ctrl_macro.h>
  25. #include <rstgen_ctrl_macro.h>
  26. #define GPIO_EN (0x0)
  27. #define GPIO_IS_LOW (0x10) //select level or edge trigge
  28. #define GPIO_IS_HIGH (0x14)
  29. #define GPIO_IBE_LOW (0x18) //interrupt both edge trigger 1:both, 0:disable both
  30. #define GPIO_IBE_HIGH (0x1c)
  31. #define GPIO_IEV_LOW (0x20) //trigger condition 1:rising, 0 falling
  32. #define GPIO_IEV_HIGH (0x24)
  33. #define GPIO_IE_LOW (0x28) //interrupt enable
  34. #define GPIO_IE_HIGH (0x2c)
  35. #define GPIO_IC_LOW (0x30) //interrupt clear
  36. #define GPIO_IC_HIGH (0x34)
  37. //read only
  38. #define GPIO_RIS_LOW (0x38) //raw interrupt
  39. #define GPIO_RIS_HIGH (0x3c)
  40. #define GPIO_MIS_LOW (0x40) //masked interrupt
  41. #define GPIO_MIS_HIGH (0x44)
  42. #define GPIO_DIN_LOW (0x48) //data in
  43. #define GPIO_DIN_HIGH (0x4c)
  44. static inline void gpio_write_reg(unsigned long base, unsigned long addr, unsigned int val)
  45. {
  46. writel(val, (volatile void *)(base + addr));
  47. }
  48. static inline unsigned int gpio_read_reg(unsigned long base, unsigned long addr)
  49. {
  50. return readl((volatile void *)(base + addr));
  51. }
  52. void gpio_enable(int enable)
  53. {
  54. if(enable == 0)
  55. gpio_write_reg(EZGPIO_FULLMUX_BASE_ADDR, GPIO_EN, 0);
  56. else
  57. gpio_write_reg(EZGPIO_FULLMUX_BASE_ADDR, GPIO_EN, 1);
  58. }
  59. int gpio_get_val(int gpio_num)
  60. {
  61. int value = 0;
  62. if(gpio_num < 32)
  63. {
  64. value = gpio_read_reg(EZGPIO_FULLMUX_BASE_ADDR, GPIO_DIN_LOW);
  65. return (value >> gpio_num) & 0x1;
  66. }
  67. else
  68. {
  69. value = gpio_read_reg(EZGPIO_FULLMUX_BASE_ADDR, GPIO_DIN_HIGH);
  70. return (value >> (gpio_num - 32)) & 0x1;
  71. }
  72. }
  73. int get_boot_mode()
  74. {
  75. int boot_mode = 0;
  76. boot_mode = gpio_get_val(BOOT_GPIO_60);
  77. boot_mode |= (gpio_get_val(BOOT_GPIO_61) << 1);
  78. boot_mode |= (gpio_get_val(BOOT_GPIO_62) << 2);
  79. return boot_mode;
  80. }
  81. void gpio_init(void)
  82. {
  83. _ENABLE_CLOCK_clk_gpio_apb_;
  84. _ASSERT_RESET_rstgen_rstn_gpio_apb_;
  85. _CLEAR_RESET_rstgen_rstn_gpio_apb_;
  86. gpio_enable(1);
  87. }