orbit_boot_training.v 13 KB

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  1. // void inline orbit_writel(volatile void __iomem *addr, uint32_t data);
  2. // void inline orbit_readl_poll(volatile void __iomem *addr, uint32_t expected, uint32_t strobe);
  3. // void orbit_nsleep(int ns); // Sleep ns nano-seconds
  4. // void orbit_usleep(int us); // Sleep us micro-seconds
  5. //cdns_phy_initialize(1);
  6. apb_write(OMC_APB_BASE_ADDR + 32'h0, 32'h00000401);
  7. apb_write(OMC_SECURE_APB_BASE_ADDR + 32'hf00, 32'h40001030);
  8. apb_write(OMC_SECURE_APB_BASE_ADDR + 32'hf04, 32'h00000001);
  9. apb_write(OMC_SECURE_APB_BASE_ADDR + 32'hf10, 32'h00800000);//region0_start //32'h00800000
  10. apb_write(OMC_SECURE_APB_BASE_ADDR + 32'hf14, 32'h027fffff);//region0_end,SOC addr shift right 8bits //0x01ffffff
  11. apb_write(OMC_SECURE_APB_BASE_ADDR + 32'hf18, 32'h00000001);
  12. apb_write(OMC_SECURE_APB_BASE_ADDR + 32'hf30, 32'h0f000031);
  13. apb_write(OMC_SECURE_APB_BASE_ADDR + 32'hf34, 32'h0f000031);
  14. apb_write(OMC_SECURE_APB_BASE_ADDR + 32'h110, 32'hc0000001);
  15. apb_write(OMC_SECURE_APB_BASE_ADDR + 32'h114, 32'hffffffff);
  16. apb_write(OMC_APB_BASE_ADDR + 32'h10c, 32'h00000505);
  17. apb_write(OMC_APB_BASE_ADDR + 32'h11c, 32'h00000000);
  18. apb_write(OMC_APB_BASE_ADDR + 32'h500, 32'h00000201);
  19. apb_write(OMC_APB_BASE_ADDR + 32'h514, 32'h00000100);
  20. apb_write(OMC_APB_BASE_ADDR + 32'h6a8, 32'h00040000);
  21. apb_write(OMC_APB_BASE_ADDR + 32'hea8, 32'h00040000);
  22. // Memory frequency should be changed below 50MHz somewhere before here
  23. apb_write(OMC_APB_BASE_ADDR + 32'h504, 32'h40000000);
  24. //cdns_dll_rst_deassert()
  25. apb_read(OMC_APB_BASE_ADDR + 32'h504, tmp);
  26. while((tmp & 32'h80000000) != 32'h80000000) begin
  27. orbit_usleep(1);
  28. apb_read(OMC_APB_BASE_ADDR + 32'h504, tmp);
  29. end
  30. apb_write(OMC_APB_BASE_ADDR + 32'h504, 32'h00000000);
  31. // tINIT0 is controlled by System
  32. apb_write(OMC_APB_BASE_ADDR + 32'h50c, 32'h00000000);
  33. // Waits tINIT1 (200 us): Minimum RESET_n LOW time after completion of voltage ramp
  34. orbit_usleep(200);
  35. apb_write(OMC_APB_BASE_ADDR + 32'h50c, 32'h00000001);
  36. // Waits tINIT3 (2 ms): Minimum CKE low time after RESET_n high
  37. orbit_usleep(2000);
  38. // Drive CKE high
  39. apb_write(OMC_APB_BASE_ADDR + 32'h10, 32'h0000003c);
  40. apb_write(OMC_APB_BASE_ADDR + 32'h14, 32'h00000001);
  41. // Waits tINIT5 (2 us): Minimum idle time before first MRW/MRR command
  42. orbit_usleep(2);
  43. apb_write(OMC_APB_BASE_ADDR + 32'h10, 32'h00000010);
  44. apb_write(OMC_APB_BASE_ADDR + 32'h14, 32'h00000001);
  45. // Waits tZQCAL (1 us)
  46. orbit_usleep(1);
  47. apb_write(OMC_APB_BASE_ADDR + 32'h10, 32'h00000011);
  48. apb_write(OMC_APB_BASE_ADDR + 32'h14, 32'h00000001);
  49. apb_write(OMC_APB_BASE_ADDR + 32'h10, 32'h00000020);
  50. apb_write(OMC_APB_BASE_ADDR + 32'h14, 32'h00000001);
  51. // Waits tZQCAL (1 us)
  52. orbit_usleep(1);
  53. apb_write(OMC_APB_BASE_ADDR + 32'h10, 32'h00000021);
  54. apb_write(OMC_APB_BASE_ADDR + 32'h14, 32'h00000001);
  55. apb_write(OMC_APB_BASE_ADDR + 32'h310, 32'h00020000);
  56. apb_write(OMC_APB_BASE_ADDR + 32'h310, 32'h00020001);
  57. // Write down RCLK-related CRs
  58. apb_write(OMC_APB_BASE_ADDR + 32'h600, 32'h002e0176);
  59. apb_write(OMC_APB_BASE_ADDR + 32'h604, 32'h002e0176);
  60. apb_write(OMC_APB_BASE_ADDR + 32'h608, 32'h001700bb);
  61. apb_write(OMC_APB_BASE_ADDR + 32'h60c, 32'h000b005d);
  62. apb_write(OMC_APB_BASE_ADDR + 32'h610, 32'h0005002e);
  63. apb_write(OMC_APB_BASE_ADDR + 32'h614, 32'h00020017);
  64. apb_write(OMC_APB_BASE_ADDR + 32'h618, 32'h00020017);
  65. apb_write(OMC_APB_BASE_ADDR + 32'h61c, 32'h00020017);
  66. apb_write(OMC_APB_BASE_ADDR + 32'h678, 32'h00000019);
  67. apb_write(OMC_APB_BASE_ADDR + 32'h100, 32'h000000fc);
  68. apb_write(OMC_APB_BASE_ADDR + 32'h620, 32'h03030404);
  69. apb_write(OMC_APB_BASE_ADDR + 32'h624, 32'h04030505);
  70. apb_write(OMC_APB_BASE_ADDR + 32'h628, 32'h07030884);
  71. apb_write(OMC_APB_BASE_ADDR + 32'h62c, 32'h13150401);
  72. apb_write(OMC_APB_BASE_ADDR + 32'h630, 32'h17150604);
  73. apb_write(OMC_APB_BASE_ADDR + 32'h634, 32'h000d0000);
  74. apb_write(OMC_APB_BASE_ADDR + 32'h638, 32'h200a0a08);
  75. apb_write(OMC_APB_BASE_ADDR + 32'h63c, 32'h17300803);
  76. apb_write(OMC_APB_BASE_ADDR + 32'h640, 32'h00060c00);
  77. apb_write(OMC_APB_BASE_ADDR + 32'h644, 32'ha0030006);
  78. apb_write(OMC_APB_BASE_ADDR + 32'h648, 32'h00000000);
  79. apb_write(OMC_APB_BASE_ADDR + 32'h64c, 32'h00081306);
  80. apb_write(OMC_APB_BASE_ADDR + 32'h650, 32'h04070304);
  81. apb_write(OMC_APB_BASE_ADDR + 32'h654, 32'h00000404);
  82. apb_write(OMC_APB_BASE_ADDR + 32'h658, 32'h00000060);
  83. apb_write(OMC_APB_BASE_ADDR + 32'h65c, 32'h00020008);
  84. apb_write(OMC_APB_BASE_ADDR + 32'h660, 32'h00000000);
  85. apb_write(OMC_APB_BASE_ADDR + 32'h680, 32'h00000400);
  86. apb_write(OMC_APB_BASE_ADDR + 32'h684, 32'h02000202);
  87. apb_write(OMC_APB_BASE_ADDR + 32'h688, 32'h04130409);
  88. apb_write(OMC_APB_BASE_ADDR + 32'h68c, 32'h20002420);
  89. apb_write(OMC_APB_BASE_ADDR + 32'h690, 32'h00140000);
  90. apb_write(OMC_APB_BASE_ADDR + 32'h69c, 32'h01240074);
  91. apb_write(OMC_APB_BASE_ADDR + 32'h6a0, 32'h00000000);
  92. apb_write(OMC_APB_BASE_ADDR + 32'h6a4, 32'h20240c00);
  93. apb_write(OMC_APB_BASE_ADDR + 32'h6a8, 32'h00040000);
  94. apb_write(OMC_APB_BASE_ADDR + 32'h4, 32'h30010006);
  95. apb_write(OMC_APB_BASE_ADDR + 32'hc, 32'h00000002);
  96. apb_write(OMC_APB_BASE_ADDR + 32'h4, 32'h30020000);
  97. apb_write(OMC_APB_BASE_ADDR + 32'hc, 32'h00000002);
  98. apb_write(OMC_APB_BASE_ADDR + 32'h4, 32'h30030031);
  99. apb_write(OMC_APB_BASE_ADDR + 32'hc, 32'h00000002);
  100. apb_write(OMC_APB_BASE_ADDR + 32'h4, 32'h30160006);
  101. apb_write(OMC_APB_BASE_ADDR + 32'hc, 32'h00000002);
  102. apb_write(OMC_APB_BASE_ADDR + 32'h514, 32'h00000000);
  103. apb_read(OMC_APB_BASE_ADDR + 32'h518, tmp);
  104. while((tmp & 32'h00000002) != 32'h00000002) begin
  105. orbit_usleep(1);
  106. apb_read(OMC_APB_BASE_ADDR + 32'h518, tmp);
  107. end
  108. apb_read(OMC_APB_BASE_ADDR + 32'h518, tmp);
  109. while((tmp & 32'h00000002) != 32'h00000000) begin
  110. orbit_usleep(1);
  111. apb_read(OMC_APB_BASE_ADDR + 32'h518, tmp);
  112. end
  113. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd11 <<2), tmp);//`DENALI_PI_11_DATA
  114. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd11 <<2), 32'h03000803);
  115. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd83 <<2), tmp);//`DENALI_PI_83_DATA
  116. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd84 <<2), tmp);//`DENALI_PI_84_DATA
  117. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd84 <<2), 32'h00000000);
  118. //cdns_pi_end( 3);
  119. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd46 <<2), tmp);//`DENALI_PI_46_DATA
  120. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd46 <<2), 32'h030f0000);
  121. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd33 <<2), tmp);//`DENALI_PI_33_DATA
  122. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd33 <<2), 32'h00000000);
  123. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd44 <<2), tmp);//`DENALI_PI_44_DATA
  124. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd44 <<2), 32'h01000000);
  125. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd44 <<2), tmp);//`DENALI_PI_44_DATA
  126. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd44 <<2), 32'h00000000);
  127. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd45 <<2), tmp);//`DENALI_PI_45_DATA
  128. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd45 <<2), 32'h00000001);
  129. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd146 <<2), tmp);//`DENALI_PI_146_DATA
  130. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd146 <<2), 32'h03011808);
  131. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd147 <<2), tmp);//`DENALI_PI_147_DATA
  132. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd147 <<2), 32'h01010301);
  133. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd147 <<2), tmp);//`DENALI_PI_147_DATA
  134. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd147 <<2), 32'h03010301);
  135. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd44 <<2), tmp);//`DENALI_PI_44_DATA
  136. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd44 <<2), 32'h00000100);
  137. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd46 <<2), tmp);//`DENALI_PI_46_DATA
  138. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd46 <<2), 32'h03030000);
  139. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd33 <<2), tmp);//`DENALI_PI_33_DATA
  140. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd33 <<2), 32'h00000000);
  141. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd43 <<2), tmp);//`DENALI_PI_43_DATA
  142. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd43 <<2), 32'h01000000);
  143. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd43 <<2), tmp);//`DENALI_PI_43_DATA
  144. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd43 <<2), 32'h00000000);
  145. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd44 <<2), tmp);//`DENALI_PI_44_DATA
  146. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd44 <<2), 32'h00000101);
  147. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd146 <<2), tmp);//`DENALI_PI_146_DATA
  148. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd146 <<2), 32'h03031808);
  149. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd147 <<2), tmp);//`DENALI_PI_147_DATA
  150. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd147 <<2), 32'h03010303);
  151. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd147 <<2), tmp);//`DENALI_PI_147_DATA
  152. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd147 <<2), 32'h03030303);
  153. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd148 <<2), tmp);//`DENALI_PI_148_DATA
  154. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd148 <<2), 32'h03170a0a);
  155. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd149 <<2), tmp);//`DENALI_PI_149_DATA
  156. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd149 <<2), 32'h03000000);
  157. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd150 <<2), tmp);//`DENALI_PI_150_DATA
  158. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd150 <<2), 32'h03000000);
  159. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd43 <<2), tmp);//`DENALI_PI_43_DATA
  160. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd43 <<2), 32'h00000100);
  161. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd67 <<2), tmp);//`DENALI_PI_67_DATA
  162. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd67 <<2), 32'h01010300);
  163. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd68 <<2), tmp);//`DENALI_PI_68_DATA
  164. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd68 <<2), 32'h34000000);
  165. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd71 <<2), tmp);//`DENALI_PI_71_DATA
  166. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd71 <<2), 32'h01000000);
  167. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd71 <<2), tmp);//`DENALI_PI_71_DATA
  168. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd71 <<2), 32'h00000000);
  169. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd72 <<2), tmp);//`DENALI_PI_72_DATA
  170. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd72 <<2), 32'h00000100);
  171. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd180 <<2), tmp);//`DENALI_PI_180_DATA
  172. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd180 <<2), 32'h06000301);
  173. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd183 <<2), tmp);//`DENALI_PI_183_DATA
  174. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd183 <<2), 32'h01000301);
  175. apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd186 <<2), tmp);//`DENALI_PI_186_DATA
  176. apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd186 <<2), 32'h13000301);
  177. //cdns_rdlvl_gate_tr_init( 3,0,0,0,0);
  178. //cdns_rdlvl_tr_init( 3,0,0,0,0);
  179. //cdns_wdqlvl_tr_init( 3,0,0,0,0);
  180. apb_write(OMC_APB_BASE_ADDR + 32'h100, 32'h000000e0);
  181. apb_write(OMC_APB_BASE_ADDR + 32'h620, 32'h04031d22);
  182. apb_write(OMC_APB_BASE_ADDR + 32'h624, 32'h0c18080c);
  183. apb_write(OMC_APB_BASE_ADDR + 32'h628, 32'h60440c9d);
  184. apb_write(OMC_APB_BASE_ADDR + 32'h62c, 32'h34271140);//tRRD[12:8]>=0x10
  185. apb_write(OMC_APB_BASE_ADDR + 32'h630, 32'h36231c0e);
  186. apb_write(OMC_APB_BASE_ADDR + 32'h634, 32'h001e0000);
  187. apb_write(OMC_APB_BASE_ADDR + 32'h638, 32'h20171708);
  188. apb_write(OMC_APB_BASE_ADDR + 32'h63c, 32'h36420806);
  189. apb_write(OMC_APB_BASE_ADDR + 32'h640, 32'h01cf2cd6);//tXSR>=0x1CC(287.5ns_8gibx16);tXP+tmrri?
  190. apb_write(OMC_APB_BASE_ADDR + 32'h644, 32'h00e101c1);//lpddr4:tRFCpb>=0xe0,tRFCab>=0x1c0
  191. apb_write(OMC_APB_BASE_ADDR + 32'h648, 32'h00000000);
  192. apb_write(OMC_APB_BASE_ADDR + 32'h64c, 32'h000c351e);
  193. apb_write(OMC_APB_BASE_ADDR + 32'h650, 32'h20664713);
  194. apb_write(OMC_APB_BASE_ADDR + 32'h654, 32'h00002520);
  195. apb_write(OMC_APB_BASE_ADDR + 32'h658, 32'h00000060);
  196. apb_write(OMC_APB_BASE_ADDR + 32'h65c, 32'h00900030);
  197. apb_write(OMC_APB_BASE_ADDR + 32'h660, 32'h00000000);
  198. apb_write(OMC_APB_BASE_ADDR + 32'h680, 32'h16000416);
  199. apb_write(OMC_APB_BASE_ADDR + 32'h684, 32'h08000a04);
  200. apb_write(OMC_APB_BASE_ADDR + 32'h688, 32'h0415040a);
  201. apb_write(OMC_APB_BASE_ADDR + 32'h68c, 32'h20003320);
  202. apb_write(OMC_APB_BASE_ADDR + 32'h690, 32'h00140000);
  203. apb_write(OMC_APB_BASE_ADDR + 32'h69c, 32'h01240074);
  204. apb_write(OMC_APB_BASE_ADDR + 32'h6a0, 32'h00000000);
  205. apb_write(OMC_APB_BASE_ADDR + 32'h6a4, 32'h20330c00);
  206. apb_write(OMC_APB_BASE_ADDR + 32'h6a8, 32'h00040000);
  207. apb_write(OMC_APB_BASE_ADDR + 32'h4, 32'h30010056);
  208. apb_write(OMC_APB_BASE_ADDR + 32'hc, 32'h00000002);
  209. apb_write(OMC_APB_BASE_ADDR + 32'h4, 32'h3002002d);
  210. apb_write(OMC_APB_BASE_ADDR + 32'hc, 32'h00000002);
  211. apb_write(OMC_APB_BASE_ADDR + 32'h4, 32'h30030031);
  212. apb_write(OMC_APB_BASE_ADDR + 32'hc, 32'h00000002);
  213. apb_write(OMC_APB_BASE_ADDR + 32'h4, 32'h30160006);
  214. apb_write(OMC_APB_BASE_ADDR + 32'hc, 32'h00000002);
  215. apb_write(OMC_APB_BASE_ADDR + 32'h410, 32'h00101010);
  216. apb_write(OMC_APB_BASE_ADDR + 32'h420, 32'h0c181006);
  217. apb_write(OMC_APB_BASE_ADDR + 32'h424, 32'h20200820);
  218. apb_write(OMC_APB_BASE_ADDR + 32'h428, 32'h80000020);
  219. apb_write(OMC_APB_BASE_ADDR + 32'h0, 32'h00000001);
  220. apb_write(OMC_APB_BASE_ADDR + 32'h108, 32'h00003000);
  221. apb_write(OMC_SECURE_APB_BASE_ADDR + 32'h704, 32'h00000007);
  222. apb_write(OMC_APB_BASE_ADDR + 32'h330, 32'h09313fff);
  223. apb_write(OMC_APB_BASE_ADDR + 32'h508, 32'h00000033);
  224. apb_write(OMC_APB_BASE_ADDR + 32'h324, 32'h00002000);
  225. apb_write(OMC_APB_BASE_ADDR + 32'h104, 32'h90000000);
  226. apb_write(OMC_APB_BASE_ADDR + 32'h510, 32'h00000100);
  227. apb_write(OMC_APB_BASE_ADDR + 32'h514, 32'h00000000);
  228. apb_write(OMC_SECURE_APB_BASE_ADDR + 32'h700, 32'h00000003);
  229. apb_write(OMC_APB_BASE_ADDR + 32'h514, 32'h00000600);
  230. apb_write(OMC_APB_BASE_ADDR + 32'h20, 32'h00000001);
  231. //cdns_per_tr_longcnt_set( 16);
  232. // Initialization done