orbit_boot_training.C_r4 18 KB

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  1. // void inline orbit_writel(volatile void __iomem *addr, uint32_t data);
  2. // void inline orbit_readl_poll(volatile void __iomem *addr, uint32_t expected, uint32_t strobe);
  3. // void orbit_nsleep(int ns); // Sleep ns nano-seconds
  4. // void orbit_usleep(int us); // Sleep us micro-seconds
  5. //cdns_phy_initialize(1);
  6. apb_write(OMC_APB_BASE_ADDR + 0x0, 0x00000401);//ignore_phy_rresp=1(Ignore dfi_rddata_valid from PHY,Only used in booting period);dram type=LPDDR4
  7. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf00, 0x40001030);//enable address region 0; 2ranks; bit15?
  8. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf04, 0x00000001);//logic page size; 256bit interleaving
  9. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf10, 0x00800000);//region0_start //0x00800000
  10. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf14, 0x027fffff);//region0_end,SOC addr shift right 8bits //0x01ffffff
  11. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf18, 0x00000001);//2-channel interleaving
  12. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf30, 0x0f000031);//chip0:rank_size=128MB*(f+1)(2GB?);bg=0;row_width=16;col_width=10
  13. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf34, 0x0f000031);//chip1
  14. apb_write(OMC_SECURE_APB_BASE_ADDR + 0x110, 0xc0000001);//region0 attribute: allow secure write/read;enable security check for this region
  15. apb_write(OMC_SECURE_APB_BASE_ADDR + 0x114, 0xffffffff);//region0: [31:16]:nsaid_wr_en(allow non-secure write); [15:0]:nsaid_rd_en(allow non-secure read)
  16. apb_write(OMC_APB_BASE_ADDR + 0x10c, 0x00000505);//Temperature monitor reads to determine the maximum re-fresh interval
  17. apb_write(OMC_APB_BASE_ADDR + 0x11c, 0x00000000);//no register
  18. apb_write(OMC_APB_BASE_ADDR + 0x500, 0x00000201);//retimer_rddata; freq_ratio
  19. apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000100);//phymstr_ack_disable=1
  20. apb_write(OMC_APB_BASE_ADDR + 0x6a8, 0x00040000);//Keep OMC idle for additional idle_num_upd cycles (ACLK) after dfi_phyupd_ack assertion
  21. apb_write(OMC_APB_BASE_ADDR + 0xea8, 0x00040000);//Keep OMC idle for additional idle_num_upd cycles (ACLK) after dfi_phyupd_ack assertion
  22. // Memory frequency should be changed below 50MHz somewhere before here
  23. apb_write(OMC_APB_BASE_ADDR + 0x504, 0x40000000);//assert dfi_init_start
  24. //cdns_dll_rst_deassert()
  25. tmp = apb_read(OMC_APB_BASE_ADDR + 0x504);//wait for dfi_init_complete
  26. while((tmp & 0x80000000) != 0x80000000) {
  27. orbit_usleep(1);
  28. tmp = apb_read(OMC_APB_BASE_ADDR + 0x504);
  29. }
  30. apb_write(OMC_APB_BASE_ADDR + 0x504, 0x00000000);//de-assert dfi_init_start; de-assert dfi_ctrlupd_req on exit from self-refresh mode
  31. // tINIT0 is controlled by System
  32. apb_write(OMC_APB_BASE_ADDR + 0x50c, 0x00000000);//Drive DRAM_RST_N low
  33. // Waits tINIT1 (200 us): Minimum RESET_n LOW time after completion of voltage ramp
  34. orbit_usleep(200);
  35. apb_write(OMC_APB_BASE_ADDR + 0x50c, 0x00000001);//Drive DRAM_RST_N high
  36. // Waits tINIT3 (2 ms): Minimum CKE low time after RESET_n high
  37. orbit_usleep(2000);
  38. // Drive CKE high
  39. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x0000003c);//dram_command_cs: rank0/1; dram_command: power-down exit
  40. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);//dram_command_start
  41. // Waits tINIT5 (2 us): Minimum idle time before first MRW/MRR command
  42. orbit_usleep(2);
  43. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000010);//rank0; ZQ start/ZQ long calibration
  44. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
  45. // Waits tZQCAL (1 us)
  46. orbit_usleep(1);
  47. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000011);//rank0; ZQ latch/ZQ short calibration
  48. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
  49. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000020);//rank1; ZQ start/ZQ long calibration
  50. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
  51. // Waits tZQCAL (1 us)
  52. orbit_usleep(1);
  53. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000021);//rank1; ZQ latch/ZQ short calibration
  54. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
  55. apb_write(OMC_APB_BASE_ADDR + 0x310, 0x00020000);//dfs_dfi_frequency=2
  56. apb_write(OMC_APB_BASE_ADDR + 0x310, 0x00020001);//dfs_dfi_init_start_toggle; assert dfi_init_start when dfi_frequency change
  57. // Write down RCLK-related CRs
  58. apb_write(OMC_APB_BASE_ADDR + 0x600, 0x002e0176);//Per-bank(31:16)/all-bank(15:0) refresh interval in OSC clock cycles for each of eight MR4 values.
  59. apb_write(OMC_APB_BASE_ADDR + 0x604, 0x002e0176);
  60. apb_write(OMC_APB_BASE_ADDR + 0x608, 0x001700bb);
  61. apb_write(OMC_APB_BASE_ADDR + 0x60c, 0x000b005d);
  62. apb_write(OMC_APB_BASE_ADDR + 0x610, 0x0005002e);
  63. apb_write(OMC_APB_BASE_ADDR + 0x614, 0x00020017);
  64. apb_write(OMC_APB_BASE_ADDR + 0x618, 0x00020017);
  65. apb_write(OMC_APB_BASE_ADDR + 0x61c, 0x00020017);//Per-bank(31:16)/all-bank(15:0) refresh interval in OSC clock cycles for each of eight MR4 values.
  66. apb_write(OMC_APB_BASE_ADDR + 0x678, 0x00000019);//t_zqcal(lpddr4) >= 1us(12'h640)
  67. apb_write(OMC_APB_BASE_ADDR + 0x100, 0x000000fc);//abr_en[7:0]
  68. apb_write(OMC_APB_BASE_ADDR + 0x620, 0x03030404);//error: tCKCKEH(tCKSRX)>=3,tCMDCKE>=3,tRPpb(tRP)>=29,tRPab(tRP)>=34
  69. apb_write(OMC_APB_BASE_ADDR + 0x624, 0x04030505);//error: tCKE>=12,tSR(tCKESR)>=24,tCKELCK>=8,tXP>=12
  70. apb_write(OMC_APB_BASE_ADDR + 0x628, 0x07030884);
  71. apb_write(OMC_APB_BASE_ADDR + 0x62c, 0x13150401);
  72. apb_write(OMC_APB_BASE_ADDR + 0x630, 0x17150604);
  73. apb_write(OMC_APB_BASE_ADDR + 0x634, 0x000d0000);
  74. apb_write(OMC_APB_BASE_ADDR + 0x638, 0x200a0a08);
  75. apb_write(OMC_APB_BASE_ADDR + 0x63c, 0x173b0003);
  76. apb_write(OMC_APB_BASE_ADDR + 0x640, 0x00060c00);
  77. apb_write(OMC_APB_BASE_ADDR + 0x644, 0xa0030006);
  78. apb_write(OMC_APB_BASE_ADDR + 0x648, 0x00000000);
  79. apb_write(OMC_APB_BASE_ADDR + 0x64c, 0x00081306);
  80. apb_write(OMC_APB_BASE_ADDR + 0x650, 0x04070304);
  81. apb_write(OMC_APB_BASE_ADDR + 0x654, 0x00000404);
  82. apb_write(OMC_APB_BASE_ADDR + 0x658, 0x00000060);
  83. apb_write(OMC_APB_BASE_ADDR + 0x65c, 0x00020008);
  84. apb_write(OMC_APB_BASE_ADDR + 0x660, 0x00000000);
  85. apb_write(OMC_APB_BASE_ADDR + 0x680, 0x00000400);//DFI_timing
  86. apb_write(OMC_APB_BASE_ADDR + 0x684, 0x02000202);
  87. apb_write(OMC_APB_BASE_ADDR + 0x688, 0x04130409);
  88. apb_write(OMC_APB_BASE_ADDR + 0x68c, 0x20002420);
  89. apb_write(OMC_APB_BASE_ADDR + 0x690, 0x00140000);
  90. apb_write(OMC_APB_BASE_ADDR + 0x69c, 0x01240074);
  91. apb_write(OMC_APB_BASE_ADDR + 0x6a0, 0x03e80000);
  92. apb_write(OMC_APB_BASE_ADDR + 0x6a4, 0x20240c00);
  93. apb_write(OMC_APB_BASE_ADDR + 0x6a8, 0x00040000);
  94. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30010006);
  95. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  96. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30020000);
  97. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  98. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30030031);
  99. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  100. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30160006);
  101. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  102. apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000000);//phymstr_ack_disable=0
  103. tmp = apb_read(OMC_APB_BASE_ADDR + 0x518);//wait for dfi_phymstr_ack=1
  104. while((tmp & 0x00000002) != 0x00000002) {
  105. orbit_usleep(1);
  106. tmp = apb_read(OMC_APB_BASE_ADDR + 0x518);
  107. }
  108. //------ training start ------
  109. tmp = apb_read(OMC_APB_BASE_ADDR + 0x518);//wait for dfi_phymstr_ack=0
  110. while((tmp & 0x00000002) != 0x00000000) {
  111. tmp = apb_read(PHY_APB_BASE_ADDR + (0 +1 << 2)); //read freq_change_req_type
  112. if((tmp & 0x00000020) == 0x00000020) { //judge freq_change_req
  113. switch(tmp & 0x0000001f) { //judge freq_change_req_type
  114. case 0:
  115. if(ddr_num == 0) //ddrc_clock=12.5M
  116. _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrosc_div2_
  117. else
  118. _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrosc_div2_
  119. break;
  120. case 1:
  121. if(ddr_num == 0) //ddrc_clock=200M
  122. _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div8_
  123. else
  124. _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div8_
  125. break;
  126. case 2:
  127. if(ddr_num == 0) //ddrc_clock=800M
  128. _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div2_
  129. else
  130. _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div2_
  131. break;
  132. default:
  133. break;
  134. }
  135. apb_write(PHY_APB_BASE_ADDR + (0 +2 << 2), 0x01); //set freq_change_ack
  136. tmp = apb_read(PHY_APB_BASE_ADDR + (0 +2 << 2)); //read freq_change_ack
  137. while((tmp & 0x00000001) != 0x00000000) {
  138. tmp = apb_read(PHY_APB_BASE_ADDR + (0 +2 << 2)); //read freq_change_ack
  139. }
  140. }
  141. orbit_usleep(1);
  142. tmp = apb_read(OMC_APB_BASE_ADDR + 0x518); //read dfi_phymstr_ack
  143. }
  144. //------ training end --------
  145. tmp = apb_read(OMC_APB_BASE_ADDR + 0x518);//wait for dfi_phymstr_ack=0
  146. while((tmp & 0x00000002) != 0x00000000) {
  147. orbit_usleep(1);
  148. tmp = apb_read(OMC_APB_BASE_ADDR + 0x518);
  149. }
  150. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +11 <<2));//`DENALI_PI_11_DATA
  151. apb_write(PHY_APB_BASE_ADDR + (2048 +11 <<2), 0x03000803);//set PI_CS_MAP=3
  152. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +83 <<2));//`DENALI_PI_83_DATA //read PI_INT_STATUS=0be02001(lpddr4) is ok
  153. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +84 <<2));//`DENALI_PI_84_DATA
  154. apb_write(PHY_APB_BASE_ADDR + (2048 +84 <<2), 0x00000000); //clear the associated bit in the pi_init_status to 0
  155. //cdns_pi_en( 3);
  156. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +46 <<2));//`DENALI_PI_46_DATA
  157. apb_write(PHY_APB_BASE_ADDR + (2048 +46 <<2), 0x030f0000);//PI_RDLVL_GATE_CS_MAP=3
  158. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +33 <<2));//`DENALI_PI_33_DATA
  159. apb_write(PHY_APB_BASE_ADDR + (2048 +33 <<2), 0x00000000);//PI_RDLVL_GATE_REQ=0(don't trigger gate training)
  160. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +44 <<2));//`DENALI_PI_44_DATA
  161. apb_write(PHY_APB_BASE_ADDR + (2048 +44 <<2), 0x01000000);//PI_RDLVL_GATE_ON_SREF_EXIT=0(disable automatic gate training sequence at sref exit)
  162. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +44 <<2));//`DENALI_PI_44_DATA
  163. apb_write(PHY_APB_BASE_ADDR + (2048 +44 <<2), 0x00000000);//PI_RDLVL_GATE_ON_DPDX=0(disable automatic gate training sequence at dpd exit)
  164. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +45 <<2));//`DENALI_PI_45_DATA
  165. apb_write(PHY_APB_BASE_ADDR + (2048 +45 <<2), 0x00000001);//PI_RDLVL_GATE_DISABLE_DFS=1(disable automatic gate training sequence on dfs)
  166. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +146 <<2));//`DENALI_PI_146_DATA
  167. apb_write(PHY_APB_BASE_ADDR + (2048 +146 <<2), 0x03011808);//PI_RDLVL_GATE_EN_F0=3(enable post-/initalization rdlvl gate training for frq set 0)
  168. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +147 <<2));//`DENALI_PI_147_DATA
  169. apb_write(PHY_APB_BASE_ADDR + (2048 +147 <<2), 0x01010301);//PI_RDLVL_GATE_EN_F1=3(enable post-/initalization rdlvl gate training for frq set 1)
  170. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +147 <<2));//`DENALI_PI_147_DATA
  171. apb_write(PHY_APB_BASE_ADDR + (2048 +147 <<2), 0x03010301);//PI_RDLVL_GATE_EN_F2=3(enable post-/initalization rdlvl gate training for frq set 2)
  172. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +44 <<2));//`DENALI_PI_44_DATA
  173. apb_write(PHY_APB_BASE_ADDR + (2048 +44 <<2), 0x00000100);//PI_RDLVL_GATE_PERIODIC=1(subsequent gate training is tuning orther than full training)
  174. //cdns_rdlvl_gate_tr_init( 3,0,0,0,0);
  175. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +46 <<2));//`DENALI_PI_46_DATA
  176. apb_write(PHY_APB_BASE_ADDR + (2048 +46 <<2), 0x03030000);//PI_RDLVL_CS_MAP=3
  177. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +33 <<2));//`DENALI_PI_33_DATA
  178. apb_write(PHY_APB_BASE_ADDR + (2048 +33 <<2), 0x00000000);//PI_RDLVL_REQ=0(don't trigger data eye training)
  179. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +43 <<2));//`DENALI_PI_43_DATA
  180. apb_write(PHY_APB_BASE_ADDR + (2048 +43 <<2), 0x01000000);//PI_RDLVL_ON_SREF_EXIT=0(disable automatic eye training sequence at sref exit)
  181. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +43 <<2));//`DENALI_PI_43_DATA
  182. apb_write(PHY_APB_BASE_ADDR + (2048 +43 <<2), 0x00000000);//PI_RDLVL_ON_DPDX=0(disable automatic data eye training sequence at dpd exit)
  183. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +44 <<2));//`DENALI_PI_44_DATA
  184. apb_write(PHY_APB_BASE_ADDR + (2048 +44 <<2), 0x00000101);//PI_RDLVL_DISABLE_DFS=1(disable automatic eye training sequence on dfs)
  185. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +146 <<2));//`DENALI_PI_146_DATA
  186. apb_write(PHY_APB_BASE_ADDR + (2048 +146 <<2), 0x03031808);//PI_RDLVL_EN_F0=3(enable post-/initalization rdlvl eye training for frq set 0)
  187. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +147 <<2));//`DENALI_PI_147_DATA
  188. apb_write(PHY_APB_BASE_ADDR + (2048 +147 <<2), 0x03010303);//PI_RDLVL_EN_F1=3(enable post-/initalization rdlvl eye training for frq set 1)
  189. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +147 <<2));//`DENALI_PI_147_DATA
  190. apb_write(PHY_APB_BASE_ADDR + (2048 +147 <<2), 0x03030303);//PI_RDLVL_EN_F2=3(enable post-/initalization rdlvl eye training for frq set 2)
  191. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +148 <<2));//`DENALI_PI_148_DATA
  192. apb_write(PHY_APB_BASE_ADDR + (2048 +148 <<2), 0x03170a0a);//PI_RDLVL_PAT0_EN_F0=3(post-/initalization dfi_lvl_pattern==0 used for frq set 0)
  193. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +149 <<2));//`DENALI_PI_149_DATA
  194. apb_write(PHY_APB_BASE_ADDR + (2048 +149 <<2), 0x03000000);//PI_RDLVL_PAT0_EN_F0=3(post-/initalization dfi_lvl_pattern==0 used for frq set 1)
  195. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +150 <<2));//`DENALI_PI_150_DATA
  196. apb_write(PHY_APB_BASE_ADDR + (2048 +150 <<2), 0x03000000);//PI_RDLVL_PAT0_EN_F0=3(post-/initalization dfi_lvl_pattern==0 used for frq set 2)
  197. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +43 <<2));//`DENALI_PI_43_DATA
  198. apb_write(PHY_APB_BASE_ADDR + (2048 +43 <<2), 0x00000100);//PI_RDLVL_PERIODIC=1(subsequent eye training is tuning orther than full training)
  199. //cdns_rdlvl_tr_init( 3,0,0,0,0);
  200. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +67 <<2));//`DENALI_PI_67_DATA
  201. apb_write(PHY_APB_BASE_ADDR + (2048 +67 <<2), 0x01010300);//PI_WDQLVL_CS_MAP=3
  202. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +68 <<2));//`DENALI_PI_68_DATA
  203. apb_write(PHY_APB_BASE_ADDR + (2048 +68 <<2), 0x34000000);//PI_WDQLVL_REQ=0(don't trigger write dq training)
  204. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +71 <<2));//`DENALI_PI_71_DATA
  205. apb_write(PHY_APB_BASE_ADDR + (2048 +71 <<2), 0x01000000);//PI_WDQLVL_ON_SREF_EXIT(disable automatic write dq training sequence at sref exit)
  206. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +71 <<2));//`DENALI_PI_71_DATA
  207. apb_write(PHY_APB_BASE_ADDR + (2048 +71 <<2), 0x00000000);//PI_WDQLVL_ON_DPDX(disable automatic write dq training sequence at dpd exit)
  208. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +72 <<2));//`DENALI_PI_72_DATA
  209. apb_write(PHY_APB_BASE_ADDR + (2048 +72 <<2), 0x00000100);//PI_WDQLVL_DISABLE_DFS=1(disable automatic eye training sequence on dfs)
  210. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +180 <<2));//`DENALI_PI_180_DATA
  211. apb_write(PHY_APB_BASE_ADDR + (2048 +180 <<2), 0x06000301);//PI_WDQLVL_EN_F0=3(enable post-/initalization write dq training for frq set 0)
  212. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +183 <<2));//`DENALI_PI_183_DATA
  213. apb_write(PHY_APB_BASE_ADDR + (2048 +183 <<2), 0x01000301);//PI_WDQLVL_EN_F1=3(enable post-/initalization write dq training for frq set 1)
  214. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +186 <<2));//`DENALI_PI_186_DATA
  215. apb_write(PHY_APB_BASE_ADDR + (2048 +186 <<2), 0x13000301);//PI_WDQLVL_EN_F2=3(enable post-/initalization write dq training for frq set 2)
  216. //cdns_wdqlvl_tr_init( 3,0,0,0,0);
  217. apb_write(OMC_APB_BASE_ADDR + 0x100, 0x000000e0);//abr_en[7:5]
  218. apb_write(OMC_APB_BASE_ADDR + 0x620, 0x04031d22);//tCKCKEH(tCKSRX)>=3,tCMDCKE>=3,tRPpb(tRP)>=29,tRPab(tRP)>=34
  219. apb_write(OMC_APB_BASE_ADDR + 0x624, 0x0c18080c);//tCKE>=12,tSR(tCKESR)>=24,tCKELCK>=8,tXP>=12
  220. apb_write(OMC_APB_BASE_ADDR + 0x628, 0x60440c9d);//tRC>=(60||63)/tCK,tRAS>=44,tRTP>=12,adv_al=1,tRCD>=0x1d
  221. apb_write(OMC_APB_BASE_ADDR + 0x62c, 0x34271040);
  222. apb_write(OMC_APB_BASE_ADDR + 0x630, 0x36231c0e);
  223. apb_write(OMC_APB_BASE_ADDR + 0x634, 0x001e0000);
  224. apb_write(OMC_APB_BASE_ADDR + 0x638, 0x20171708);
  225. apb_write(OMC_APB_BASE_ADDR + 0x63c, 0x36420004);
  226. apb_write(OMC_APB_BASE_ADDR + 0x640, 0x01cf2cd6);//tXSR>=0x1CC(287.5ns_8gibx16);tXP+tmrri?
  227. apb_write(OMC_APB_BASE_ADDR + 0x644, 0x00e001c0);//tRFC>=0x230(350ns_8gib)
  228. apb_write(OMC_APB_BASE_ADDR + 0x648, 0x00000000);//tXSDLL,tXSfast>=0x110(170ns_8gib)
  229. apb_write(OMC_APB_BASE_ADDR + 0x64c, 0x000c351e);
  230. apb_write(OMC_APB_BASE_ADDR + 0x650, 0x20664713);
  231. apb_write(OMC_APB_BASE_ADDR + 0x654, 0x00002520);
  232. apb_write(OMC_APB_BASE_ADDR + 0x658, 0x00000060);
  233. apb_write(OMC_APB_BASE_ADDR + 0x65c, 0x00900030);
  234. apb_write(OMC_APB_BASE_ADDR + 0x660, 0x00000000);
  235. apb_write(OMC_APB_BASE_ADDR + 0x680, 0x16000416);//DFI_timing
  236. apb_write(OMC_APB_BASE_ADDR + 0x684, 0x08000a04);
  237. apb_write(OMC_APB_BASE_ADDR + 0x688, 0x0415040a);
  238. apb_write(OMC_APB_BASE_ADDR + 0x68c, 0x20003320);
  239. apb_write(OMC_APB_BASE_ADDR + 0x690, 0x00140000);
  240. apb_write(OMC_APB_BASE_ADDR + 0x69c, 0x01240074);
  241. apb_write(OMC_APB_BASE_ADDR + 0x6a0, 0x03e80000);
  242. apb_write(OMC_APB_BASE_ADDR + 0x6a4, 0x20330c00);
  243. apb_write(OMC_APB_BASE_ADDR + 0x6a8, 0x00040000);
  244. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30010056);//nWR=30,BL=on the fly
  245. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  246. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x3002002d);//WL/RL for 1333M~1600M
  247. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  248. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30030031);//PDDS=RZQ/6,PU-CAl=VDDQ/3(default)
  249. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  250. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30160006);//soc_ODT=RZQ/6
  251. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  252. apb_write(OMC_APB_BASE_ADDR + 0x410, 0x00101010);//generation/urgent<->oldest request
  253. apb_write(OMC_APB_BASE_ADDR + 0x420, 0x0c181006);
  254. apb_write(OMC_APB_BASE_ADDR + 0x424, 0x20200820);
  255. apb_write(OMC_APB_BASE_ADDR + 0x428, 0x80000020);
  256. apb_write(OMC_APB_BASE_ADDR + 0x0, 0x00000001);//ignore_phy_rresp=0(Ignore dfi_rddata_valid from PHY,Only used in booting period);dram type=LPDDR4
  257. apb_write(OMC_APB_BASE_ADDR + 0x108, 0x00003000);
  258. apb_write(OMC_APB_BASE_ADDR + 0x508, 0x00000033);
  259. apb_write(OMC_APB_BASE_ADDR + 0x324, 0x8000a000);//enable dynamic DRAM power down/self-refresh;aref_between_srefs
  260. apb_write(OMC_APB_BASE_ADDR + 0x104, 0x90000000);//Enable auto-refresh;Opportunistic selection of target bank refresh to reduce bank confliction
  261. apb_write(OMC_APB_BASE_ADDR + 0x510, 0x00000100);//Issue {num_phyupd_abr} number of all-bank-refresh commands before ac-knowledging phyupd_req.
  262. apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000000);//phymstr_ack_disable=0
  263. apb_write(OMC_SECURE_APB_BASE_ADDR + 0x700, 0x00000003);//CR_UPDATE_CTRL
  264. apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000600);//Wait dfi_phymstr_* handshake after (POWER Gating mode/DFS completed) exited
  265. apb_write(OMC_APB_BASE_ADDR + 0x20, 0x00000001);//DRAM_INIT_DONE
  266. // Initialization done