gpio.c 2.8 KB

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  1. /**
  2. ******************************************************************************
  3. * @file gpio.c
  4. * @author StarFive Technology
  5. * @version V1.0
  6. * @date 08/13/2020
  7. * @brief
  8. ******************************************************************************
  9. * @copy
  10. *
  11. * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  12. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  13. * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
  14. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  15. * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  16. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  17. *
  18. * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
  19. */
  20. #include "gpio.h"
  21. #include <sys.h>
  22. //#include <ezGPIO_fullMux_ctrl_macro.h>
  23. #include <clkgen_ctrl_macro.h>
  24. #include <rstgen_ctrl_macro.h>
  25. #define GPIO_EN (0x0)
  26. #define GPIO_IS_LOW (0x10) //select level or edge trigge
  27. #define GPIO_IS_HIGH (0x14)
  28. #define GPIO_IBE_LOW (0x18) //interrupt both edge trigger 1:both, 0:disable both
  29. #define GPIO_IBE_HIGH (0x1c)
  30. #define GPIO_IEV_LOW (0x20) //trigger condition 1:rising, 0 falling
  31. #define GPIO_IEV_HIGH (0x24)
  32. #define GPIO_IE_LOW (0x28) //interrupt enable
  33. #define GPIO_IE_HIGH (0x2c)
  34. #define GPIO_IC_LOW (0x30) //interrupt clear
  35. #define GPIO_IC_HIGH (0x34)
  36. //read only
  37. #define GPIO_RIS_LOW (0x38) //raw interrupt
  38. #define GPIO_RIS_HIGH (0x3c)
  39. #define GPIO_MIS_LOW (0x40) //masked interrupt
  40. #define GPIO_MIS_HIGH (0x44)
  41. #define GPIO_DIN_LOW (0x48) //data in
  42. #define GPIO_DIN_HIGH (0x4c)
  43. static inline void gpio_write_reg(unsigned long base, unsigned long addr, unsigned int val)
  44. {
  45. writel(val, (volatile void *)(base + addr));
  46. }
  47. static inline unsigned int gpio_read_reg(unsigned long base, unsigned long addr)
  48. {
  49. return readl((volatile void *)(base + addr));
  50. }
  51. void gpio_enable(int enable)
  52. {
  53. if(enable == 0)
  54. gpio_write_reg(EZGPIO_FULLMUX_BASE_ADDR, GPIO_EN, 0);
  55. else
  56. gpio_write_reg(EZGPIO_FULLMUX_BASE_ADDR, GPIO_EN, 1);
  57. }
  58. int gpio_get_val(int gpio_num)
  59. {
  60. int value = 0;
  61. if(gpio_num < 32)
  62. {
  63. value = gpio_read_reg(EZGPIO_FULLMUX_BASE_ADDR, GPIO_DIN_LOW);
  64. return (value >> gpio_num) & 0x1;
  65. }
  66. else
  67. {
  68. value = gpio_read_reg(EZGPIO_FULLMUX_BASE_ADDR, GPIO_DIN_HIGH);
  69. return (value >> (gpio_num - 32)) & 0x1;
  70. }
  71. }
  72. int get_boot_mode()
  73. {
  74. int boot_mode = 0;
  75. boot_mode = gpio_get_val(BOOT_GPIO_60);
  76. boot_mode |= (gpio_get_val(BOOT_GPIO_61) << 1);
  77. boot_mode |= (gpio_get_val(BOOT_GPIO_62) << 2);
  78. return boot_mode;
  79. }
  80. void gpio_init(void)
  81. {
  82. _ENABLE_CLOCK_clk_gpio_apb_;
  83. _ASSERT_RESET_rstgen_rstn_gpio_apb_;
  84. _CLEAR_RESET_rstgen_rstn_gpio_apb_;
  85. gpio_enable(1);
  86. }